From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 8BDA2FE5 for ; Wed, 15 Apr 2015 17:09:43 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 15 Apr 2015 08:09:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,582,1422950400"; d="scan'208,217";a="709515605" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga002.fm.intel.com with ESMTP; 15 Apr 2015 08:09:40 -0700 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.2]) by IRSMSX102.ger.corp.intel.com ([169.254.2.2]) with mapi id 14.03.0224.002; Wed, 15 Apr 2015 16:09:39 +0100 From: "Kavanagh, Mark B" To: "dev@dpdk.org" Thread-Topic: Minimum Supported x86 microarchitecture Thread-Index: AdB3jTKY7vK6E6MCTEmtvngTL0yxgQ== Date: Wed, 15 Apr 2015 15:09:39 +0000 Message-ID: Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-dev] Minimum Supported x86 microarchitecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Apr 2015 15:09:44 -0000 Hi, The recent reimplementation of rte_memcpy in DPDK v2.0.0 seems to have a pl= aced an implicit floor on the microarchitecture/Instruction set supported b= y DPDK. For example, I can't compile head of OVS against DPDK 2.0 with gcc without = passing the 'msse3' flag; this points to an implicit minimum supported CPU= of 'core2'. More discussion on same is available here: http://openvswitch.= org/pipermail/dev/2015-April/053523.html Can anyone confirm or deny this, and is/should it be documented? Thanks in advance, Mark