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Mon, 29 Sep 2025 19:53:13 +0000 From: "Shetty, Praveen" To: "Richardson, Bruce" CC: "Singh, Aman Deep" , "dev@dpdk.org" , "Shukla, Dhananjay" , "Patel, Atul" Subject: RE: [PATCH v3 3/4] net/intel: add config queue support to vCPF Thread-Topic: [PATCH v3 3/4] net/intel: add config queue support to vCPF Thread-Index: AQHcLG0eTTSZzwEpeUW7P41XX21gTLSqNF8AgABYNdA= Date: Mon, 29 Sep 2025 19:53:13 +0000 Message-ID: References: <20250922141058.1390212-2-praveen.shetty@intel.com> <20250923125455.1484992-1-praveen.shetty@intel.com> <20250923125455.1484992-4-praveen.shetty@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DM3PPF291EF9BF1:EE_|MW6PR11MB8412:EE_ x-ms-office365-filtering-correlation-id: 4dac1610-e6fe-4a98-0faa-08ddff91d322 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM3PPF291EF9BF1.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4dac1610-e6fe-4a98-0faa-08ddff91d322 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2025 19:53:13.3965 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 66djUILi4Bp1WvXglKNkBrVfjnW/mGQrVybQ2gknaC6Vq5xwuTdFDz5xKm+b/AbwVfHqaPgGdC4jmDGNCBvtqF6kb3LuSgWyTFpCvwoUHBs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR11MB8412 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Tue, Sep 23, 2025 at 02:54:54PM +0200, Shetty, Praveen wrote: > From: Praveen Shetty >=20 > A "configuration queue" is a software term to denote a hardware=20 > mailbox queue dedicated to NSS programming. > While the hardware does not have a construct of a "configuration=20 > queue", software does to state clearly the distinction between a queue=20 > software dedicates to regular mailbox processing (e.g. CPChnl or=20 > Virtchnl) and a queue software dedicates to NSS programming (e.g.=20 > SEM/LEM rule programming). >=20 Please provide expansions or clarifications for the acronyms used in the co= mmit message, so that the commit log is understandable for those unaware of= what the NSS is, or what SEM/LEM refers to. As far as I know, these are no= t generally known terms in the industry. >> Sure - will address this in v4. Also, you say that the hardware doesn't have a config queue, but software d= oes - I think that needs a bit of explanation as to what exactly the patch= is doing/implementing? How is software providing a special config queue if= the facility is not provided by HW. >> From the HW perspective, both mailbox and the config queues are "control= " queues. >> For HW, "opcode" in the queue descriptor is one of the key differentiati= ng factors between mailbox queues and the config queues(operation code is d= ifferent for mailbox queues and the config queues). >> Mailbox queues are used for Virtchnl and the CPChnl communication betwee= n the driver and the FW. >> Config queues are used for programming the FXP pipeline(Flexible packet = processor). >> This patch will request for the queues from the fw using add_queue virtc= hnl message and configures it as a config queue. >> vCPF driver will then use this config queues to program the FXP pipeline= using rte_flow. >> will add this information in the v4. > Signed-off-by: Praveen Shetty > Tested-by: Dhananjay Shukla > Tested-by: Atul Patel > --- Couple of small comments inline below. /Bruce > drivers/net/intel/cpfl/cpfl_ethdev.c | 274 +++++++++++++++--- > drivers/net/intel/cpfl/cpfl_ethdev.h | 38 ++- > drivers/net/intel/cpfl/cpfl_vchnl.c | 143 ++++++++- > drivers/net/intel/idpf/base/idpf_osdep.h | 3 + > drivers/net/intel/idpf/base/virtchnl2.h | 3 +- > drivers/net/intel/idpf/idpf_common_device.h | 2 + > drivers/net/intel/idpf/idpf_common_virtchnl.c | 38 +++ > drivers/net/intel/idpf/idpf_common_virtchnl.h | 3 + > 8 files changed, 449 insertions(+), 55 deletions(-) >=20 > diff --git a/drivers/net/intel/cpfl/cpfl_ethdev.c=20 > b/drivers/net/intel/cpfl/cpfl_ethdev.c > index d6227c99b5..c411a2a024 100644 > --- a/drivers/net/intel/cpfl/cpfl_ethdev.c > +++ b/drivers/net/intel/cpfl/cpfl_ethdev.c > @@ -29,6 +29,9 @@ > #define CPFL_FLOW_PARSER "flow_parser" > #endif > =20 > +#define VCPF_FID 0 > +#define CPFL_FID 6 > + > rte_spinlock_t cpfl_adapter_lock; > /* A list for all adapters, one adapter matches one PCI device */ =20 > struct cpfl_adapter_list cpfl_adapter_list; @@ -1699,7 +1702,8 @@=20 > cpfl_handle_vchnl_event_msg(struct cpfl_adapter_ext *adapter, uint8_t *ms= g, uint > } > =20 > /* ignore if it is ctrl vport */ > - if (adapter->ctrl_vport.base.vport_id =3D=3D vc_event->vport_id) > + if (adapter->base.hw.device_id =3D=3D IDPF_DEV_ID_CPF && > + adapter->ctrl_vport.base.vport_id =3D=3D vc_event->vport_id) > return; > =20 > vport =3D cpfl_find_vport(adapter, vc_event->vport_id); @@ -1903,18=20 > +1907,30 @@ cpfl_stop_cfgqs(struct cpfl_adapter_ext *adapter) { > int i, ret; > =20 > - for (i =3D 0; i < CPFL_TX_CFGQ_NUM; i++) { > - ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, false, fals= e, > + for (i =3D 0; i < adapter->num_tx_cfgq; i++) { > + if (adapter->base.hw.device_id =3D=3D IXD_DEV_ID_VCPF) > + ret =3D idpf_vc_ena_dis_one_queue_vcpf(&adapter->base, > + adapter->cfgq_info[0].id, > + VIRTCHNL2_QUEUE_TYPE_CONFIG_TX, false); > + else > + ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, false,=20 > +false, > VIRTCHNL2_QUEUE_TYPE_CONFIG_TX); > + > if (ret) { > PMD_DRV_LOG(ERR, "Fail to disable Tx config queue."); > return ret; > } > } > =20 > - for (i =3D 0; i < CPFL_RX_CFGQ_NUM; i++) { > - ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, true, false= , > - VIRTCHNL2_QUEUE_TYPE_CONFIG_RX); > + for (i =3D 0; i < adapter->num_rx_cfgq; i++) { > + if (adapter->base.hw.device_id =3D=3D IXD_DEV_ID_VCPF) > + ret =3D idpf_vc_ena_dis_one_queue_vcpf(&adapter->base, > + adapter->cfgq_info[1].id, > + VIRTCHNL2_QUEUE_TYPE_CONFIG_RX, false); > + else > + ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, true, fals= e, > + VIRTCHNL2_QUEUE_TYPE_CONFIG_RX); > + > if (ret) { > PMD_DRV_LOG(ERR, "Fail to disable Rx config queue."); > return ret; > @@ -1922,6 +1938,7 @@ cpfl_stop_cfgqs(struct cpfl_adapter_ext *adapter) > } > =20 > return 0; > + > } > =20 > static int > @@ -1941,8 +1958,13 @@ cpfl_start_cfgqs(struct cpfl_adapter_ext *adapter) > return ret; > } > =20 > - for (i =3D 0; i < CPFL_TX_CFGQ_NUM; i++) { > - ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, false, true= , > + for (i =3D 0; i < adapter->num_tx_cfgq; i++) { > + if (adapter->base.hw.device_id =3D=3D IXD_DEV_ID_VCPF) > + ret =3D idpf_vc_ena_dis_one_queue_vcpf(&adapter->base, > + adapter->cfgq_info[0].id, > + VIRTCHNL2_QUEUE_TYPE_CONFIG_TX, true); > + else > + ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, false,=20 > +true, > VIRTCHNL2_QUEUE_TYPE_CONFIG_TX); > if (ret) { > PMD_DRV_LOG(ERR, "Fail to enable Tx config queue."); @@ -1950,8=20 > +1972,13 @@ cpfl_start_cfgqs(struct cpfl_adapter_ext *adapter) > } > } > =20 > - for (i =3D 0; i < CPFL_RX_CFGQ_NUM; i++) { > - ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, true, true, > + for (i =3D 0; i < adapter->num_rx_cfgq; i++) { > + if (adapter->base.hw.device_id =3D=3D IXD_DEV_ID_VCPF) > + ret =3D idpf_vc_ena_dis_one_queue_vcpf(&adapter->base, > + adapter->cfgq_info[1].id, > + VIRTCHNL2_QUEUE_TYPE_CONFIG_RX, true); > + else > + ret =3D idpf_vc_queue_switch(&adapter->ctrl_vport.base, i, true,=20 > +true, > VIRTCHNL2_QUEUE_TYPE_CONFIG_RX); > if (ret) { > PMD_DRV_LOG(ERR, "Fail to enable Rx config queue."); @@ -1971,14=20 > +1998,20 @@ cpfl_remove_cfgqs(struct cpfl_adapter_ext *adapter) > =20 > create_cfgq_info =3D adapter->cfgq_info; > =20 > - for (i =3D 0; i < CPFL_CFGQ_NUM; i++) { > - if (adapter->ctlqp[i]) > + for (i =3D 0; i < adapter->num_cfgq; i++) { > + if (adapter->ctlqp[i]) { > cpfl_vport_ctlq_remove(hw, adapter->ctlqp[i]); > + adapter->ctlqp[i] =3D NULL; > + } > if (create_cfgq_info[i].ring_mem.va) > idpf_free_dma_mem(&adapter->base.hw, &create_cfgq_info[i].ring_mem); > if (create_cfgq_info[i].buf_mem.va) > idpf_free_dma_mem(&adapter->base.hw, &create_cfgq_info[i].buf_mem); > } > + if (adapter->ctlqp) { > + rte_free(adapter->ctlqp); > + adapter->ctlqp =3D NULL; > + } > } > =20 > static int > @@ -1988,7 +2021,16 @@ cpfl_add_cfgqs(struct cpfl_adapter_ext *adapter) > int ret =3D 0; > int i =3D 0; > =20 > - for (i =3D 0; i < CPFL_CFGQ_NUM; i++) { > + adapter->ctlqp =3D rte_zmalloc("ctlqp", adapter->num_cfgq * > + sizeof(struct idpf_ctlq_info *), > + RTE_CACHE_LINE_SIZE); > + > + if (!adapter->ctlqp) { > + PMD_DRV_LOG(ERR, "Failed to allocate memory for control queues"); > + return -ENOMEM; > + } > + > + for (i =3D 0; i < adapter->num_cfgq; i++) { > cfg_cq =3D NULL; > ret =3D cpfl_vport_ctlq_add((struct idpf_hw *)(&adapter->base.hw), > &adapter->cfgq_info[i], > @@ -2007,6 +2049,62 @@ cpfl_add_cfgqs(struct cpfl_adapter_ext *adapter) > return ret; > } > =20 > +static > +int vcpf_save_chunk_in_cfgq(struct cpfl_adapter_ext *adapter) { > + struct virtchnl2_add_queues *add_q =3D > + (struct virtchnl2_add_queues *)adapter->addq_recv_info; > + struct vcpf_cfg_queue *cfgq; > + struct virtchnl2_queue_reg_chunk *q_chnk; > + u16 rx, tx, num_chunks, num_q, struct_size; > + u32 q_id, q_type; > + > + rx =3D 0; tx =3D 0; > + > + cfgq =3D rte_zmalloc("cfgq", adapter->num_cfgq * > + sizeof(struct vcpf_cfg_queue), > + RTE_CACHE_LINE_SIZE); > + I suspect you can probably fix both sides of the multiply on a single line = here, and still be within 100 chars. That will mak ethe code slightly easie= r to read. >> Thanks, will address this in v4. > + if (!cfgq) { > + PMD_DRV_LOG(ERR, "Failed to allocate memory for cfgq"); > + return -ENOMEM; > + } > + > + struct_size =3D idpf_struct_size(add_q, chunks.chunks, (add_q->chunks.n= um_chunks - 1)); > + adapter->cfgq_in.cfgq_add =3D rte_zmalloc("config_queues",=20 > +struct_size, 0); Missing check for a failed zmalloc call. >> thanks, will address this in v4. > + rte_memcpy(adapter->cfgq_in.cfgq_add, add_q, struct_size); > + > + num_chunks =3D add_q->chunks.num_chunks; > + for (u16 i =3D 0; i < num_chunks; i++) { > + num_q =3D add_q->chunks.chunks[i].num_queues; > + q_chnk =3D &add_q->chunks.chunks[i]; > + for (u16 j =3D 0; j < num_q; j++) { > + if (rx > adapter->num_cfgq || tx > adapter->num_cfgq) > + break; > + q_id =3D q_chnk->start_queue_id + j; > + q_type =3D q_chnk->type; > + if (q_type =3D=3D VIRTCHNL2_QUEUE_TYPE_MBX_TX) { > + cfgq[0].qid =3D q_id; > + cfgq[0].qtail_reg_start =3D q_chnk->qtail_reg_start; > + cfgq[0].qtail_reg_spacing =3D q_chnk->qtail_reg_spacing; > + q_chnk->type =3D VIRTCHNL2_QUEUE_TYPE_CONFIG_TX; > + tx++; > + } else if (q_type =3D=3D VIRTCHNL2_QUEUE_TYPE_MBX_RX) { > + cfgq[1].qid =3D q_id; > + cfgq[1].qtail_reg_start =3D q_chnk->qtail_reg_start; > + cfgq[1].qtail_reg_spacing =3D q_chnk->qtail_reg_spacing; > + q_chnk->type =3D VIRTCHNL2_QUEUE_TYPE_CONFIG_RX; > + rx++; > + } > + } > + } > +