[PATCH 0/8] Fixes for Intel common rx/tx path selection

[PATCH 0/8] Fixes for Intel common rx/tx path selection

[Ciara Loftus]

An issue exists with the way Rx and Tx paths are defined and then used
by the common selection infrastructure, which in some cases means not
all paths are available for selection. The issue affects four drivers on
both Rx and Tx paths resulting in eight fix patches.

Depending on the underlying architecture and CPU flags available, a
different set of paths are defined for each driver. The path selection
function iterates sequentially from zero to num_paths where num_paths is
the size of the array as determined by the RTE_DIM macro. However,
depending on the platform, some of these entries may be empty, and valid
entries at the end of the array may never be considered in the selection
function. Fix this by editing each driver's rx/tx "func_type" enum and
only defining a value for the path if it is implemented in the driver's
rx/tx "path_infos" array.

The fixes for the Tx paths can be squashed into the next-net-intel tree
as the commits that those fixes target have not yet made it into the
main branch. The fixes for the Rx paths can be squashed into one commit
if that's a more desirable approach, since the commit messages of them
all are essentially the same but for the driver name. The generic
version is the paragraph above.

Ciara Loftus (8):
  net/i40e: ensure all Tx paths are selectable
  net/iavf: ensure all Tx paths are selectable
  net/ice: ensure all Tx paths are selectable
  net/idpf: ensure all Tx paths are selectable
  net/i40e: ensure all Rx paths are selectable
  net/iavf: ensure all Rx paths are selectable
  net/ice: ensure all Rx paths are selectable
  net/idpf: ensure all Rx paths are selectable

 drivers/net/intel/i40e/i40e_ethdev.h        | 12 ++++++++++++
 drivers/net/intel/i40e/i40e_rxtx.c          |  8 ++++++--
 drivers/net/intel/iavf/iavf.h               | 10 ++++++++++
 drivers/net/intel/ice/ice_ethdev.h          |  8 ++++++++
 drivers/net/intel/idpf/idpf_common_device.h |  8 ++++++++
 5 files changed, 44 insertions(+), 2 deletions(-)

-- 
2.43.0

[PATCH 1/8] net/i40e: ensure all Tx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Tx paths are defined. The Tx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the i40e_tx_func_type enum and only defining a value
for the Tx path if it is implemented in the i40e_tx_path_infos array.

Fixes: dc9c426f991f ("net/i40e: use common Tx path selection infrastructure")

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/i40e/i40e_ethdev.h | 6 ++++++
 drivers/net/intel/i40e/i40e_rxtx.c   | 8 ++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/intel/i40e/i40e_ethdev.h b/drivers/net/intel/i40e/i40e_ethdev.h
index 1fe504d0cd..c3240be960 100644
--- a/drivers/net/intel/i40e/i40e_ethdev.h
+++ b/drivers/net/intel/i40e/i40e_ethdev.h
@@ -1246,11 +1246,17 @@ enum i40e_rx_func_type {
 enum i40e_tx_func_type {
 	I40E_TX_DEFAULT,
 	I40E_TX_SCALAR_SIMPLE,
+#ifdef RTE_ARCH_X86
 	I40E_TX_SSE,
 	I40E_TX_AVX2,
+#ifdef CC_AVX512_SUPPORT
 	I40E_TX_AVX512,
+#endif
+#elif defined(RTE_ARCH_ARM64)
 	I40E_TX_NEON,
+#elif defined(RTE_ARCH_PPC_64)
 	I40E_TX_ALTIVEC,
+#endif
 };
 
 /*
diff --git a/drivers/net/intel/i40e/i40e_rxtx.c b/drivers/net/intel/i40e/i40e_rxtx.c
index a7d80e2bc0..f3c9d41686 100644
--- a/drivers/net/intel/i40e/i40e_rxtx.c
+++ b/drivers/net/intel/i40e/i40e_rxtx.c
@@ -3626,10 +3626,14 @@ i40e_set_tx_function(struct rte_eth_dev *dev)
 		i40e_tx_path_infos[ad->tx_func_type].info, dev->data->port_id);
 
 	if (ad->tx_func_type == I40E_TX_SCALAR_SIMPLE ||
+#ifdef RTE_ARCH_X86
 			ad->tx_func_type == I40E_TX_SSE ||
-			ad->tx_func_type == I40E_TX_NEON ||
-			ad->tx_func_type == I40E_TX_ALTIVEC ||
 			ad->tx_func_type == I40E_TX_AVX2)
+#elif defined(RTE_ARCH_ARM64)
+			ad->tx_func_type == I40E_TX_NEON)
+#elif defined(RTE_ARCH_PPC_64)
+			ad->tx_func_type == I40E_TX_ALTIVEC)
+#endif
 		dev->recycle_tx_mbufs_reuse = i40e_recycle_tx_mbufs_reuse_vec;
 }
 
-- 
2.43.0

[PATCH 2/8] net/iavf: ensure all Tx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Tx paths are defined. The Tx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the iavf_tx_func_type enum and only defining a value
for the Tx path if it is implemented in the iavf_tx_path_infos array.

Fixes: d89b61bed380 ("net/iavf: use common Tx path selection infrastructure")

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/iavf/iavf.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/iavf/iavf.h b/drivers/net/intel/iavf/iavf.h
index 921bf0a607..35d3bd5671 100644
--- a/drivers/net/intel/iavf/iavf.h
+++ b/drivers/net/intel/iavf/iavf.h
@@ -353,13 +353,17 @@ enum iavf_rx_func_type {
 enum iavf_tx_func_type {
 	IAVF_TX_DISABLED,
 	IAVF_TX_DEFAULT,
+#ifdef RTE_ARCH_X86
 	IAVF_TX_SSE,
 	IAVF_TX_AVX2,
 	IAVF_TX_AVX2_OFFLOAD,
+#ifdef CC_AVX512_SUPPORT
 	IAVF_TX_AVX512,
 	IAVF_TX_AVX512_OFFLOAD,
 	IAVF_TX_AVX512_CTX,
 	IAVF_TX_AVX512_CTX_OFFLOAD,
+#endif
+#endif
 };
 
 #define IAVF_MBUF_CHECK_F_TX_MBUF        (1ULL << 0)
-- 
2.43.0

[PATCH 3/8] net/ice: ensure all Tx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Tx paths are defined. The Tx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the ice_tx_func_type enum and only defining a value
for the Tx path if it is implemented in the ice_tx_path_infos array.

Fixes: 058abc74f380 ("net/ice: use common Tx path selection infrastructure")

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/ice/ice_ethdev.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/ice/ice_ethdev.h b/drivers/net/intel/ice/ice_ethdev.h
index a2379a68c2..d1d31760d5 100644
--- a/drivers/net/intel/ice/ice_ethdev.h
+++ b/drivers/net/intel/ice/ice_ethdev.h
@@ -211,11 +211,15 @@ enum ice_rx_func_type {
 enum ice_tx_func_type {
 	ICE_TX_DEFAULT,
 	ICE_TX_SIMPLE,
+#ifdef RTE_ARCH_X86
 	ICE_TX_SSE,
 	ICE_TX_AVX2,
 	ICE_TX_AVX2_OFFLOAD,
+#ifdef CC_AVX512_SUPPORT
 	ICE_TX_AVX512,
 	ICE_TX_AVX512_OFFLOAD,
+#endif
+#endif
 };
 
 struct ice_adapter;
-- 
2.43.0

[PATCH 4/8] net/idpf: ensure all Tx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Tx paths are defined. The Tx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the idpf_tx_func_type enum and only defining a value
for the Tx path if it is implemented in the idpf_tx_path_infos array.

Fixes: 04bb7e425614 ("net/idpf: use common Tx path selection infrastructure")

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/idpf/idpf_common_device.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/idpf/idpf_common_device.h b/drivers/net/intel/idpf/idpf_common_device.h
index 31915a03d4..9d3f35176d 100644
--- a/drivers/net/intel/idpf/idpf_common_device.h
+++ b/drivers/net/intel/idpf/idpf_common_device.h
@@ -78,9 +78,13 @@ enum idpf_rx_func_type {
 enum idpf_tx_func_type {
 	IDPF_TX_DEFAULT,
 	IDPF_TX_SINGLEQ,
+#ifdef RTE_ARCH_X86
 	IDPF_TX_SINGLEQ_AVX2,
+#ifdef CC_AVX512_SUPPORT
 	IDPF_TX_AVX512,
 	IDPF_TX_SINGLEQ_AVX512,
+#endif
+#endif
 	/* Need a max value defined as array values in are defined
 	 * in a C file in idpf driver, but cpfl driver needs to reuse
 	 * that array and know the size
-- 
2.43.0

[PATCH 5/8] net/i40e: ensure all Rx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Rx paths are defined. The Rx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the i40e_rx_func_type enum and only defining a value
for the Rx path if it is implemented in the i40e_rx_path_infos array.

Fixes: 3f24891594c1 ("net/i40e: use common Rx path selection infrastructure")
Cc: stable@dpdk.org

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/i40e/i40e_ethdev.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/intel/i40e/i40e_ethdev.h b/drivers/net/intel/i40e/i40e_ethdev.h
index c3240be960..6d729f6ae9 100644
--- a/drivers/net/intel/i40e/i40e_ethdev.h
+++ b/drivers/net/intel/i40e/i40e_ethdev.h
@@ -1231,16 +1231,22 @@ enum i40e_rx_func_type {
 	I40E_RX_DEFAULT,
 	I40E_RX_SCATTERED,
 	I40E_RX_BULK_ALLOC,
+#ifdef RTE_ARCH_X86
 	I40E_RX_SSE,
 	I40E_RX_SSE_SCATTERED,
 	I40E_RX_AVX2,
 	I40E_RX_AVX2_SCATTERED,
+#ifdef CC_AVX512_SUPPORT
 	I40E_RX_AVX512,
 	I40E_RX_AVX512_SCATTERED,
+#endif
+#elif defined(RTE_ARCH_ARM64)
 	I40E_RX_NEON,
 	I40E_RX_NEON_SCATTERED,
+#elif defined(RTE_ARCH_PPC_64)
 	I40E_RX_ALTIVEC,
 	I40E_RX_ALTIVEC_SCATTERED,
+#endif
 };
 
 enum i40e_tx_func_type {
-- 
2.43.0

[PATCH 6/8] net/iavf: ensure all Rx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Rx paths are defined. The Rx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the iavf_rx_func_type enum and only defining a value
for the Rx path if it is implemented in the iavf_rx_path_infos array.

Fixes: 91e3205d72d8 ("net/iavf: use common Rx path selection infrastructure")
Cc: stable@dpdk.org

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/iavf/iavf.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/intel/iavf/iavf.h b/drivers/net/intel/iavf/iavf.h
index 35d3bd5671..53c036c0e8 100644
--- a/drivers/net/intel/iavf/iavf.h
+++ b/drivers/net/intel/iavf/iavf.h
@@ -328,7 +328,10 @@ enum iavf_rx_func_type {
 	IAVF_RX_SCATTERED_FLEX_RXD,
 	IAVF_RX_BULK_ALLOC,
 	IAVF_RX_BULK_ALLOC_FLEX_RXD,
+#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM)
 	IAVF_RX_SSE,
+#endif
+#ifdef RTE_ARCH_X86
 	IAVF_RX_SSE_SCATTERED,
 	IAVF_RX_SSE_FLEX_RXD,
 	IAVF_RX_SSE_SCATTERED_FLEX_RXD,
@@ -340,6 +343,7 @@ enum iavf_rx_func_type {
 	IAVF_RX_AVX2_SCATTERED_FLEX_RXD,
 	IAVF_RX_AVX2_FLEX_RXD_OFFLOAD,
 	IAVF_RX_AVX2_SCATTERED_FLEX_RXD_OFFLOAD,
+#ifdef CC_AVX512_SUPPORT
 	IAVF_RX_AVX512,
 	IAVF_RX_AVX512_SCATTERED,
 	IAVF_RX_AVX512_OFFLOAD,
@@ -348,6 +352,8 @@ enum iavf_rx_func_type {
 	IAVF_RX_AVX512_SCATTERED_FLEX_RXD,
 	IAVF_RX_AVX512_FLEX_RXD_OFFLOAD,
 	IAVF_RX_AVX512_SCATTERED_FLEX_RXD_OFFLOAD,
+#endif /* CC_AVX512_SUPPORT */
+#endif /* RTE_ARCH_X86 */
 };
 
 enum iavf_tx_func_type {
-- 
2.43.0

[PATCH 7/8] net/ice: ensure all Rx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Rx paths are defined. The Rx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the ice_rx_func_type enum and only defining a value
for the Rx path if it is implemented in the ice_rx_path_infos array.

Fixes: 872b57178709 ("net/ice: use common Rx path selection infrastructure")
Cc: stable@dpdk.org

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/ice/ice_ethdev.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/ice/ice_ethdev.h b/drivers/net/intel/ice/ice_ethdev.h
index d1d31760d5..b682df0717 100644
--- a/drivers/net/intel/ice/ice_ethdev.h
+++ b/drivers/net/intel/ice/ice_ethdev.h
@@ -196,16 +196,20 @@ enum ice_rx_func_type {
 	ICE_RX_DEFAULT,
 	ICE_RX_SCATTERED,
 	ICE_RX_BULK_ALLOC,
+#ifdef RTE_ARCH_X86
 	ICE_RX_SSE,
 	ICE_RX_SSE_SCATTERED,
 	ICE_RX_AVX2,
 	ICE_RX_AVX2_SCATTERED,
 	ICE_RX_AVX2_OFFLOAD,
 	ICE_RX_AVX2_SCATTERED_OFFLOAD,
+#ifdef CC_AVX512_SUPPORT
 	ICE_RX_AVX512,
 	ICE_RX_AVX512_SCATTERED,
 	ICE_RX_AVX512_OFFLOAD,
 	ICE_RX_AVX512_SCATTERED_OFFLOAD,
+#endif /* CC_AVX512_SUPPORT */
+#endif /* RTE_ARCH_X86 */
 };
 
 enum ice_tx_func_type {
-- 
2.43.0

[PATCH 8/8] net/idpf: ensure all Rx paths are selectable

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Rx paths are defined. The Rx path selection function
iterates sequentially from zero to num_paths where num_paths is the size
of the array as determined by the RTE_DIM macro. However, depending on
the platform, some of these entries may be empty, and valid entries at
the end of the array may never be considered in the selection function.
Fix this by editing the idpf_rx_func_type enum and only defining a value
for the Rx path if it is implemented in the idpf_rx_path_infos array.

Fixes: 12b1c2901761 ("net/idpf: use common Rx path selection infrastructure")
Cc: stable@dpdk.org

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/idpf/idpf_common_device.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/idpf/idpf_common_device.h b/drivers/net/intel/idpf/idpf_common_device.h
index 9d3f35176d..487ca9d93c 100644
--- a/drivers/net/intel/idpf/idpf_common_device.h
+++ b/drivers/net/intel/idpf/idpf_common_device.h
@@ -69,9 +69,13 @@ enum idpf_rx_func_type {
 	IDPF_RX_DEFAULT,
 	IDPF_RX_SINGLEQ,
 	IDPF_RX_SINGLEQ_SCATTERED,
+#ifdef RTE_ARCH_X86
 	IDPF_RX_SINGLEQ_AVX2,
+#ifdef CC_AVX512_SUPPORT
 	IDPF_RX_AVX512,
 	IDPF_RX_SINGLEQ_AVX512,
+#endif
+#endif
 	IDPF_RX_MAX
 };
 
-- 
2.43.0

Re: [PATCH 0/8] Fixes for Intel common rx/tx path selection

[Bruce Richardson]

On Mon, Dec 15, 2025 at 02:05:45PM +0000, Ciara Loftus wrote:
> An issue exists with the way Rx and Tx paths are defined and then used
> by the common selection infrastructure, which in some cases means not
> all paths are available for selection. The issue affects four drivers on
> both Rx and Tx paths resulting in eight fix patches.
> 
> Depending on the underlying architecture and CPU flags available, a
> different set of paths are defined for each driver. The path selection
> function iterates sequentially from zero to num_paths where num_paths is
> the size of the array as determined by the RTE_DIM macro. However,
> depending on the platform, some of these entries may be empty, and valid
> entries at the end of the array may never be considered in the selection
> function. Fix this by editing each driver's rx/tx "func_type" enum and
> only defining a value for the path if it is implemented in the driver's
> rx/tx "path_infos" array.
>
I wonder if there is an alternative/better approach that can work here. For
each array, RTE_DIM will correctly give its size, and the indexes are set
according to the enum values which are common across each platform.
Therefore, the remaining entries in each array are going to be all zeroed,
since they are not explicitly initialized, e.g. the AXV entries on ARM
platforms. Would it not then work to just check during selection for a
non-NULL pkt_burst pointer in each entry we are comparing and skip those
which are NULL?

/Bruce

RE: [PATCH 0/8] Fixes for Intel common rx/tx path selection

[Loftus, Ciara]

> Subject: Re: [PATCH 0/8] Fixes for Intel common rx/tx path selection
> 
> On Mon, Dec 15, 2025 at 02:05:45PM +0000, Ciara Loftus wrote:
> > An issue exists with the way Rx and Tx paths are defined and then used
> > by the common selection infrastructure, which in some cases means not
> > all paths are available for selection. The issue affects four drivers on
> > both Rx and Tx paths resulting in eight fix patches.
> >
> > Depending on the underlying architecture and CPU flags available, a
> > different set of paths are defined for each driver. The path selection
> > function iterates sequentially from zero to num_paths where num_paths is
> > the size of the array as determined by the RTE_DIM macro. However,
> > depending on the platform, some of these entries may be empty, and valid
> > entries at the end of the array may never be considered in the selection
> > function. Fix this by editing each driver's rx/tx "func_type" enum and
> > only defining a value for the path if it is implemented in the driver's
> > rx/tx "path_infos" array.
> >
> I wonder if there is an alternative/better approach that can work here. For
> each array, RTE_DIM will correctly give its size, and the indexes are set
> according to the enum values which are common across each platform.
> Therefore, the remaining entries in each array are going to be all zeroed,
> since they are not explicitly initialized, e.g. the AXV entries on ARM
> platforms. Would it not then work to just check during selection for a
> non-NULL pkt_burst pointer in each entry we are comparing and skip those
> which are NULL?

That would indeed be much simpler - I'll submit a v2 shortly. Thanks!

> 
> /Bruce

[PATCH v2 0/3] Fixes for Intel common rx/tx path selection

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Rx/Tx paths may be defined by a driver using the common
path selection infrastructure. However the path selection function
iterates through the entire array of potential paths, regardless of
whether they are available for selection by that platform. This could
result in a null burst function being selected. Fix this by discarding
paths with a null burst function from selection.

The fix for the Tx paths can be squashed into the next-net-intel tree
as the commit that it targets has not yet made it into the main branch.

I added a third commit which addresses some minor inconsistencies in the
Rx path selection code and brings it in line with the Tx path selection
code. Functionally it remains the same.

Ciara Loftus (3):
  net/intel: prevent selection of a null Tx burst function
  net/intel: prevent selection of a null Rx burst function
  net/intel: bring common Rx path selection in line with Tx

 drivers/net/intel/common/rx.h             |  42 ++++-----
 drivers/net/intel/common/tx.h             |   4 +
 drivers/net/intel/cpfl/cpfl_rxtx.c        |   8 +-
 drivers/net/intel/i40e/i40e_rxtx.c        |  40 ++++----
 drivers/net/intel/iavf/iavf_rxtx.c        | 106 +++++++++++-----------
 drivers/net/intel/ice/ice_rxtx.c          |  40 ++++----
 drivers/net/intel/idpf/idpf_common_rxtx.c |  10 +-
 drivers/net/intel/idpf/idpf_rxtx.c        |   8 +-
 8 files changed, 131 insertions(+), 127 deletions(-)

-- 
2.43.0

[PATCH v2 1/3] net/intel: prevent selection of a null Tx burst function

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Tx paths may be defined by a driver using the common
path selection infrastructure. However the Tx path selection function
iterates through the entire array of potential Tx paths, regardless of
whether they are available for selection by that platform. This could
result in a null Tx burst function being selected. Fix this by
discarding paths with a null Tx burst function from selection.

Fixes: 336374d8454c ("net/intel: introduce infrastructure for Tx path selection")

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/common/tx.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/common/tx.h b/drivers/net/intel/common/tx.h
index 24fcfbe225..b259d98904 100644
--- a/drivers/net/intel/common/tx.h
+++ b/drivers/net/intel/common/tx.h
@@ -307,6 +307,10 @@ ci_tx_path_select(const struct ci_tx_path_features *req_features,
 	for (unsigned int i = 0; i < num_paths; i++) {
 		const struct ci_tx_path_features *path_features = &infos[i].features;
 
+		/* Do not select a path with a NULL pkt_burst function. */
+		if (infos[i].pkt_burst == NULL)
+			continue;
+
 		/* Do not select a disabled tx path. */
 		if (path_features->disabled)
 			continue;
-- 
2.43.0

[PATCH v2 2/3] net/intel: prevent selection of a null Rx burst function

[Ciara Loftus]

Depending on the underlying architecture and CPU flags available, a
different set of Rx paths may be defined by a driver using the common
path selection infrastructure. However the Rx path selection function
iterates through the entire array of potential Rx paths, regardless of
whether they are available for selection by that platform. This could
result in a null Rx burst function being selected. Fix this by
discarding paths with a null Rx burst function from selection.

Fixes: 9d99641d80a0 ("net/intel: introduce infrastructure for Rx path selection")
Cc: stable@dpdk.org

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/common/rx.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/intel/common/rx.h b/drivers/net/intel/common/rx.h
index ea7fb98b47..83259f2737 100644
--- a/drivers/net/intel/common/rx.h
+++ b/drivers/net/intel/common/rx.h
@@ -266,6 +266,10 @@ ci_rx_path_select(struct ci_rx_path_features req_features,
 	for (i = 0; i < num_paths; i++) {
 		const struct ci_rx_path_features *path_features = &infos[i].features;
 
+		/* Do not select a path with a NULL pkt_burst function. */
+		if (infos[i].pkt_burst == NULL)
+			continue;
+
 		/* Do not select a disabled rx path. */
 		if (path_features->extra.disabled)
 			continue;
-- 
2.43.0

[PATCH v2 3/3] net/intel: bring common Rx path selection in line with Tx

[Ciara Loftus]

The common Tx path selection infrastructure which was based off the Rx
infrastructure has recently been added. In the review process some
improvements were suggested for the Tx infrastructure which also apply
to the existing Rx infrastructure. This commit implements these
improvements for the Rx side.

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/common/rx.h             |  38 ++++----
 drivers/net/intel/cpfl/cpfl_rxtx.c        |   8 +-
 drivers/net/intel/i40e/i40e_rxtx.c        |  40 ++++----
 drivers/net/intel/iavf/iavf_rxtx.c        | 106 +++++++++++-----------
 drivers/net/intel/ice/ice_rxtx.c          |  40 ++++----
 drivers/net/intel/idpf/idpf_common_rxtx.c |  10 +-
 drivers/net/intel/idpf/idpf_rxtx.c        |   8 +-
 7 files changed, 123 insertions(+), 127 deletions(-)

diff --git a/drivers/net/intel/common/rx.h b/drivers/net/intel/common/rx.h
index 83259f2737..54dc3d7464 100644
--- a/drivers/net/intel/common/rx.h
+++ b/drivers/net/intel/common/rx.h
@@ -126,7 +126,9 @@ struct ci_rx_queue {
 	};
 };
 
-struct ci_rx_path_features_extra {
+struct ci_rx_path_features {
+	uint32_t rx_offloads;
+	enum rte_vect_max_simd simd_width;
 	bool scattered;
 	bool flex_desc;
 	bool bulk_alloc;
@@ -134,12 +136,6 @@ struct ci_rx_path_features_extra {
 	bool single_queue;
 };
 
-struct ci_rx_path_features {
-	uint32_t rx_offloads;
-	enum rte_vect_max_simd simd_width;
-	struct ci_rx_path_features_extra extra;
-};
-
 struct ci_rx_path_info {
 	eth_rx_burst_t pkt_burst;
 	const char *info;
@@ -255,15 +251,15 @@ ci_rxq_vec_capable(uint16_t nb_desc, uint16_t rx_free_thresh)
  *   or default_path if no suitable path is found
  */
 static inline int
-ci_rx_path_select(struct ci_rx_path_features req_features,
+ci_rx_path_select(const struct ci_rx_path_features *req_features,
 			const struct ci_rx_path_info *infos,
-			int num_paths,
+			size_t num_paths,
 			int default_path)
 {
-	int i, idx = default_path;
+	int idx = default_path;
 	const struct ci_rx_path_features *chosen_path_features = NULL;
 
-	for (i = 0; i < num_paths; i++) {
+	for (unsigned int i = 0; i < num_paths; i++) {
 		const struct ci_rx_path_features *path_features = &infos[i].features;
 
 		/* Do not select a path with a NULL pkt_burst function. */
@@ -271,32 +267,32 @@ ci_rx_path_select(struct ci_rx_path_features req_features,
 			continue;
 
 		/* Do not select a disabled rx path. */
-		if (path_features->extra.disabled)
+		if (path_features->disabled)
 			continue;
 
 		/* If requested, ensure the path uses the flexible descriptor. */
-		if (path_features->extra.flex_desc != req_features.extra.flex_desc)
+		if (path_features->flex_desc != req_features->flex_desc)
 			continue;
 
 		/* If requested, ensure the path supports single queue RX. */
-		if (path_features->extra.single_queue != req_features.extra.single_queue)
+		if (path_features->single_queue != req_features->single_queue)
 			continue;
 
 		/* If requested, ensure the path supports scattered RX. */
-		if (path_features->extra.scattered != req_features.extra.scattered)
+		if (path_features->scattered != req_features->scattered)
 			continue;
 
 		/* Do not use a bulk alloc path if not requested. */
-		if (path_features->extra.bulk_alloc && !req_features.extra.bulk_alloc)
+		if (path_features->bulk_alloc && !req_features->bulk_alloc)
 			continue;
 
 		/* Ensure the path supports the requested RX offloads. */
-		if ((path_features->rx_offloads & req_features.rx_offloads) !=
-				req_features.rx_offloads)
+		if ((path_features->rx_offloads & req_features->rx_offloads) !=
+				req_features->rx_offloads)
 			continue;
 
 		/* Ensure the path's SIMD width is compatible with the requested width. */
-		if (path_features->simd_width > req_features.simd_width)
+		if (path_features->simd_width > req_features->simd_width)
 			continue;
 
 		/* Do not select the path if it is less suitable than the chosen path. */
@@ -314,8 +310,8 @@ ci_rx_path_select(struct ci_rx_path_features req_features,
 			/* Do not select paths without bulk alloc support if requested and the
 			 * chosen path already meets this requirement.
 			 */
-			if (!path_features->extra.bulk_alloc && req_features.extra.bulk_alloc &&
-					chosen_path_features->extra.bulk_alloc)
+			if (!path_features->bulk_alloc && req_features->bulk_alloc &&
+					chosen_path_features->bulk_alloc)
 				continue;
 		}
 
diff --git a/drivers/net/intel/cpfl/cpfl_rxtx.c b/drivers/net/intel/cpfl/cpfl_rxtx.c
index b6bf4094f1..2e4cf3b875 100644
--- a/drivers/net/intel/cpfl/cpfl_rxtx.c
+++ b/drivers/net/intel/cpfl/cpfl_rxtx.c
@@ -1423,10 +1423,10 @@ cpfl_set_rx_function(struct rte_eth_dev *dev)
 		req_features.simd_width = cpfl_get_max_simd_bitwidth();
 #endif /* RTE_ARCH_X86 */
 
-	req_features.extra.single_queue = (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE);
-	req_features.extra.scattered = dev->data->scattered_rx;
+	req_features.single_queue = (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE);
+	req_features.scattered = dev->data->scattered_rx;
 
-	ad->rx_func_type = ci_rx_path_select(req_features,
+	ad->rx_func_type = ci_rx_path_select(&req_features,
 						&idpf_rx_path_infos[0],
 						IDPF_RX_MAX,
 						IDPF_RX_DEFAULT);
@@ -1434,7 +1434,7 @@ cpfl_set_rx_function(struct rte_eth_dev *dev)
 #ifdef RTE_ARCH_X86
 	if (idpf_rx_path_infos[ad->rx_func_type].features.simd_width >= RTE_VECT_SIMD_256) {
 		/* Vector function selected. Prepare the rxq accordingly. */
-		if (idpf_rx_path_infos[ad->rx_func_type].features.extra.single_queue) {
+		if (idpf_rx_path_infos[ad->rx_func_type].features.single_queue) {
 			for (i = 0; i < dev->data->nb_rx_queues; i++) {
 				cpfl_rxq = dev->data->rx_queues[i];
 				(void)idpf_qc_singleq_rx_vec_setup(&cpfl_rxq->base);
diff --git a/drivers/net/intel/i40e/i40e_rxtx.c b/drivers/net/intel/i40e/i40e_rxtx.c
index a7d80e2bc0..2db58c6b24 100644
--- a/drivers/net/intel/i40e/i40e_rxtx.c
+++ b/drivers/net/intel/i40e/i40e_rxtx.c
@@ -3373,7 +3373,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.info = "Scalar Scattered",
 		.features = {
 			.rx_offloads = I40E_RX_SCALAR_OFFLOADS,
-			.extra.scattered = true
+			.scattered = true
 		}
 	},
 	[I40E_RX_BULK_ALLOC] = {
@@ -3381,7 +3381,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.info = "Scalar Bulk Alloc",
 		.features = {
 			.rx_offloads = I40E_RX_SCALAR_OFFLOADS,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 #ifdef RTE_ARCH_X86
@@ -3391,7 +3391,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[I40E_RX_SSE_SCATTERED] = {
@@ -3400,8 +3400,8 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[I40E_RX_AVX2] = {
@@ -3410,7 +3410,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[I40E_RX_AVX2_SCATTERED] = {
@@ -3419,8 +3419,8 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 #ifdef CC_AVX512_SUPPORT
@@ -3430,7 +3430,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[I40E_RX_AVX512_SCATTERED] = {
@@ -3439,8 +3439,8 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 #endif
@@ -3451,7 +3451,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[I40E_RX_NEON_SCATTERED] = {
@@ -3460,8 +3460,8 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 #elif defined(RTE_ARCH_PPC_64)
@@ -3471,7 +3471,7 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[I40E_RX_ALTIVEC_SCATTERED] = {
@@ -3480,8 +3480,8 @@ static const struct ci_rx_path_info i40e_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = I40E_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 #endif
@@ -3517,11 +3517,11 @@ i40e_set_rx_function(struct rte_eth_dev *dev)
 
 	req_features.simd_width = rx_simd_width;
 	if (dev->data->scattered_rx)
-		req_features.extra.scattered = true;
+		req_features.scattered = true;
 	if (ad->rx_bulk_alloc_allowed)
-		req_features.extra.bulk_alloc = true;
+		req_features.bulk_alloc = true;
 
-	ad->rx_func_type = ci_rx_path_select(req_features,
+	ad->rx_func_type = ci_rx_path_select(&req_features,
 						&i40e_rx_path_infos[0],
 						RTE_DIM(i40e_rx_path_infos),
 						I40E_RX_DEFAULT);
diff --git a/drivers/net/intel/iavf/iavf_rxtx.c b/drivers/net/intel/iavf/iavf_rxtx.c
index 9ba8ff0979..ee53e6e802 100644
--- a/drivers/net/intel/iavf/iavf_rxtx.c
+++ b/drivers/net/intel/iavf/iavf_rxtx.c
@@ -3693,7 +3693,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.pkt_burst = iavf_recv_pkts_no_poll,
 		.info = "Disabled",
 		.features = {
-			.extra.disabled = true
+			.disabled = true
 		}
 	},
 	[IAVF_RX_DEFAULT] = {
@@ -3708,7 +3708,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.info = "Scalar Scattered",
 		.features = {
 			.rx_offloads = IAVF_RX_SCALAR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
-			.extra.scattered = true
+			.scattered = true
 		}
 	},
 	[IAVF_RX_FLEX_RXD] = {
@@ -3716,7 +3716,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.info = "Scalar Flex",
 		.features = {
 			.rx_offloads = IAVF_RX_SCALAR_FLEX_OFFLOADS,
-			.extra.flex_desc = true
+			.flex_desc = true
 		}
 	},
 	[IAVF_RX_SCATTERED_FLEX_RXD] = {
@@ -3724,8 +3724,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.info = "Scalar Scattered Flex",
 		.features = {
 			.rx_offloads = IAVF_RX_SCALAR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
-			.extra.scattered = true,
-			.extra.flex_desc = true
+			.scattered = true,
+			.flex_desc = true
 		}
 	},
 	[IAVF_RX_BULK_ALLOC] = {
@@ -3733,7 +3733,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.info = "Scalar Bulk Alloc",
 		.features = {
 			.rx_offloads = IAVF_RX_SCALAR_OFFLOADS,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_BULK_ALLOC_FLEX_RXD] = {
@@ -3741,8 +3741,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.info = "Scalar Bulk Alloc Flex",
 		.features = {
 			.rx_offloads = IAVF_RX_SCALAR_FLEX_OFFLOADS,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 #ifdef RTE_ARCH_X86
@@ -3752,7 +3752,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_SSE_SCATTERED] = {
@@ -3761,8 +3761,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_SSE_FLEX_RXD] = {
@@ -3771,8 +3771,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_SSE_SCATTERED_FLEX_RXD] = {
@@ -3782,9 +3782,9 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS |
 				       RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.scattered = true,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2] = {
@@ -3793,7 +3793,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_SCATTERED] = {
@@ -3802,8 +3802,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_OFFLOAD] = {
@@ -3812,7 +3812,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_SCATTERED_OFFLOAD] = {
@@ -3821,8 +3821,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_FLEX_RXD] = {
@@ -3831,8 +3831,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_SCATTERED_FLEX_RXD] = {
@@ -3841,9 +3841,9 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_FLEX_RXD_OFFLOAD] = {
@@ -3852,8 +3852,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX2_SCATTERED_FLEX_RXD_OFFLOAD] = {
@@ -3863,9 +3863,9 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS |
 				       RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 #ifdef CC_AVX512_SUPPORT
@@ -3875,7 +3875,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_SCATTERED] = {
@@ -3884,8 +3884,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_OFFLOAD] = {
@@ -3894,7 +3894,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_SCATTERED_OFFLOAD] = {
@@ -3903,8 +3903,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_FLEX_RXD] = {
@@ -3913,8 +3913,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_SCATTERED_FLEX_RXD] = {
@@ -3923,9 +3923,9 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_FLEX_RXD_OFFLOAD] = {
@@ -3934,8 +3934,8 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 	[IAVF_RX_AVX512_SCATTERED_FLEX_RXD_OFFLOAD] = {
@@ -3945,9 +3945,9 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 			.rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS |
 				       RTE_ETH_RX_OFFLOAD_SCATTER,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.flex_desc = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.flex_desc = true,
+			.bulk_alloc = true
 		}
 	},
 #endif
@@ -3958,7 +3958,7 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IAVF_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 #endif
@@ -4233,11 +4233,11 @@ iavf_set_rx_function(struct rte_eth_dev *dev)
 	}
 
 	if (use_flex)
-		req_features.extra.flex_desc = true;
+		req_features.flex_desc = true;
 	if (dev->data->scattered_rx)
-		req_features.extra.scattered = true;
+		req_features.scattered = true;
 	if (adapter->rx_bulk_alloc_allowed) {
-		req_features.extra.bulk_alloc = true;
+		req_features.bulk_alloc = true;
 		default_path = IAVF_RX_BULK_ALLOC;
 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM)
 		if (iavf_rx_vec_dev_check(dev) != -1)
@@ -4245,7 +4245,7 @@ iavf_set_rx_function(struct rte_eth_dev *dev)
 #endif
 	}
 
-	adapter->rx_func_type = ci_rx_path_select(req_features,
+	adapter->rx_func_type = ci_rx_path_select(&req_features,
 						&iavf_rx_path_infos[0],
 						RTE_DIM(iavf_rx_path_infos),
 						default_path);
diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/ice_rxtx.c
index 3fdb9fbf6e..f5d484c1e6 100644
--- a/drivers/net/intel/ice/ice_rxtx.c
+++ b/drivers/net/intel/ice/ice_rxtx.c
@@ -3698,7 +3698,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.info = "Scalar Scattered",
 		.features = {
 			.rx_offloads = ICE_RX_SCALAR_OFFLOADS,
-			.extra.scattered = true
+			.scattered = true
 		}
 	},
 	[ICE_RX_BULK_ALLOC] = {
@@ -3706,7 +3706,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.info = "Scalar Bulk Alloc",
 		.features = {
 			.rx_offloads = ICE_RX_SCALAR_OFFLOADS,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 #ifdef RTE_ARCH_X86
@@ -3716,7 +3716,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_SSE_SCATTERED] = {
@@ -3725,8 +3725,8 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_128,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX2] = {
@@ -3735,7 +3735,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX2_SCATTERED] = {
@@ -3744,8 +3744,8 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX2_OFFLOAD] = {
@@ -3754,7 +3754,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX2_SCATTERED_OFFLOAD] = {
@@ -3763,8 +3763,8 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 #ifdef CC_AVX512_SUPPORT
@@ -3774,7 +3774,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX512_SCATTERED] = {
@@ -3783,8 +3783,8 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX512_OFFLOAD] = {
@@ -3793,7 +3793,7 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.bulk_alloc = true
+			.bulk_alloc = true
 		}
 	},
 	[ICE_RX_AVX512_SCATTERED_OFFLOAD] = {
@@ -3802,8 +3802,8 @@ static const struct ci_rx_path_info ice_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.scattered = true,
-			.extra.bulk_alloc = true
+			.scattered = true,
+			.bulk_alloc = true
 		}
 	},
 #endif
@@ -3839,11 +3839,11 @@ ice_set_rx_function(struct rte_eth_dev *dev)
 
 	req_features.simd_width = rx_simd_width;
 	if (dev->data->scattered_rx)
-		req_features.extra.scattered = true;
+		req_features.scattered = true;
 	if (ad->rx_bulk_alloc_allowed)
-		req_features.extra.bulk_alloc = true;
+		req_features.bulk_alloc = true;
 
-	ad->rx_func_type = ci_rx_path_select(req_features,
+	ad->rx_func_type = ci_rx_path_select(&req_features,
 						&ice_rx_path_infos[0],
 						RTE_DIM(ice_rx_path_infos),
 						ICE_RX_DEFAULT);
diff --git a/drivers/net/intel/idpf/idpf_common_rxtx.c b/drivers/net/intel/idpf/idpf_common_rxtx.c
index cfeab8a1e4..797ee515dd 100644
--- a/drivers/net/intel/idpf/idpf_common_rxtx.c
+++ b/drivers/net/intel/idpf/idpf_common_rxtx.c
@@ -1667,15 +1667,15 @@ const struct ci_rx_path_info idpf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IDPF_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_DISABLED,
-			.extra.single_queue = true}},
+			.single_queue = true}},
 	[IDPF_RX_SINGLEQ_SCATTERED] = {
 		.pkt_burst = idpf_dp_singleq_recv_scatter_pkts,
 		.info = "Single Scalar Scattered",
 		.features = {
 			.rx_offloads = IDPF_RX_SCALAR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_DISABLED,
-			.extra.scattered = true,
-			.extra.single_queue = true}},
+			.scattered = true,
+			.single_queue = true}},
 #ifdef RTE_ARCH_X86
 	[IDPF_RX_SINGLEQ_AVX2] = {
 		.pkt_burst = idpf_dp_singleq_recv_pkts_avx2,
@@ -1683,7 +1683,7 @@ const struct ci_rx_path_info idpf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IDPF_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_256,
-			.extra.single_queue = true}},
+			.single_queue = true}},
 #ifdef CC_AVX512_SUPPORT
 	[IDPF_RX_AVX512] = {
 		.pkt_burst = idpf_dp_splitq_recv_pkts_avx512,
@@ -1697,7 +1697,7 @@ const struct ci_rx_path_info idpf_rx_path_infos[] = {
 		.features = {
 			.rx_offloads = IDPF_RX_VECTOR_OFFLOADS,
 			.simd_width = RTE_VECT_SIMD_512,
-			.extra.single_queue = true}},
+			.single_queue = true}},
 #endif /* CC_AVX512_SUPPORT */
 #endif /* RTE_ARCH_X86 */
 };
diff --git a/drivers/net/intel/idpf/idpf_rxtx.c b/drivers/net/intel/idpf/idpf_rxtx.c
index 3e2bccd279..47f8347b41 100644
--- a/drivers/net/intel/idpf/idpf_rxtx.c
+++ b/drivers/net/intel/idpf/idpf_rxtx.c
@@ -776,10 +776,10 @@ idpf_set_rx_function(struct rte_eth_dev *dev)
 		req_features.simd_width = idpf_get_max_simd_bitwidth();
 #endif /* RTE_ARCH_X86 */
 
-	req_features.extra.single_queue = (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE);
-	req_features.extra.scattered = dev->data->scattered_rx;
+	req_features.single_queue = (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE);
+	req_features.scattered = dev->data->scattered_rx;
 
-	ad->rx_func_type = ci_rx_path_select(req_features,
+	ad->rx_func_type = ci_rx_path_select(&req_features,
 						&idpf_rx_path_infos[0],
 						IDPF_RX_MAX,
 						IDPF_RX_DEFAULT);
@@ -787,7 +787,7 @@ idpf_set_rx_function(struct rte_eth_dev *dev)
 #ifdef RTE_ARCH_X86
 	if (idpf_rx_path_infos[ad->rx_func_type].features.simd_width >= RTE_VECT_SIMD_256) {
 		/* Vector function selected. Prepare the rxq accordingly. */
-		if (idpf_rx_path_infos[ad->rx_func_type].features.extra.single_queue) {
+		if (idpf_rx_path_infos[ad->rx_func_type].features.single_queue) {
 			for (i = 0; i < dev->data->nb_rx_queues; i++) {
 				rxq = dev->data->rx_queues[i];
 				(void)idpf_qc_singleq_rx_vec_setup(rxq);
-- 
2.43.0

Re: [PATCH v2 1/3] net/intel: prevent selection of a null Tx burst function

[Bruce Richardson]

On Tue, Dec 16, 2025 at 10:35:02AM +0000, Ciara Loftus wrote:
> Depending on the underlying architecture and CPU flags available, a
> different set of Tx paths may be defined by a driver using the common
> path selection infrastructure. However the Tx path selection function
> iterates through the entire array of potential Tx paths, regardless of
> whether they are available for selection by that platform. This could
> result in a null Tx burst function being selected. Fix this by
> discarding paths with a null Tx burst function from selection.
> 
> Fixes: 336374d8454c ("net/intel: introduce infrastructure for Tx path selection")
> 
> Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
> ---
Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Re: [PATCH v2 2/3] net/intel: prevent selection of a null Rx burst function

[Bruce Richardson]

On Tue, Dec 16, 2025 at 10:35:03AM +0000, Ciara Loftus wrote:
> Depending on the underlying architecture and CPU flags available, a
> different set of Rx paths may be defined by a driver using the common
> path selection infrastructure. However the Rx path selection function
> iterates through the entire array of potential Rx paths, regardless of
> whether they are available for selection by that platform. This could
> result in a null Rx burst function being selected. Fix this by
> discarding paths with a null Rx burst function from selection.
> 
> Fixes: 9d99641d80a0 ("net/intel: introduce infrastructure for Rx path selection")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Re: [PATCH v2 3/3] net/intel: bring common Rx path selection in line with Tx

[Bruce Richardson]

On Tue, Dec 16, 2025 at 10:35:04AM +0000, Ciara Loftus wrote:
> The common Tx path selection infrastructure which was based off the Rx
> infrastructure has recently been added. In the review process some
> improvements were suggested for the Tx infrastructure which also apply
> to the existing Rx infrastructure. This commit implements these
> improvements for the Rx side.
> 
> Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
> ---

Seems reasonable cleanup, and I like the consistency.

Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Re: [PATCH v2 0/3] Fixes for Intel common rx/tx path selection

[Bruce Richardson]

On Tue, Dec 16, 2025 at 10:35:01AM +0000, Ciara Loftus wrote:
> Depending on the underlying architecture and CPU flags available, a
> different set of Rx/Tx paths may be defined by a driver using the common
> path selection infrastructure. However the path selection function
> iterates through the entire array of potential paths, regardless of
> whether they are available for selection by that platform. This could
> result in a null burst function being selected. Fix this by discarding
> paths with a null burst function from selection.
> 
> The fix for the Tx paths can be squashed into the next-net-intel tree
> as the commit that it targets has not yet made it into the main branch.
> 
> I added a third commit which addresses some minor inconsistencies in the
> Rx path selection code and brings it in line with the Tx path selection
> code. Functionally it remains the same.
> 
> Ciara Loftus (3):
>   net/intel: prevent selection of a null Tx burst function
>   net/intel: prevent selection of a null Rx burst function
>   net/intel: bring common Rx path selection in line with Tx
> 
Patch 1 squashed into original commit in net-net-intel. Other two applied
as new commits in that tree.

Thanks,
/Bruce