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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5055.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 166984a8-2488-4e0e-dfb4-08dc78b9712a X-MS-Exchange-CrossTenant-originalarrivaltime: 20 May 2024 10:41:44.2614 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NFIz8EeKdrSv0R3iPA/YY1ktUtB6ywei4EAp8mG8avo1S4vXAQWyDO1HxPGCYLkaQ4BPf5obQm0Xq90MjIR5lw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7123 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org [AMD Official Use Only - AMD Internal Distribution Only] Acked-by: Selwin Sebastian -----Original Message----- From: Ande, Venkat Kumar Sent: Tuesday, May 7, 2024 6:13 PM To: dev@dpdk.org Cc: Sebastian, Selwin ; Ande, Venkat Kumar ; stable@dpdk.org Subject: [PATCH v2 07/25] net/axgbe: enable PLL control for fixed PHY modes= only PLL control setting(RRC) is needed only in fixed PHY configuration to fix t= he peer-peer issues. Without the PLL control setting, the link up takes lon= ger time in a fixed phy configuration. Without the fix the user will not get the link come UP. Driver implements SW RRC for Autoneg On configuration, hence PLL control se= tting (RRC) is not needed for AN On configuration, and can be skipped. Also, PLL re-initialization is not needed for PHY Power Off and RRC command= s. Otherwise, they lead to mailbox errors. Added the changes accordingly. Fixes: 09b0a36cc7ae ("net/axgbe: toggle PLL settings during rate change") Cc: stable@dpdk.org Signed-off-by: Venkat Kumar Ande --- drivers/net/axgbe/axgbe_phy_impl.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_p= hy_impl.c index f51830f800..9c2ae7bba0 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -1228,6 +1228,10 @@ static void axgbe_phy_rx_reset(struct axgbe_port *pd= ata) static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) { + /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Au= toneg) only */ + if (pdata->phy.autoneg !=3D AUTONEG_DISABLE) + return; + XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, XGBE_PMA_PLL_CTRL_MASK, enable ? XGBE_PMA_PLL_CTRL_SET @@ -1272,8 +1276,10 @@ static void axgbe_phy_perform_ratechange(struct axgb= e_port *pdata, axgbe_phy_rx_reset(pdata); reenable_pll: - /* Re-enable the PLL control */ - axgbe_phy_pll_ctrl(pdata, true); + /* Enable PLL re-initialization, not needed for PHY Power Off and R= RC cmds */ + if (cmd !=3D AXGBE_MB_CMD_POWER_OFF && + cmd !=3D AXGBE_MB_CMD_RRC) + axgbe_phy_pll_ctrl(pdata, true); PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");= } -- 2.34.1