From: Raslan Darawsheh <rasland@nvidia.com>
To: Alexander Kozyrev <akozyrev@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "stable@dpdk.org" <stable@dpdk.org>,
Slava Ovsiienko <viacheslavo@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix Tx meta width for modify field flow rule
Date: Sun, 31 Oct 2021 12:33:00 +0000 [thread overview]
Message-ID: <DM4PR12MB5312A5E2F022DC680F722A53CF899@DM4PR12MB5312.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20211026151357.1349968-1-akozyrev@nvidia.com>
Hi,
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Tuesday, October 26, 2021 6:14 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Subject: [PATCH] net/mlx5: fix Tx meta width for modify field flow rule
>
> Register C is used for the metadata within NIC Rx domain.
> And its width can vary from 0 to 32 bits depending on its kernel usage. But it
> is not the case within NIC Tx domain, register A is always 32 bits there. Fix
> metadata width detection for the modify_field flow API within NIC Tx
> domain.
>
> Fixes: 6d5735c1cb ("net/mlx5: fix meta register conversion for extensive
> mode")
> Cc: stable@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
prev parent reply other threads:[~2021-10-31 12:33 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 15:13 Alexander Kozyrev
2021-10-31 12:33 ` Raslan Darawsheh [this message]
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