From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41BB745BFE; Mon, 28 Oct 2024 16:47:04 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2DA6C40E0B; Mon, 28 Oct 2024 16:47:04 +0100 (CET) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2079.outbound.protection.outlook.com [40.107.92.79]) by mails.dpdk.org (Postfix) with ESMTP id 9DD47400D7; Mon, 28 Oct 2024 16:47:03 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=si+KDY01iRh0xLkAwJIoXSrFNDp9WL4LNVgXYTszo122THM8ZBBEFuhdlmAtBk8oub2ljNgUoWSEXAqOU4RJnTElXUN2Sllawea+vpNWyPvOcMC7zncX7r0evMuPLR82NytPwIju6kBUQbpn6Ss11NXWjMg3QEHcmpTzPv28/itx9y3+ZXYtILz25I+OyQPn6VpbFUCUC34qvybwD0ZM9gBA/dlxYu1CCl+jCBFPK0bAheu24qeSsFWCQWZXcT/qGSJZu/3ICeYivsRaWzu+WVvV5Llh3FzcM5jLjvv9j4gKUzTH22zkGdcQVO9Zh4udVrsnV4jKaROLsfvfeTzL9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WRqmowjpvyDR+mvS2sUv189/1ZduAsjberRa+XYH+n8=; b=UmeOTUTyQqBapmY0NE6seLmFB3fDi6axMDctlN6xFKW2rqRG5KgNfe0P1oznxYVBy/v+bQegCG4AK8yCVNpgsNMvcdD4CsYahzO5uP1aJpH12fIiQ1jwplxHXwDjw9dk6wDj6nDC4ACU3hmDs3FuDAu03k3B9fSoRNu+2dicelkQ4+tbkjo2W+eldSxGOpbR2OgSIgIOrooz2TUfZ0vwkk4WYHPTTbafwr8UKoV13jv0geyQq79f0QHsazLHXrQxIKONDEmZVoopLhsvNmNjOz7bUxuoYMF3EP6zguVBhB/DTKR9z+/x67dObOeqx3PxXoZbhNusJ0IOuI8YlhUy+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WRqmowjpvyDR+mvS2sUv189/1ZduAsjberRa+XYH+n8=; b=nAOEbJjbeYRKIe0oPX4V6q8KkoaXffEQKlOpEhz0d+gqqZAJrtrAMxuaFKhJB6FYyWABm/7pzfkDXHxEEe4QqJ/gvIjTv3wteCvN9+RWUMrCPozz/xzv9+1wjK01abO4tE6YoNGyw50PwA3IEv5dSu4+9Q0NN54kiUTxILayqvlIWD3FcasHmxP7TdJhKkMovdWQnNS9877ZqHvxVz3aL28kD+tbqqGfsdkKIVTnQhhyq2NX9wPulSmXXuAdMoFWTNN8kGu6zyHMZHycBK8MeFUBn+fndnSu0NNv0YCPDDJoGlL3tjevCfqyCKp+Jf6KVnhPrfbw371ZeqotJY/70w== Received: from DM4PR12MB7549.namprd12.prod.outlook.com (2603:10b6:8:10f::14) by DM6PR12MB4313.namprd12.prod.outlook.com (2603:10b6:5:21e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.24; Mon, 28 Oct 2024 15:47:00 +0000 Received: from DM4PR12MB7549.namprd12.prod.outlook.com ([fe80::36a0:7d17:4418:7c62]) by DM4PR12MB7549.namprd12.prod.outlook.com ([fe80::36a0:7d17:4418:7c62%4]) with mapi id 15.20.8093.024; Mon, 28 Oct 2024 15:47:00 +0000 From: Slava Ovsiienko To: Igor Gutorov , "dev@dpdk.org" CC: "stable@dpdk.org" Subject: RE: [PATCH v3 1/2] net/mlx5: fix reported Rx/Tx desc limits Thread-Topic: [PATCH v3 1/2] net/mlx5: fix reported Rx/Tx desc limits Thread-Index: AQHa6QqqQfcQSVE42UWENRWXk9c/WLKczwfw Date: Mon, 28 Oct 2024 15:47:00 +0000 Message-ID: References: <20240807204406.700332-1-igootorov@gmail.com> <20240807204406.700332-2-igootorov@gmail.com> In-Reply-To: <20240807204406.700332-2-igootorov@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DM4PR12MB7549:EE_|DM6PR12MB4313:EE_ x-ms-office365-filtering-correlation-id: 1af858a5-f250-4570-dd5b-08dcf767c2e3 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|376014|366016|1800799024|38070700018; x-microsoft-antispam-message-info: =?us-ascii?Q?EFVJEQWgUlbXXbEft4LZyAJvwSzc07sRo6rLo7oRVv/Nv/bfP5FDbw5ptYAJ?= =?us-ascii?Q?cAq0eclZw1hHf06Tgxka/Q7d/XrfBLeJsyIWPRxSD0EZfvkiSgS6NxhOgHR9?= =?us-ascii?Q?obapWDKN4ajXWAt48/hT/w5yQt/bjkB+0rsnhGgGmpxsfALCWBL2xA+sVxwm?= =?us-ascii?Q?VtaIOoohdYz65zmE/a7TBDJl89FyBYd/yXh/mx1qZNCRBUOumNymTMKuuhN2?= =?us-ascii?Q?t47VH2FDc4Nfz6dBmjQaMX8u5EEWr0ge6EGh7isH814DmpD6cASZjdKTzgQM?= =?us-ascii?Q?8gWkRevP2KKFbwkAxOBzPqF0aHX/kLDEZf6rNkT66tC85p4/ntKvG+Ptx2Pw?= =?us-ascii?Q?nb+xhl3k3njTufTcvzSxh2clFYlTL+rd5+rhuCi9fI7M+N6n0u+rOq3vX/cH?= =?us-ascii?Q?wXJYPgpfN3re5qrxzz3er3ALiDpZqS1p515f3SfHb9v4kEveHsMYlvL0bXiZ?= =?us-ascii?Q?6edycQcY3wJEwc5GBZsp/cxfjSaOczUdathDVCxg5oXBUi9waZGVgtWbhjOc?= =?us-ascii?Q?1An0lz/7OM5FaDS375TMUxggKiswsE00yayt4ebICIfXCUVIUZ7sBsYvOZXR?= =?us-ascii?Q?7ktLfWGCctc1kwdPkINH30Xzq9riVcCb1rIcbfNn+dWcxQAXZC3TkCM9RRgJ?= =?us-ascii?Q?lrrkmkrmErE205DBJQcHOjNuFPBnJ5pp4+gu3KQ7zCBm7sX7jMsYEf9JHlK4?= =?us-ascii?Q?WKtrxJHeLBqgSdw2jwiBRwJhyZONi4QRMD5xgBEpt7yCU/ItS5bBZR3u5a8Z?= =?us-ascii?Q?QSzf/R2TQyDNVdVqPWixsiH4aZSGVALXpnEaI1jqdz/Ly44+fv95JFezpbMb?= =?us-ascii?Q?dTA0xF4Qw1+UZSrLh33wJOZaDn+3mP/+zlFwF/q52feAr1VIapzFJeXmJY4F?= =?us-ascii?Q?W+bRKryPv4LO17Gg0aBomim1AYe9aKokDB4m4Q2lbyOnM1bLzVQlDTIyrsbc?= =?us-ascii?Q?O6e6hnioKCI89l3GwG2WbTthLGtAYKhzAWEAW2oH/2laIKHlgHv6i1toPTUo?= =?us-ascii?Q?2shitsN4zWARg2L4DP0Se6p5VUYZnSJNWe1dJhqewYwbAMJj0HcqABvACzWd?= =?us-ascii?Q?HWN4QSimM32PsSWnpRei6vcfTxadt1nmyoW91o/bEMslMp+bDbtPE+1bZZTy?= =?us-ascii?Q?YTNEDoDZrzyA/e0r08jzyvTkS6GPL8QCA+wueScKjCFOnvOVWaIqEUs+zkLk?= =?us-ascii?Q?2QtJjuD9afXTG340ZsB5idgfLUsIVihuTv/xWv8wRbygG5BSDPxlgIICIqCq?= =?us-ascii?Q?+CspDvdL0o/4j2qyxR4mI0oyhFvzsz7s5rIlzXM2pCCseSLiuuE2mTIeHskk?= =?us-ascii?Q?cZqmWBw8vPmYQMhplT7ZiLqDmBmrI3vF4qACJh0yr2DQJuIcQfApTdTXVqtc?= =?us-ascii?Q?Z3lqJiE=3D?= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM4PR12MB7549.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(366016)(1800799024)(38070700018); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?kKU1px9fPbs9f93J157VVHfDBMj7JBLKKP26NjJbfUYqlbfSnSJxCT7ADL03?= =?us-ascii?Q?ZNpOeML2wYOjOE+71wQMoakB2JAtKt7Cdh1+jbgjUhd6RJg8uJw0HBwprrbr?= =?us-ascii?Q?CBI4A2rAipSdu2PSFMJ/mJJlFGb4XD/dNVXLkyaLXlIq/YS7GkSW50wua5WV?= =?us-ascii?Q?IZ3GTcV5SpfbZyVipSX6M9Ycv/1W6zY2Qx6xTwMRyFAJz2/2A3/jWfy/1XmV?= =?us-ascii?Q?3lm31s7Un+mnDs5t7tX6xxiMrXr1SfmNjbtMxIDPORpMGLwQg9qCWdHvM0jh?= =?us-ascii?Q?i0UuJtOV44zxDRAYE8TrWlo+iWe4SW3xmZf6yAWYsc2++H6Gqb8gGvk1EqLu?= =?us-ascii?Q?PzSMQUnaHtzFz/YrNHykOvTRaSd4RZ8Iu2l3KkoqtcAjOf7Ii4LK0ldC1HWR?= =?us-ascii?Q?ZuQj5Y1F2j/DJhVtODn8qKYbGWewMc38A4Gza2cVnbGx0ffn3Idv3pHpsoi7?= =?us-ascii?Q?UpI7K8Usl99ogCtYSOwVaiuxAjZOcn8tT46JwheKuU0sUxfib3CorZkJ3z8t?= =?us-ascii?Q?/IibqCDcifuw7NkNbMmYWrY9kX49WduTNeFIkdD5tP9onbpVnHx60/VZZXNZ?= =?us-ascii?Q?yjAPYApJQXjvLytPoPgtOCn/anU2/ryOxWBNYpcJU4L630U3Gb8DSqLVUJSQ?= =?us-ascii?Q?0RNqGh7mIYK+/WAgNOvsqU2FlTZJ97B02b/Pdijr+8rKloLl6Mj0U3spgunr?= =?us-ascii?Q?OpR8fk0n9QdjQCYp9dj9MX9kn7pJu4R4Jr5Z/4FysPnQqnHZaf5+1NXPWzGr?= =?us-ascii?Q?3oB2k+rUB9K+HUOtH7y/HHhV5djSm0H2pk2r4ZENzVkIoBNXb102BbBQEUAy?= =?us-ascii?Q?d1s+V0x8Fqfv9Zo8jotMfbAPGWesfqMMU16NpFVsW5Y1lpaRqGFjf2rvUacw?= =?us-ascii?Q?bUp4BG0IBgTKNoTuMxRcP9T2D4AJQiN+/lUuEMOZldHh9xeWg8QJxQbhKZUR?= =?us-ascii?Q?d5RcdViI1kf5+44G4eteMz/4f0Y+QH2imQfg3SrElXSBY3gdw9jZyuCkvVDF?= =?us-ascii?Q?joVtjrYHKewYGlzO5sMqIkAr+U5KzOORj9e2oeq6jwV95w/pvJtXmZWG5fKv?= =?us-ascii?Q?HnDarBUJzjCDXgkPbP+v90gXF6UbQ+goXf7ReM8QEmKqI0vLamTaU7YtxbRw?= =?us-ascii?Q?ew54DE27VVELTqXSi0MmvA0qfK5TUWsLsBWDqbhjvbsnOeOJs1QW+0g4RwvI?= =?us-ascii?Q?06Rlfr3+tW5oUMo+pkkOL+MxXgJsueRL5pBo5ggb1Je5cDcUCfUdzloZZvr2?= =?us-ascii?Q?9pYcXeGDOxYtw61ez34ImnIjKVPxxJ23AnNnSKZTvmOTkBYxv5fMZh4hxCda?= =?us-ascii?Q?iQiJuWwH7ImCkrtMNrLPODg8nj+QyBRjcKgC6/qpzUbUa5DXbh0TW/nPwszd?= =?us-ascii?Q?me6jvP6xvYtR/iqBPta8EJiNXXmL0Xee8ygFAFCmB9O/a+89uBIX5ydJDNVD?= =?us-ascii?Q?aUz8WabM3zB/0cCh/czyO2coOlxakt8viY0T9F3csRX5q0l25Q4uc969U3h+?= =?us-ascii?Q?1lLNZnEFxMarOLMDeXSgH1niUVLviRBSvk59f6gHmrI2AmgC+ViGqVFPNEM5?= =?us-ascii?Q?Au/vcnTzU9OPDwAyi2GquhBlgqERUITwN3p9yk7m?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB7549.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1af858a5-f250-4570-dd5b-08dcf767c2e3 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2024 15:47:00.3117 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: HSDErwD1vROwgODF5Umac57Kk3xjg/SaGLZHeD4CpbM2kwKnOl27tuTNJJb5IWeujgeajH+hYDtBnkzssbUmpw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4313 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Thank you for the patch. Acked-by: Viacheslav Ovsiienko > -----Original Message----- > From: Igor Gutorov > Sent: Wednesday, August 7, 2024 11:44 PM > To: dev@dpdk.org > Cc: Igor Gutorov ; stable@dpdk.org > Subject: [PATCH v3 1/2] net/mlx5: fix reported Rx/Tx desc limits >=20 > Currently, `rte_eth_dev_info.rx_desc_lim.nb_max` as well as > `rte_eth_dev_info.tx_desc_lim.nb_max` shows 65535 as the limit, which > results in a few problems: >=20 > * It is not the actual Rx/Tx queue limit > * Allocating an Rx queue and passing `rx_desc_lim.nb_max` results in an > integer overflow and 0 ring size: >=20 > ``` > rte_eth_rx_queue_setup(0, 0, rx_desc_lim.nb_max, 0, NULL, mb_pool); ``` >=20 > Which overflows ring size and generates the following log: > ``` > mlx5_net: port 0 increased number of descriptors in Rx queue 0 to the nex= t > power of two (0) ``` The same holds for allocating a Tx queue. >=20 > Fixes: e60fbd5b24fc ("mlx5: add device configure/start/stop") > Cc: stable@dpdk.org >=20 > Signed-off-by: Igor Gutorov > --- > drivers/common/mlx5/mlx5_devx_cmds.c | 1 + > drivers/common/mlx5/mlx5_devx_cmds.h | 1 + > drivers/net/mlx5/mlx5_ethdev.c | 4 ++++ > drivers/net/mlx5/mlx5_rxq.c | 8 ++++++++ > drivers/net/mlx5/mlx5_txq.c | 8 ++++++++ > 5 files changed, 22 insertions(+) >=20 > diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c > b/drivers/common/mlx5/mlx5_devx_cmds.c > index 9710dcedd3..a75f011750 100644 > --- a/drivers/common/mlx5/mlx5_devx_cmds.c > +++ b/drivers/common/mlx5/mlx5_devx_cmds.c > @@ -1027,6 +1027,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, > attr->log_max_qp =3D MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); > attr->log_max_cq_sz =3D MLX5_GET(cmd_hca_cap, hcattr, > log_max_cq_sz); > attr->log_max_qp_sz =3D MLX5_GET(cmd_hca_cap, hcattr, > log_max_qp_sz); > + attr->log_max_wq_sz =3D MLX5_GET(cmd_hca_cap, hcattr, > log_max_wq_sz); > attr->log_max_mrw_sz =3D MLX5_GET(cmd_hca_cap, hcattr, > log_max_mrw_sz); > attr->log_max_pd =3D MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); > attr->log_max_srq =3D MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); > diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h > b/drivers/common/mlx5/mlx5_devx_cmds.h > index 6cf7999c46..2ad9e5414f 100644 > --- a/drivers/common/mlx5/mlx5_devx_cmds.h > +++ b/drivers/common/mlx5/mlx5_devx_cmds.h > @@ -267,6 +267,7 @@ struct mlx5_hca_attr { > struct mlx5_hca_flow_attr flow; > struct mlx5_hca_flex_attr flex; > struct mlx5_hca_crypto_mmo_attr crypto_mmo; > + uint8_t log_max_wq_sz; > int log_max_qp_sz; > int log_max_cq_sz; > int log_max_qp; > diff --git a/drivers/net/mlx5/mlx5_ethdev.c > b/drivers/net/mlx5/mlx5_ethdev.c index 6a678d6dcc..cac55f7a72 100644 > --- a/drivers/net/mlx5/mlx5_ethdev.c > +++ b/drivers/net/mlx5/mlx5_ethdev.c > @@ -359,6 +359,10 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, > struct rte_eth_dev_info *info) > info->flow_type_rss_offloads =3D ~MLX5_RSS_HF_MASK; > mlx5_set_default_params(dev, info); > mlx5_set_txlimit_params(dev, info); > + info->rx_desc_lim.nb_max =3D > + 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz; > + info->tx_desc_lim.nb_max =3D > + 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz; > if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && > priv->obj_ops.rxq_obj_new =3D=3D devx_obj_ops.rxq_obj_new) > info->dev_capa |=3D RTE_ETH_DEV_CAPA_RXQ_SHARE; diff -- > git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index > f13fc3b353..7e171039eb 100644 > --- a/drivers/net/mlx5/mlx5_rxq.c > +++ b/drivers/net/mlx5/mlx5_rxq.c > @@ -655,6 +655,14 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev > *dev, uint16_t idx, uint16_t *desc, > struct mlx5_rxq_priv *rxq; > bool empty; >=20 > + if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) { > + DRV_LOG(ERR, > + "port %u number of descriptors requested for Rx > queue" > + " %u is more than supported", > + dev->data->port_id, idx); > + rte_errno =3D EINVAL; > + return -EINVAL; > + } > if (!rte_is_power_of_2(*desc)) { > *desc =3D 1 << log2above(*desc); > DRV_LOG(WARNING, > diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c > index f05534e168..3e93517323 100644 > --- a/drivers/net/mlx5/mlx5_txq.c > +++ b/drivers/net/mlx5/mlx5_txq.c > @@ -333,6 +333,14 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev > *dev, uint16_t idx, uint16_t *desc) { > struct mlx5_priv *priv =3D dev->data->dev_private; >=20 > + if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) { > + DRV_LOG(ERR, > + "port %u number of descriptors requested for Tx > queue" > + " %u is more than supported", > + dev->data->port_id, idx); > + rte_errno =3D EINVAL; > + return -EINVAL; > + } > if (*desc <=3D MLX5_TX_COMP_THRESH) { > DRV_LOG(WARNING, > "port %u number of descriptors requested for Tx > queue" > -- > 2.45.2