From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9DD51A04AA; Tue, 8 Sep 2020 03:53:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8712D1C116; Tue, 8 Sep 2020 03:53:51 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 1F46B1C10F for ; Tue, 8 Sep 2020 03:53:48 +0200 (CEST) IronPort-SDR: H5EBVEG16SIp82lpWcyE70DJpj7V5AhmwMGaNUNtN8EJTq7RZ3KNdRVbMuaz0hbwONUioRzQpt FHMNq9l4ROVA== X-IronPort-AV: E=McAfee;i="6000,8403,9737"; a="219618527" X-IronPort-AV: E=Sophos;i="5.76,404,1592895600"; d="scan'208";a="219618527" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2020 18:53:47 -0700 IronPort-SDR: do3plyBI7hPZmOQScAnc35+Kj+NRI8pC2JXm/AHPyj0YgBKtEwGBar3pj+nj9IN4k6WYeHN5sJ fCy1vUnGHKuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,404,1592895600"; d="scan'208";a="504881528" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by fmsmga005.fm.intel.com with ESMTP; 07 Sep 2020 18:53:47 -0700 Received: from orsmsx601.amr.corp.intel.com (10.22.229.14) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 7 Sep 2020 18:53:47 -0700 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 7 Sep 2020 18:53:47 -0700 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.102) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Mon, 7 Sep 2020 18:53:43 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DzdmN3qnmT/r6PZ1ZQmod10zetu3Oxmt8GJAb1XbWNBodEnHsmmKV7vQYcL2l0+D2LVIblMLoEDkml5ynl/0YNFQ5OF7WhTMHEOUKSYMjppV+JCYlWQMgVYSzN53vUDKK46g3H5zDBVIdg08w/BcY3d8ASbtFLH9BU5hqKYak3oy2gM6uXGKr2fhxTMcH7DIv8nMC8fNeqlDJOgIAhpEMJE8x8ahY/wGsTeNOes+wQSGG9tRGZ1E/Sa/DRahLN1m3xIemTNsAAKm/s0yUrlO8myNPK1sjdMdPWJ2kAn6ZEdrm3m0svUXGERs5xmmys02uZYRWqnHYBu7G70LK0Kziw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V+bkkRqvpr9teIuBjcdcO0cNuKxkFh4EMfUsESP8H2k=; b=iERilmB0c0tHxX282QXxAQdj2P5lVgI+TXBTcIdTzC67EqaczWoKYv74apUrYiAWUS5flxdMFpROxgXf7yq+/Q1kyb6rlw6c4ni7yeNnPdhHepVEzTRjEBGxXNtBYAj8Jh6fQIncOhhbh/DlmEOlYcTRMzoduCi9PwcEbgr1sDg6lPgvKRF1lYotGyJtc09QIMtJ8VCMgenVYTrc5CO4JLPJY5Q1ej/mL/JEVBwtZ1xRrIYayProjMFldeL6vBXO5w+c//QiR8kbj/KEknvGnTWgchdO1Tyarp6shQStwtFU7BxcozTYVjlfh0G0IWitWKHnAjCpBDHyu3UH4FA1uw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V+bkkRqvpr9teIuBjcdcO0cNuKxkFh4EMfUsESP8H2k=; b=qViKkJCFUQvY8R0ZviJjUhoFmoUztsMZU7IRcmDuVl6SYoWMttjBastmy6FC6WXm23CPSeYIMpNhbspKSua3NTP4/moroFpIEibDKR0DCiwHWLI1LJHsjx77UiqKaVUMZ+oT+J45fBsF7zfGug//4Ig74k2v5xaDs2GAopx1944= Received: from DM5PR11MB1753.namprd11.prod.outlook.com (2603:10b6:3:10d::13) by DM6PR11MB3531.namprd11.prod.outlook.com (2603:10b6:5:61::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.15; Tue, 8 Sep 2020 01:53:41 +0000 Received: from DM5PR11MB1753.namprd11.prod.outlook.com ([fe80::ec81:9fa3:310c:982b]) by DM5PR11MB1753.namprd11.prod.outlook.com ([fe80::ec81:9fa3:310c:982b%10]) with mapi id 15.20.3348.019; Tue, 8 Sep 2020 01:53:41 +0000 From: "Li, Xiaoyun" To: "Wu, Jingjing" CC: "dev@dpdk.org" , "Maslekar, Omkar" Thread-Topic: [PATCH v3] raw/ntb: add Icelake support for Intel NTB Thread-Index: AQHWhL2fU7n2mFtPj0qWehTdnWXa76lc2f+AgAAIcnCAAHhcAIAAoRww Date: Tue, 8 Sep 2020 01:53:41 +0000 Message-ID: References: <20200831045958.5589-1-xiaoyun.li@intel.com> <20200907022112.17640-1-xiaoyun.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.55.46.36] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 84ab666b-6064-438c-6e5e-08d8539a0312 x-ms-traffictypediagnostic: DM6PR11MB3531: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 4V883q/D0rc5f7liAZtqn+Im+lb7+IdNKQ7BeOsbSuu1JMyZHIKGHUj5+e5+dzblxxhhc4/usM360JPqzuHrLSi6fhMPm3gv4DvZwCZbzxzNUmkJprvSQFFp9mAPHl+HGUIoxGRlvwQlSsrKBkpVq0REUzIOwaOXMX9ua0NF4CysUzKNvDaT/exmvED+PRD9VuVhWzUf1WaxxF/RpZc8l+QXcXsT36kZruUPu6Vp9whAXpZaGgfFpbX9kPaSKZ6d7LtU4slfah0FmopgEKR+IjEeLfxBN17fvA05IPRFmc4FKfHIUeWJoqiFkmk41Yiqqq4re7IiLVeuv0Yw/FeeLg== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM5PR11MB1753.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(346002)(376002)(136003)(366004)(396003)(39860400002)(33656002)(76116006)(83380400001)(478600001)(4326008)(71200400001)(66946007)(8936002)(8676002)(64756008)(66556008)(66476007)(186003)(6862004)(7696005)(52536014)(53546011)(6506007)(2906002)(5660300002)(55016002)(66446008)(26005)(9686003)(86362001)(107886003)(6636002)(316002)(54906003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: r2WCgt2OX+lCP+qqp87dKPcLNQDtfLzn8gGCLovmYnt86WfT8czqNUAMRxrd8wNpGNS8ivj7yw9B4LNumtv18p1+gb4teo/psup145o3ZeejWeQ08ZEPDY6d6BADD56gLpegfph+tg28nzBSakeNyVadkUIRVPpr66PcfeZ+u2czUB9PZNqc5nTgytg7hnS3NUDfUV1ivwEKpUYxO/9N4nwcBdI6AOAh22+vDUa/vKOg+iZmJLMeMNMeQOjR63CrY/9eM5YNAwB4Q7ElJbq5R5D2Dzser9/aeFs5UUBcDlVfcnfGrPc/RNWqzdLNIe7+Yq3L0hXmatlyRcLdJPtutZx90srFBJ8vu/xmbr2pCXC02qhVsc9ZOpicHgPvPmPOPRASmkbZEVMKguCG+d1hXyXitQYFvCf21K8IhnglK1we9nBCt2NnJWvFxPtIQgk51Ksa5vf8SqR0hJRNnQd4dUPou7Y/tWQJcyan78sw2vAwSerluOFWlbbf68HhP0j+wKmp5FDKENMwJ/pHjUhJlKklFMVLHJXNoBegRHJ1pvsWZt89kPNr/1J4uN2+Kv2yoCD55JzRENJb+ZpfCLN+sm/DM2bS/9BWVZnxdnmDuZjfHhW/El/ougWXog+9/fpX772oBL7XbU4GFS2DkxWViw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM5PR11MB1753.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 84ab666b-6064-438c-6e5e-08d8539a0312 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Sep 2020 01:53:41.3534 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AC0Q3dioskYC2HBrscNyU6O+Y64W+dr0c5amFQ6e2jlAqIhvOxzDZIrQJVte2gSOLAbJpGPMYc4NaHxPrC0cxw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3531 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3] raw/ntb: add Icelake support for Intel NTB X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi > -----Original Message----- > From: Wu, Jingjing > Sent: Tuesday, September 8, 2020 00:16 > To: Li, Xiaoyun > Cc: dev@dpdk.org; Maslekar, Omkar > Subject: RE: [PATCH v3] raw/ntb: add Icelake support for Intel NTB >=20 > > > > - rte_write64(limit, limit_addr); > > > > + if (is_gen3_ntb(hw)) { > > > > + /* Setup the external point so that remote can access. */ > > > > + xlat_off =3D XEON_EMBAR1_OFFSET + 8 * mw_idx; > > > > + xlat_addr =3D hw->hw_addr + xlat_off; > > > > + limit_off =3D XEON_EMBAR1XLMT_OFFSET + > > > > + mw_idx * XEON_BAR_INTERVAL_OFFSET; > > > > + limit_addr =3D hw->hw_addr + limit_off; > > > > + base =3D rte_read64(xlat_addr); > > > > + base &=3D ~0xf; > > > > + limit =3D base + size; > > > > + rte_write64(limit, limit_addr); > > > > + } else if (is_gen4_ntb(hw)) { > > > Can we use a variable in struct to indicate it's gen4 or gen3 after > > > init instead of check it every time? > > > > What's the difference? It comes from the value in hw->pci_dev->id.devic= e_id. > > Checking it in this way is trying to make it easier to extend it for ge= n2 ntb in the > future. > > It's not either gen3 or gen4. > > I don't think it makes sense to have a bool value to indicate it's gen3= or gen4. >=20 > Understand, as the inline function is very simple, it looks OK. > > > > > > > > > + /* Set translate base address index register */ > > > > + xlat_off =3D XEON_GEN4_IM1XBASEIDX_OFFSET + > > > > + mw_idx * XEON_GEN4_XBASEIDX_INTERVAL; > > > > + xlat_addr =3D hw->hw_addr + xlat_off; > > > > + rte_write16(rte_log2_u64(size), xlat_addr); > > > > + } else { > > > > + rte_write64(base, limit_addr); > > > > + rte_write64(0, xlat_addr); > > > > + return -ENOTSUP; > > > > + } > > > Is the else branch necessary? As if neither gen3 or gen4, the init wo= uld fail. > > > Would be better to print an ERR instead of just return NO support. > > > > I don't think so. > > Yes. It will fail in init. Returning err is to stop other following > > actions like in > > intel_ntb_vector_bind() since it should be stopped. > > And I'd like to keep them in one coding style. As to the print, I > > think that can be upper layer's job to check the value and print err. > > Choosing ENOTSUP is because that in init, if it's not supported hw, it > > will return - ENOTSUP err. > > > I cannot say what you did is incorrect. But try to think it like this way= : according > current API design, ntb raw device is allocated when driver probe, if ini= t fails, > raw device would be free. How the ops be called? I'll add a err print later. >=20 > > > > > > > > return 0; > > > > } > > >