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Thu, 8 Oct 2020 09:25:42 +0000 From: "Power, Ciara" To: Olivier Matz CC: "dev@dpdk.org" , Ray Kinsella , Neil Horman , "Richardson, Bruce" Thread-Topic: [dpdk-dev] [PATCH v3 01/18] eal: add max SIMD bitwidth Thread-Index: AQHWlyrBAbDihkshFEi9z+NzKaB/wamKWNOAgAGiw0CAAA0qAIABa+hA Date: Thu, 8 Oct 2020 09:25:42 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-2-ciara.power@intel.com> <20201006093217.GG21395@platinum> <20201007111812.GR21395@platinum> In-Reply-To: <20201007111812.GR21395@platinum> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: 6wind.com; dkim=none (message not signed) header.d=none;6wind.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [78.18.45.234] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 42f4d84d-003b-476d-3e7d-08d86b6c2101 x-ms-traffictypediagnostic: DM5PR11MB1273: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 7iRvF5gHMAr+rPuFcpIPpyx4ylKZv33lu/bgbsBI/+rShc3N2nPirGzVneBG1SR22mA3DR398C1hAMkUL1zfB8EW4cvDtHb10bAGFuNB8N1Q7k12OWviFv7p/hu+XIgH1ajRGNSRgZRiwd8/AmZiTjjZA9Wy7pEEcTUG0mpd5nOGy8bqSgz++hizjCSDCZPWJRnu6OjeUjVCILe7CM7G4V8BDLI4njZKU7xA8QbfJ0V+DL2oNr2eeWUZnYK/c7QKFa2W96Q3dm8IXPpd8RrnvJAkfhTPYLDfzhQPCvTUJnhAzjqNB4fN9U9VOw8/KHnbBBPV4yG0NIJNB+P9aN9PE6+5BgnnsEvlxnTVhx1f9LAhW5kV49indg/z75qX53J11LTH+QeaRoDjlsOAp25QBmNJnTypvzIMEF3QtU/q3nx9PT1aPkfMId1SP0fhC0D68dPGBXo9obyjo6TkjQXmVXafN+/TTZ57uYIg1rDZNernEAYJAcqQa1kXTXFPMkvW8+vsSI+748i2I908DXILKYLx4C4MmB1i5Jq0nY6JlNpIGoH6z3R7iiHURlnOx/6FhJZ6gKAEgTjUnN/Mv1qxHFbwSLTr8mQwhQJF+gEMNg+UGMTfGDBJJhrJlZ50PyByv4rApvDqHNwn7IxKYwe1fQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB2555.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 42f4d84d-003b-476d-3e7d-08d86b6c2101 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2020 09:25:42.6655 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GnSqt+6P6AnQLhURw175BkUtOoeQ35MkQpfVRLAIZ6q+3DQB1P5MptUUwcUo2PXqBLiJ7K/tQ2+n2iXdI6bE1A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1273 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 01/18] eal: add max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Olivier, >-----Original Message----- >From: Olivier Matz >Sent: Wednesday 7 October 2020 12:18 >To: Power, Ciara >Cc: dev@dpdk.org; Ray Kinsella ; Neil Horman >; Richardson, Bruce >Subject: Re: [dpdk-dev] [PATCH v3 01/18] eal: add max SIMD bitwidth > >Hi Ciara, > >On Wed, Oct 07, 2020 at 10:47:34AM +0000, Power, Ciara wrote: >> Hi Olivier, >> >> Thanks for reviewing, some comments below. >> >> >> >-----Original Message----- >> >From: Olivier Matz >> >Sent: Tuesday 6 October 2020 10:32 >> >To: Power, Ciara >> >Cc: dev@dpdk.org; Ray Kinsella ; Neil Horman >> > >> >Subject: Re: [dpdk-dev] [PATCH v3 01/18] eal: add max SIMD bitwidth >> > >> >Hi Ciara, >> > >> >Please find some comments below. >> > >> >On Wed, Sep 30, 2020 at 02:03:57PM +0100, Ciara Power wrote: >> >> This patch adds a max SIMD bitwidth EAL configuration. The API >> >> allows for an app to set this value. It can also be set using EAL >> >> argument --force-max-simd-bitwidth, which will lock the value and >> >> override any modifications made by the app. >> >> >> >> Signed-off-by: Ciara Power >> >> >> >> --- >> >> v3: >> >> - Added enum value to essentially disable using max SIMD to choose >> >> paths, intended for use by ARM SVE. >> >> - Fixed parsing bitwidth argument to return an error for values >> >> greater than uint16_t. >> >> v2: Added to Doxygen comment for API. >> >> --- >> >> >> >> >> >> >> +uint16_t >> >> +rte_get_max_simd_bitwidth(void) >> >> +{ >> >> + const struct internal_config *internal_conf =3D >> >> + eal_get_internal_configuration(); >> >> + return internal_conf->max_simd_bitwidth.bitwidth; >> >> +} >> > >> >Should the return value be enum rte_max_simd_t? >> >If not, do we really need the enum definition? >> > >> >> I kept the return value and param value below as uint16_t to allow for >> arbitrary values, and will allow it be more flexible for future addition= s as >new enums won't need to be added. >> For the set function below, this is used when a user passes the EAL >> command line flag, which passes an integer value rather than an enum one= . >> The enums are useful when checking the max_simd_bitwidth in >> drivers/libs, for example using "RTE_MAX_256_SIMD" instead of "256" in >the condition checks. >> >> >> + >> >> +int >> >> +rte_set_max_simd_bitwidth(uint16_t bitwidth) { >> >> + struct internal_config *internal_conf =3D >> >> + eal_get_internal_configuration(); >> >> + if (internal_conf->max_simd_bitwidth.locked) { >> >> + RTE_LOG(NOTICE, EAL, "Cannot set max SIMD bitwidth - user >> >runtime override enabled"); >> >> + return -EPERM; >> >> + } >> >> + >> >> + if (bitwidth !=3D RTE_MAX_SIMD_DISABLE && (bitwidth < >> >RTE_NO_SIMD || >> >> + !rte_is_power_of_2(bitwidth))) { >> >> + RTE_LOG(ERR, EAL, "Invalid bitwidth value!\n"); >> >> + return -EINVAL; >> >> + } >> >> + internal_conf->max_simd_bitwidth.bitwidth =3D bitwidth; >> >> + return 0; >> >> +} >> > >> >Same question, should the parameter be enum rte_max_simd_t? >> > >> >> >> >> >> +enum rte_max_simd_t { >> >> + RTE_NO_SIMD =3D 64, >> >> + RTE_MAX_128_SIMD =3D 128, >> >> + RTE_MAX_256_SIMD =3D 256, >> >> + RTE_MAX_512_SIMD =3D 512, >> >> + RTE_MAX_SIMD_DISABLE =3D UINT16_MAX, }; >> > >> >What is the difference between RTE_NO_SIMD and >RTE_MAX_SIMD_DISABLE? >> >> RTE_NO_SIMD has value 64 to limit paths to scalar only. >> RTE_MAX_SIMD_DISABLE sets the highest value possible, so essentially >> disables the limit affecting which vector paths are taken. >> This disable option was added to allow for ARM SVE which will be later >> added, Discussed with Honnappa on a previous version: >> https://patchwork.dpdk.org/patch/76097/ > >Ok, so RTE_MAX_SIMD_DISABLE means "disable the max limit", right? > >I feel the name is a bit confusing. What about something like this: > >enum rte_simd { > RTE_SIMD_DISABLED =3D 0, > RTE_SIMD_128 =3D 128, > RTE_SIMD_256 =3D 256, > RTE_SIMD_512 =3D 512, > RTE_SIMD_MAX =3D UINT16_MAX, >}; > > Sure, I can rename these. Although will implement with RTE_SIMD_DISABLED=3D= 64 to allow for scalar path only. >> >> >The default value in internal_config is 0, so in my understanding >> >rte_get_max_simd_bitwidth() will return 0 if >> >--force-max-simd-bitwidth is not passed. Is it expected? >> > >> >Maybe I'm missing something, but I don't understand why the value in >> >internal_config is not set to the maximum supported SIMD bitwidth by >> >default, and optionally overriden by the command line argument, or by >> >the API. >> > >> >> The default value for max_simd_bitwidth is set depending on the >> architecture, 256 for x86/ppc, and UINT16_MAX for ARM. So for example >the default on x86 allows for AVX2 and under. >> The defaults can be seen in patch 2: >> https://patchwork.dpdk.org/patch/79339/ > >Ok, I was expecting to have a runtime check for this. For instance, on int= el >architecture, it is not known at compilation, it depends on the target whi= ch >can support up to AVX, AVX2, or AVX512. > Yes, the actual support will vary, but this max SIMD bitwidth is only an up= per limit on what paths can be taken. So for example with x86 default at 256, the path will still be chosen based= on what the target can support, but it must be AVX2 or a lesser path.=20 This allows for AVX512 to be enabled at runtime, by increasing the max SIMD= bitwidth to 512, allowing for that path to be taken where supported. Thanks, Ciara