From: "Mcnamara, John" <john.mcnamara@intel.com>
To: "Stokes, Ian" <ian.stokes@intel.com>,
"Pai G, Sunil" <sunil.pai.g@intel.com>,
"Hu, Jiayu" <jiayu.hu@intel.com>,
"Ferriter, Cian" <cian.ferriter@intel.com>,
"Van Haaren, Harry" <harry.van.haaren@intel.com>,
Ilya Maximets <i.maximets@ovn.org>,
"Maxime Coquelin (maxime.coquelin@redhat.com)"
<maxime.coquelin@redhat.com>,
"ovs-dev@openvswitch.org" <ovs-dev@openvswitch.org>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: "O'Driscoll, Tim" <tim.odriscoll@intel.com>,
"Finn, Emma" <emma.finn@intel.com>,
Ralf Hoffmann <ralf.hoffmann@allegro-packets.com>,
"Harris, James R" <james.r.harris@intel.com>,
"Luse, Paul E" <paul.e.luse@intel.com>,
"hemal.shah@broadcom.com" <hemal.shah@broadcom.com>,
"Gooch, Stephen" <stephen.gooch@windriver.com>,
Bing Zhao <bingz@nvidia.com>,
"Wiles, Keith" <keith.wiles@intel.com>,
"Prasanna Murugesan (prasanna)" <prasanna@cisco.com>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"Yu, De" <de.yu@intel.com>,
Tom Barbette <tom.barbette@uclouvain.be>,
"Zeng, ZhichaoX" <zhichaox.zeng@intel.com>,
"Knight, Joshua" <Joshua.Knight@netscout.com>,
"Scheurich, Jan" <jan.scheurich@ericsson.com>,
"Sinai, Asaf" <asafsi@radware.com>
Subject: OVS DPDK DMA-Dev library/Design Discussion
Date: Mon, 25 Apr 2022 15:19:21 +0000 [thread overview]
Message-ID: <DM6PR11MB3227E79B99EBD4DFE9D35633FCF89@DM6PR11MB3227.namprd11.prod.outlook.com> (raw)
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Updated with meeting and presentation.
This meeting is a follow-up to the previous calls in March and the discussion which has happened since on the DPDK and OVS mailing lists.
Three approaches were presented in the previous calls:
* "Defer work": Handle DMA completions at OVS PMD thread level
* "v3": Handle DMA Tx completions from Rx context.
* "v3 + lockless ring": Handle DMA Tx completions from Rx context + lockless ring to avoid contention.
After these calls, the discussion continued on the DPDK and OVS mailing lists, where an alternate approach has been proposed.
The newly-suggested approach:
* "DMA VirtQ Completions": Add an additional transaction(s) to each burst of DMA copies; a special transaction containing the memory write operation that makes the descriptors available to the Virtio driver. Also separate the actual kick of the guest with the data transfer.
Agenda for call 26th April:
* Intel team will present slides to help understand the differences in architecture/designs.
* Discuss the strengths/weaknesses/feasibility of the "DMA VirtQ Completions" approach, comparing to current best-candidate "Defer Work".
* Work toward single-solution to be accepted upstream in DPDK and OVS
Slides: https://github.com/Sunil-Pai-G/OVS-DPDK-presentation-share/blob/main/ovs_datapath_design_2022%20session%203.pdf
Google Meet: https://meet.google.com/hme-pygf-bfb
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ORGANIZER;CN="Mcnamara, John":mailto:john.mcnamara@intel.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Stokes, Ia
n":mailto:ian.stokes@intel.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Pai G, Sun
il":mailto:sunil.pai.g@intel.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Hu, Jiayu":
mailto:jiayu.hu@intel.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Ferriter,
Cian":mailto:cian.ferriter@intel.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Van Haaren
, Harry":mailto:harry.van.haaren@intel.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=Ilya Maxim
ets:mailto:i.maximets@ovn.org
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=Maxime Coq
uelin (maxime.coquelin@redhat.com):mailto:maxime.coquelin@redhat.com
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=ovs-dev@op
envswitch.org:mailto:ovs-dev@openvswitch.org
ATTENDEE;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=dev@dpdk.o
rg:mailto:dev@dpdk.org
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="O'Driscoll
, Tim":mailto:tim.odriscoll@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Finn, Emma"
:mailto:emma.finn@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=Ralf Hoffm
ann:mailto:ralf.hoffmann@allegro-packets.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Harris, Ja
mes R":mailto:james.r.harris@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Luse, Paul
E":mailto:paul.e.luse@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=hemal.shah
@broadcom.com:mailto:hemal.shah@broadcom.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Gooch, Ste
phen":mailto:stephen.gooch@windriver.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=Bing Zhao:
mailto:bingz@nvidia.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Wiles, Kei
th":mailto:keith.wiles@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=Prasanna M
urugesan (prasanna):mailto:prasanna@cisco.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Ananyev, K
onstantin":mailto:konstantin.ananyev@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Yu, De":mai
lto:de.yu@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN=Tom Barbet
te:mailto:tom.barbette@uclouvain.be
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Zeng, Zhic
haoX":mailto:zhichaox.zeng@intel.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Knight, Jo
shua":mailto:Joshua.Knight@netscout.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Scheurich,
Jan":mailto:jan.scheurich@ericsson.com
ATTENDEE;ROLE=OPT-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=TRUE;CN="Sinai, Asa
f":mailto:asafsi@radware.com
DESCRIPTION;LANGUAGE=en-US:Updated with meeting and presentation.\n\nThis m
eeting is a follow-up to the previous calls in March and the discussion wh
ich has happened since on the DPDK and OVS mailing lists.\n\nThree approac
hes were presented in the previous calls:\n\n• "Defer work": Handl
e DMA completions at OVS PMD thread level\n• "v3": Handle DMA Tx c
ompletions from Rx context.\n• "v3 + lockless ring": Handle DMA Tx
completions from Rx context + lockless ring to avoid contention.\n\nAfter
these calls\, the discussion continued on the DPDK and OVS mailing lists\
, where an alternate approach has been proposed.\n\nThe newly-suggested ap
proach:\n\n• "DMA VirtQ Completions": Add an additional transactio
n(s) to each burst of DMA copies\; a special transaction containing the me
mory write operation that makes the descriptors available to the Virtio dr
iver. Also separate the actual kick of the guest with the data transfer.\n
\nAgenda for call 26th April:\n\n• Intel team will present slides
to help understand the differences in architecture/designs.\n• Dis
cuss the strengths/weaknesses/feasibility of the "DMA VirtQ Completions" a
pproach\, comparing to current best-candidate "Defer Work".\n• Wor
k toward single-solution to be accepted upstream in DPDK and OVS\n\nSlides
: https://github.com/Sunil-Pai-G/OVS-DPDK-presentation-share/blob/main/ovs
_datapath_design_2022%20session%203.pdf\n\nGoogle Meet: https://meet.googl
e.com/hme-pygf-bfb\n\n\n\n\n\n
UID:040000008200E00074C5B7101A82E0080000000000DED7A59755D801000000000000000
0100000001E85284E2C159341818ACDC3087374E1
SUMMARY;LANGUAGE=en-US:OVS DPDK DMA-Dev library/Design Discussion
DTSTART;TZID=GMT Standard Time:20220426T140000
DTEND;TZID=GMT Standard Time:20220426T150000
CLASS:PUBLIC
PRIORITY:5
DTSTAMP:20220425T151916Z
TRANSP:OPAQUE
STATUS:CONFIRMED
SEQUENCE:1
LOCATION;LANGUAGE=en-US:https://meet.google.com/hme-pygf-bfb
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next reply other threads:[~2022-04-25 15:19 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 15:19 Mcnamara, John [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-04-21 14:57 Mcnamara, John
[not found] <DM6PR11MB3227AC0014F321EB901BE385FC199@DM6PR11MB3227.namprd11.prod.outlook.com>
2022-04-21 11:51 ` Mcnamara, John
2022-03-24 15:36 Stokes, Ian
2022-03-28 18:19 ` Pai G, Sunil
2022-03-29 12:51 ` Morten Brørup
2022-03-29 13:01 ` Van Haaren, Harry
2022-03-29 14:44 ` Morten Brørup
2022-03-29 16:24 ` Maxime Coquelin
2022-03-29 16:45 ` Morten Brørup
2022-03-29 17:03 ` Bruce Richardson
2022-03-29 17:13 ` Morten Brørup
2022-03-29 17:45 ` Ilya Maximets
2022-03-29 18:46 ` Morten Brørup
2022-03-30 2:02 ` Hu, Jiayu
2022-03-30 9:25 ` Maxime Coquelin
2022-03-30 10:20 ` Bruce Richardson
2022-03-30 14:27 ` Hu, Jiayu
2022-03-29 17:46 ` Van Haaren, Harry
2022-03-29 19:59 ` Morten Brørup
2022-03-30 9:01 ` Van Haaren, Harry
2022-04-07 14:04 ` Van Haaren, Harry
2022-04-07 14:25 ` Maxime Coquelin
2022-04-07 14:39 ` Ilya Maximets
2022-04-07 14:42 ` Van Haaren, Harry
2022-04-07 15:01 ` Ilya Maximets
2022-04-07 15:46 ` Maxime Coquelin
2022-04-07 16:04 ` Bruce Richardson
2022-04-08 7:13 ` Hu, Jiayu
2022-04-08 8:21 ` Morten Brørup
2022-04-08 9:57 ` Ilya Maximets
2022-04-20 15:39 ` Mcnamara, John
2022-04-20 16:41 ` Mcnamara, John
2022-04-25 21:46 ` Ilya Maximets
2022-04-27 14:55 ` Mcnamara, John
2022-04-27 20:34 ` Bruce Richardson
2022-04-28 12:59 ` Ilya Maximets
2022-04-28 13:55 ` Bruce Richardson
2022-05-03 19:38 ` Van Haaren, Harry
2022-05-10 14:39 ` Van Haaren, Harry
2022-05-24 12:12 ` Ilya Maximets
2022-03-30 10:41 ` Ilya Maximets
2022-03-30 10:52 ` Ilya Maximets
2022-03-30 11:12 ` Bruce Richardson
2022-03-30 11:41 ` Ilya Maximets
2022-03-30 14:09 ` Bruce Richardson
2022-04-05 11:29 ` Ilya Maximets
2022-04-05 12:07 ` Bruce Richardson
2022-04-08 6:29 ` Pai G, Sunil
2022-05-13 8:52 ` fengchengwen
2022-05-13 9:10 ` Bruce Richardson
2022-05-13 9:48 ` fengchengwen
2022-05-13 10:34 ` Bruce Richardson
2022-05-16 9:04 ` Morten Brørup
[not found] <DM8PR11MB5605B4A5DBD79FFDB4B1C3B2BD0A9@DM8PR11MB5605.namprd11.prod.outlook.com>
2022-03-21 18:23 ` Pai G, Sunil
2022-03-15 15:48 Stokes, Ian
2022-03-15 13:17 Stokes, Ian
2022-03-15 11:15 Stokes, Ian
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