From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B0A3A00BE; Tue, 14 Jun 2022 10:43:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9945E4069C; Tue, 14 Jun 2022 10:43:07 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id D850C4068E for ; Tue, 14 Jun 2022 10:43:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655196186; x=1686732186; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=MnBuWXa0cDOTJOaKLgwAqkfMRkeFge1M3yi6QfA6HH0=; b=XK0OOFpcZdjq8AGzqpMxWlvboIHshp4GXwbWpIw9sLA/M5hMUeqbgkdy e9A5ijU589lYy3Dm1Y5fuE7wTJeGD2xX7jdTLH3rDA6TBdKdOKGUa82YV NSA0jKkVzh9g4yAJjWNS0wsEhOawqFV/E7uApT0QHK3cyC6TiHhxZQgTK rVSd1YU/9Q8MAkAs+j7xf0oaPzt6cN67I08juSZETwG+T3SbC9vi0iK9g NrMVV/wQNqO6MexT6yE9cIOdvSksXlx+utZWs9vHdSeeXLKw6SCjqgU0L hUCv1qC9iVaz4vBNHDYw0pvjPc4upDtCH4lJyHbALFJbAg82DFd6O9JxW A==; X-IronPort-AV: E=McAfee;i="6400,9594,10377"; a="258387615" X-IronPort-AV: E=Sophos;i="5.91,299,1647327600"; d="scan'208";a="258387615" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2022 01:43:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,299,1647327600"; d="scan'208";a="535481973" Received: from fmsmsx604.amr.corp.intel.com ([10.18.126.84]) by orsmga003.jf.intel.com with ESMTP; 14 Jun 2022 01:43:02 -0700 Received: from fmsmsx606.amr.corp.intel.com (10.18.126.86) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Tue, 14 Jun 2022 01:43:02 -0700 Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Tue, 14 Jun 2022 01:43:02 -0700 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (104.47.58.106) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.27; Tue, 14 Jun 2022 01:43:01 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N1RmRLhQP+qFw/FImnpQB+N4UAMJ+VtHiaycdNfx6yqJ39JjXhfUcs7AofzFs4G29X0mkyaduZ0aK1+Kuw3U0K4nn4PRZBvsQi6qsTuhCAB5V6ejNmvIcUsn1OuUSCyw4NvMg/Fsy5WQNX1B4xgKmtygJLmVXlh3gT0sjrPdx1+PGCrA7//u6nfY/+L7xRbXPZlwlzUn+20+xKyRxdNOQ7a/+9/3UGDJWtj9/awAo4f5yQwWAjbJ826sVr8eh3YpqHAxV7j7KKkRV0baOCUSOEkJWe/qXZVl+kdH23r8T7aJnD4mSmxa5lPM13jlvZay7kyx6iyp2Yf1e6ih/rjN4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=V6DGhDluWg9r1jQVr+z4Qs0/bi1agnYVp8ZyZ383LrI=; b=V4fLfZrIwRUtP8vrUpV46WKd+65OjBgf3kFPEfLSNfUbR/57eDXwwkv63v1avX/e8P0QZg1kJUWZQ2bXUfI8bSEGw3V8me/atVWX9CJjpwCw8sg+1Jt5CuO72dpChGD3CIa4CI8lUxZWBmIacz6x7eJV+P+oHsxroKc2TDrA3/g8pls8Z5pMZiQ99nejr0/Ds4ogcG1TmGZrtzvgxENuVTUjOJbxYxTSOaajo5ZSX+9ErC/uy5bAB8XqsZKG9To0nWXfzIOL6iSFY9x5OvTTu8Oy8DhC5P0+1eH+LsGlmlG5sCPG5SL3D4pLbAY1KEIZo5IX5Hl78kHKS5RXGBx02w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from DM6PR11MB3673.namprd11.prod.outlook.com (2603:10b6:5:145::26) by DM6PR11MB4009.namprd11.prod.outlook.com (2603:10b6:5:193::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5332.19; Tue, 14 Jun 2022 08:43:00 +0000 Received: from DM6PR11MB3673.namprd11.prod.outlook.com ([fe80::2d4c:ca2d:45b0:64cd]) by DM6PR11MB3673.namprd11.prod.outlook.com ([fe80::2d4c:ca2d:45b0:64cd%5]) with mapi id 15.20.5332.022; Tue, 14 Jun 2022 08:43:00 +0000 From: "Liu, KevinX" To: "Zhang, Yuying" , "dev@dpdk.org" CC: "Xing, Beilei" , "Yang, SteveX" , "Zhang, RobinX" Subject: RE: [PATCH v7] net/i40e: add outer VLAN processing Thread-Topic: [PATCH v7] net/i40e: add outer VLAN processing Thread-Index: AQHYfKRlbKPdde+F/USGyq3kCtM4PK1ON8cAgAAExMCAAF7DAIAAAFfw Date: Tue, 14 Jun 2022 08:43:00 +0000 Message-ID: References: <20220610155216.81289-1-kevinx.liu@intel.com> <20220610162944.99526-1-kevinx.liu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6fa164e7-dc3f-4bc1-91cf-08da4de1e353 x-ms-traffictypediagnostic: DM6PR11MB4009:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: LsTAAt3nXS9uGE/8/c3wYQEkCcs8Z/lO5ySgyFjD4l+GpuEtxSTIJnT36Q+U9epM+wuvCSzcDEmIThEvmchgezddxVRNLk8jMvPORg0oBZLTuItNPjxTPmvUgoF2SH3s9AchFPGTu/rdgUOZmElVIdCIYU9iTcwFSHUZHu6sK/l4yK1qdGy7MtWF7Eo4mAA9HKWbdcL93gNXgjJc3xou/C8BxResVjQxUW3xto2D2RyeeSi+pdyjOnTo7chZIvIvlEgVBVI+FJkEzpzUttpWCn7/h72vJ/uSKxhDK9v2ndLOrwImpndpNFfkQK5w3RoFJ48733lukc6Eo9isqvf0ZJdEQwWz04vflKA5w8yl/i1nRBJlbHT3E+6E0gk+ZQX6xLHiBXtgkP9fpA0RtsokHk8ft5l+OakcAriWeLJxUo4qhrukB9Lc8Lgjb3/Tu4BwCmFp9OGc7U8lhjXpCNEOMEHURvYXwzq/V56P7KznfSkzw3Ivxtfj4YgBAdCCGNbkz7Og/ogmbog1bBIpNrXkInqM/3YK3yGQW7K9TBkVBOUgdqSt1wcZVg9usNNrDxIN4L8tximgIgee8KGb2+1noF+H9bK5lUK4Z+yU6hqt/y/qntCEXy7m0MD4dIKOuumiNXFiZYardA3snvDQU08vzO8wx8gTO43Yb8oAkzam04I/96fMp54eVV9Y3/J5IAoF/nltTI5pqD5uuS06to15jg== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR11MB3673.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(366004)(38100700002)(54906003)(110136005)(122000001)(186003)(6506007)(107886003)(7696005)(4326008)(83380400001)(82960400001)(76116006)(316002)(8676002)(71200400001)(66446008)(66946007)(66476007)(64756008)(508600001)(5660300002)(52536014)(33656002)(8936002)(30864003)(53546011)(86362001)(55016003)(26005)(2906002)(38070700005)(9686003)(66556008); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-2022-jp?B?Tm5DVmY4SDdTOVBJcXdnc29aZm1Ccno4bUNiL2tlcm9PRGdyRjJEOEw3?= =?iso-2022-jp?B?S2NJdUk2enFqK3pTV3MyMTFaOVg4OW9rdlZZbkRPVmlPMzRIWDA2UDJJ?= =?iso-2022-jp?B?MERPTWExeHUvekVEeXhYalhIQm5ob2x0cDc0RmxqaUxpOVRKem9TM3Jm?= =?iso-2022-jp?B?MjRDWWFQdnNiOTRtOFBIdlJ4Rk42Zkl5a1E0VHpNRDg5b09aSS90ZG5h?= =?iso-2022-jp?B?QVU3bWozYXRrYURMN1NuemZHQmxsTC83TjlCc01FZlVZYVhBS1N4QzhV?= =?iso-2022-jp?B?NDlXQ3lVeGp3YlhHcy91RUZnZlhwK2FRYVEzdHVCOVZQQmpaM1dvMTNz?= =?iso-2022-jp?B?QnJWUkx3N3VJMm9UM0M1b21VOTFzYXYrK1FWNERnRUVJQldxL21EdXhm?= =?iso-2022-jp?B?NHZrOHd5dFlZc2FkcU51anNJWHNTL2FHdkpDamE4b1lYajVEV2Ntckdv?= =?iso-2022-jp?B?RThwRis5UGpnODlBWllJMGdVRWd2QmVTSUpKUUQ3c2JoZzF2VzZ6dXhu?= =?iso-2022-jp?B?WTBwN2tDTWR2bkNCcC9wSFFFL1BZcGdBa0VVRURhSlJoalkyLytwTFhZ?= =?iso-2022-jp?B?WE5CaEhkY1JOWnY5aVVnNVhpMjN5aFRQSUQveDh0dGl4dUlkYkNIdU5u?= =?iso-2022-jp?B?MHNHakl4MVp4N1JlbjFvK0p4U3hVTVFtTU4zcWxSc2wzclRCdWlUL3Z0?= =?iso-2022-jp?B?UkFiN0h3WnNLb0xrZWhXN0J0a3dxUERDN0hlSXQrVHU0cjl0aUpRcEIr?= =?iso-2022-jp?B?UUMrRm1yV3FSU0dSZ0RPV2ovUkpJdzM4UEtxeXdub3JWYWRIRkIwUFRq?= =?iso-2022-jp?B?L25pNFpoSlFaMEJKK0Zqemo4Q1lmL1JQK0FONm8xbThPZVBnNG9jM0J1?= =?iso-2022-jp?B?bUxjMEY2cEVMRmxnU1BhRkFEZURTVlBHSFJHVGNzdjVTQUgyV1VaTkVR?= =?iso-2022-jp?B?T2NxNXpheWh5VXY1bXlJd3M5UUpodEpYUm9xbXhia2dNKy9WQkJFd3E2?= =?iso-2022-jp?B?K2VjL2U4NXFac09udW1lR2V0ZWRheEg1clhqTFRjUVovSHFWMUdveTBW?= =?iso-2022-jp?B?VnRzbXJ3K1NaMGFUNldkRnNWM3RZaEppQm1GS0cra241ZVUrU2Z5QkhJ?= =?iso-2022-jp?B?OENmazBzTHFJVld3ZkdEVy96OGx3TmpKTldUSTY0bGNGRUt4cVBkeDV5?= =?iso-2022-jp?B?K1hMM3hBdVpUSWhpL3lSc295M3hGUllJR3hmVVloTjc1a1o2VnozRlNW?= =?iso-2022-jp?B?bXM4OThBa08zbVpRd0FtR0FWanVxYjlWZzBmSkpSWXZwaFN2Y0FBOTNH?= =?iso-2022-jp?B?dlR3VXBXeWlUbTNUYUZWUXpITDZkejNWOGE0TTVBSlR2dTJlejdjNTFy?= =?iso-2022-jp?B?bVBhMHdQNU1FdlZnMDlSa0RpOG1yQkZvbkxyVmNzUldESDB5NkVpby8y?= =?iso-2022-jp?B?MWlGM1BRYlhQZTRYZzNqVEJWVFp1Qk45L0tkTDhkQjVOdFZpcERsWGJ1?= =?iso-2022-jp?B?WGtMNGR5d01vMGV0UmZTQWlVdkxYYnFMd1BMZWpHcmwvbURXa2dwMnR2?= =?iso-2022-jp?B?bE01UENqSkx6bEtUc2RWYU03RTFDMlVnTVc3L3YxSnVnTnArVll1bGFK?= =?iso-2022-jp?B?UFFiOTRIeWJKWk1sdzcvWG5LR2Vqd3kreWhkaFRmOXozd20rUU5xNm1m?= =?iso-2022-jp?B?d1RNM0hnbFNmcXpyY1M0MzJ6eWdxRk5yWjYwaDdyLzBBbkdCMHhhM1Mx?= =?iso-2022-jp?B?Y2toWm5VRldFZmxJeHNjckhJdGltTHZ1REtVbmdPbWRWencyRWlKRU9j?= =?iso-2022-jp?B?VVR4WmNKY3VFc2JQZVNVWHluZHhsRVhBbXR6bGF1VFY3YVJrbXhjV0tI?= =?iso-2022-jp?B?RWhteW1hZnd4OVN3ckRkZkpVQUdBcjJyaXoyVHZmWWcxQzJ6NGZUL3dO?= =?iso-2022-jp?B?NHQ4cFJEbVJEdUtPQkpPTnYxRVZvZFEzYWlIb01VOHVVZ0NZZlpwVDRS?= =?iso-2022-jp?B?ZTc1allMVnNhdzFGNmVENVpVdGlhU3NnQUlsTzVaSjRrS3Qxc1prOExk?= =?iso-2022-jp?B?UzkwKzgzaEwxclB4V21iZjdPWXNneFdNRXJXTjBOclAxMWMxK1RpRGlM?= =?iso-2022-jp?B?T3NOZGJnMEJENUtLWk5IZG5VR21XSnRteTNxcDY5b2EyUXhuWm9HVTNF?= =?iso-2022-jp?B?VDJvb2wwRmhyOXBLVkNvOHlVSy9QUEcwelRKZVZhT2Jyd3E2dXRvSzQ3?= =?iso-2022-jp?B?aWdqa0kwUFlhK051UzBjS1VOa2NoUmxmaGpTeDluSklmR0NIa1NKRjBj?= =?iso-2022-jp?B?T2RNWlgvSHdaOGpab1lPMnB3N1ZCUkQyU0JMSmpFb2s4dU81L0ZYMkhv?= =?iso-2022-jp?B?WHhUR25CdTJ2ZC9BMW4vWmh5VGJ1U0t6SmFoVmxSRXlWWWJtK1B1dnph?= =?iso-2022-jp?B?Yk9YNXIrTGJ2ZXV1ZnFuNlFyS3Q4ME43ZkVrbXBVZXBPNCt4ck5RZDdR?= =?iso-2022-jp?B?Qi9QUDdlYWhNbXlvVVJKODlTV0NrMGozaGl4UT09?= Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3673.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6fa164e7-dc3f-4bc1-91cf-08da4de1e353 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Jun 2022 08:43:00.3075 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wdwYsHbLPCYdzzuXNvGJ5zmx96zz7fnMQz7okjQag/sSd5fND+oHA7/wdqojy9oJZdrMHlNcWczBxI1pbkgqaw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4009 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Yes, that is necessary. Thank you very much for your review! > -----Original Message----- > From: Zhang, Yuying > Sent: 2022=1B$BG/=1B(B6=1B$B7n=1B(B14=1B$BF|=1B(B 16:40 > To: Liu, KevinX ; dev@dpdk.org > Cc: Xing, Beilei ; Yang, SteveX > ; Zhang, RobinX > Subject: RE: [PATCH v7] net/i40e: add outer VLAN processing >=20 > Hi Kevin, >=20 > Workaround should be replaced when root cause be found. >=20 > Best regards, > Yuying >=20 > > -----Original Message----- > > From: Liu, KevinX > > Sent: Tuesday, June 14, 2022 11:07 AM > > To: Zhang, Yuying ; dev@dpdk.org > > Cc: Xing, Beilei ; Yang, SteveX > > ; Zhang, RobinX > > Subject: RE: [PATCH v7] net/i40e: add outer VLAN processing > > > > Hi, Yuying > > > > > -----Original Message----- > > > From: Zhang, Yuying > > > Sent: 2022=1B$BG/=1B(B6=1B$B7n=1B(B14=1B$BF|=1B(B 10:44 > > > To: Liu, KevinX ; dev@dpdk.org > > > Cc: Xing, Beilei ; Yang, SteveX > > > ; Zhang, RobinX > > > Subject: RE: [PATCH v7] net/i40e: add outer VLAN processing > > > > > > Hi Kevin, > > > > > > > -----Original Message----- > > > > From: Liu, KevinX > > > > Sent: Saturday, June 11, 2022 12:30 AM > > > > To: dev@dpdk.org > > > > Cc: Zhang, Yuying ; Xing, Beilei > > > > ; Yang, SteveX ; > > > > Zhang, RobinX ; Liu, KevinX > > > > > > > > Subject: [PATCH v7] net/i40e: add outer VLAN processing > > > > > > > > From: Robin Zhang > > > > > > > > Outer VLAN processing is supported after firmware v8.4, kernel > > > > driver also > > > > > > Since this patch can only be enabled with firmware v8.6, should you > > > sync with dpdk here? > > OK, I'll revise it here. > > > > > > > change the default behavior to support this feature. To align with > > > > kernel driver, add support for outer VLAN processing in DPDK. > > > > > > > > But it is forbidden for firmware to change the Inner/Outer VLAN > > > > configuration while there are MAC/VLAN filters in the switch table. > > > > Therefore, we need to clear the MAC table before setting config, > > > > and then restore the MAC table after setting. > > > > > > > > This will not impact on an old firmware. > > > > > > > > Signed-off-by: Robin Zhang > > > > Signed-off-by: Kevin Liu >=20 > Acked-by: Yuying Zhang >=20 > > > > --- > > > > drivers/net/i40e/i40e_ethdev.c | 94 > > > > ++++++++++++++++++++++++++++++++-- > > > > drivers/net/i40e/i40e_ethdev.h | 3 ++ > > > > 2 files changed, 92 insertions(+), 5 deletions(-) > > > > > > > > diff --git a/drivers/net/i40e/i40e_ethdev.c > > > > b/drivers/net/i40e/i40e_ethdev.c index 755786dc10..4cae163cb9 > > > > 100644 > > > > --- a/drivers/net/i40e/i40e_ethdev.c > > > > +++ b/drivers/net/i40e/i40e_ethdev.c > > > > @@ -2575,6 +2575,7 @@ i40e_dev_close(struct rte_eth_dev *dev) > > > > struct i40e_hw *hw =3D I40E_DEV_PRIVATE_TO_HW(dev->data- > > > > >dev_private); > > > > struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > > > > struct rte_intr_handle *intr_handle =3D pci_dev->intr_handle; > > > > + struct rte_eth_rxmode *rxmode =3D &dev->data->dev_conf.rxmode; > > > > struct i40e_filter_control_settings settings; > > > > struct rte_flow *p_flow; > > > > uint32_t reg; > > > > @@ -2587,6 +2588,18 @@ i40e_dev_close(struct rte_eth_dev *dev) > > > > if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) > > > > return 0; > > > > > > > > + /* > > > > + * It is a workaround, if the double VLAN is disabled when > > > > + * the program exits, an abnormal error will occur on the > > > > + * NIC. Need to enable double VLAN when dev is closed. > > > > + */ > > > > > > What is the root cause of this error, I suggest finding a true fix > > > instead of adding additonal process here. > > About this error, dpdk has reported a known issue. Because it doesn't > > know the root cause of the problem, it adds a workaround here to > > temporarily avoid some problems. > > > > > > > + if (pf->fw8_3gt) { > > > > + if (!(rxmode->offloads & > > > > RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { > > > > + rxmode->offloads |=3D > > > > RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; > > > > + i40e_vlan_offload_set(dev, > > > > RTE_ETH_VLAN_EXTEND_MASK); > > > > + } > > > > + } > > > > + > > > > ret =3D rte_eth_switch_domain_free(pf->switch_domain_id); > > > > if (ret) > > > > PMD_INIT_LOG(WARNING, "failed to free switch > > > > domain: %d", ret); @@ -3909,6 +3922,7 @@ i40e_vlan_tpid_set(struct > > > > rte_eth_dev *dev, > > > > struct i40e_pf *pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data- > > > > >dev_private); > > > > int qinq =3D dev->data->dev_conf.rxmode.offloads & > > > > RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; > > > > + u16 sw_flags =3D 0, valid_flags =3D 0; > > > > int ret =3D 0; > > > > > > > > if ((vlan_type !=3D RTE_ETH_VLAN_TYPE_INNER && @@ -3927,15 > > > > +3941,32 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, > > > > /* 802.1ad frames ability is added in NVM API 1.7*/ > > > > if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { > > > > if (qinq) { > > > > + if (pf->fw8_3gt) { > > > > + sw_flags =3D > > > > I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; > > > > + valid_flags =3D > > > > I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; > > > > + } > > > > if (vlan_type =3D=3D RTE_ETH_VLAN_TYPE_OUTER) > > > > hw->first_tag =3D rte_cpu_to_le_16(tpid); > > > > else if (vlan_type =3D=3D RTE_ETH_VLAN_TYPE_INNER) > > > > hw->second_tag =3D rte_cpu_to_le_16(tpid); > > > > } else { > > > > - if (vlan_type =3D=3D RTE_ETH_VLAN_TYPE_OUTER) > > > > - hw->second_tag =3D rte_cpu_to_le_16(tpid); > > > > + /* > > > > + * If tpid is equal to 0x88A8, indicates that the > > > > + * disable double VLAN operation is in progress. > > > > + * Need set switch configuration back to default. > > > > + */ > > > > > > I don't suppose we need to set qinq tpid in vlan case. Please > > > explain this situation in details. > > I'll think about how to explain this place. Thank you. > > > > > > > + if (pf->fw8_3gt && tpid =3D=3D RTE_ETHER_TYPE_QINQ) { > > > > + sw_flags =3D 0; > > > > + valid_flags =3D > > > > I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; > > > > + if (vlan_type =3D=3D > > > RTE_ETH_VLAN_TYPE_OUTER) > > > > + hw->first_tag =3D > > > > rte_cpu_to_le_16(tpid); > > > > + } else { > > > > + if (vlan_type =3D=3D > > > RTE_ETH_VLAN_TYPE_OUTER) > > > > + hw->second_tag =3D > > > > rte_cpu_to_le_16(tpid); > > > > + } > > > > } > > > > - ret =3D i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); > > > > + ret =3D i40e_aq_set_switch_config(hw, sw_flags, > > > > + valid_flags, 0, NULL); > > > > if (ret !=3D I40E_SUCCESS) { > > > > PMD_DRV_LOG(ERR, > > > > "Set switch config failed aq_err: %d", @@ - > > > > 3987,8 +4018,13 @@ static int i40e_vlan_offload_set(struct > > > > rte_eth_dev *dev, int mask) { > > > > struct i40e_pf *pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data- > > > > >dev_private); > > > > + struct i40e_mac_filter_info *mac_filter; > > > > struct i40e_vsi *vsi =3D pf->main_vsi; > > > > struct rte_eth_rxmode *rxmode; > > > > + struct i40e_mac_filter *f; > > > > + int i, num; > > > > + void *temp; > > > > + int ret; > > > > > > > > rxmode =3D &dev->data->dev_conf.rxmode; > > > > if (mask & RTE_ETH_VLAN_FILTER_MASK) { @@ -4007,6 +4043,33 > > > @@ > > > > i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) > > > > } > > > > > > > > if (mask & RTE_ETH_VLAN_EXTEND_MASK) { > > > > + i =3D 0; > > > > + num =3D vsi->mac_num; > > > > + mac_filter =3D rte_zmalloc("mac_filter_info_data", > > > > + num * sizeof(*mac_filter), 0); > > > > + if (mac_filter =3D=3D NULL) { > > > > + PMD_DRV_LOG(ERR, "failed to allocate memory"); > > > > + return I40E_ERR_NO_MEMORY; > > > > + } > > > > + > > > > + /* > > > > + * Outer VLAN processing is supported after firmware v8.4, > > > > kernel driver > > > > + * also change the default behavior to support this feature. > > > > To align with > > > > + * kernel driver, set switch config in 'i40e_vlan_tpie_set' to > > > > support for > > > > + * outer VLAN processing. But it is forbidden for firmware to > > > > change the > > > > + * Inner/Outer VLAN configuration while there are > > > > MAC/VLAN filters in the > > > > + * switch table. Therefore, we need to clear the MAC table > > > > before setting > > > > + * config, and then restore the MAC table after setting. This > > > > feature is > > > > + * recommended to be used in firmware v8.6. > > > > + */ > > > > + /* Remove all existing mac */ > > > > + RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) { > > > > + mac_filter[i] =3D f->mac_info; > > > > + ret =3D i40e_vsi_delete_mac(vsi, &f- > > > > >mac_info.mac_addr); > > > > + if (ret) > > > > + PMD_DRV_LOG(ERR, "i40e vsi delete mac > > > > fail."); > > > > + i++; > > > > + } > > > > if (rxmode->offloads & > > > > RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { > > > > i40e_vsi_config_double_vlan(vsi, TRUE); > > > > /* Set global registers with default ethertype. */ @@ > > > > -4014,9 +4077,19 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, > > > > int > > > > mask) > > > > RTE_ETHER_TYPE_VLAN); > > > > i40e_vlan_tpid_set(dev, > > > RTE_ETH_VLAN_TYPE_INNER, > > > > RTE_ETHER_TYPE_VLAN); > > > > - } > > > > - else > > > > + } else { > > > > + if (pf->fw8_3gt) > > > > + i40e_vlan_tpid_set(dev, > > > > RTE_ETH_VLAN_TYPE_OUTER, > > > > + RTE_ETHER_TYPE_QINQ); > > > > i40e_vsi_config_double_vlan(vsi, FALSE); > > > > + } > > > > + /* Restore all mac */ > > > > + for (i =3D 0; i < num; i++) { > > > > + ret =3D i40e_vsi_add_mac(vsi, &mac_filter[i]); > > > > + if (ret) > > > > + PMD_DRV_LOG(ERR, "i40e vsi add mac fail."); > > > > + } > > > > + rte_free(mac_filter); > > > > } > > > > > > > > if (mask & RTE_ETH_QINQ_STRIP_MASK) { @@ -4846,6 +4919,17 > > @@ > > > > i40e_pf_parameter_init(struct rte_eth_dev *dev) > > > > return -EINVAL; > > > > } > > > > > > > > + /** > > > > + * Enable outer VLAN processing if firmware version is greater > > > > + * than v8.3 > > > > + */ > > > > + if (hw->aq.fw_maj_ver > 8 || > > > > + (hw->aq.fw_maj_ver =3D=3D 8 && hw->aq.fw_min_ver > 3)) { > > > > + pf->fw8_3gt =3D true; > > > > + } else { > > > > + pf->fw8_3gt =3D false; > > > > + } > > > > + > > > > return 0; > > > > } > > > > > > > > diff --git a/drivers/net/i40e/i40e_ethdev.h > > > > b/drivers/net/i40e/i40e_ethdev.h index a1ebdc093c..fe943a45ff > > > > 100644 > > > > --- a/drivers/net/i40e/i40e_ethdev.h > > > > +++ b/drivers/net/i40e/i40e_ethdev.h > > > > @@ -1188,6 +1188,9 @@ struct i40e_pf { > > > > /* Switch Domain Id */ > > > > uint16_t switch_domain_id; > > > > > > > > + /* When firmware > 8.3, the enable flag for outer VLAN > > > > +processing > > > */ > > > > + bool fw8_3gt; > > > > + > > > > struct i40e_vf_msg_cfg vf_msg_cfg; > > > > uint64_t prev_rx_bytes; > > > > uint64_t prev_tx_bytes; > > > > -- > > > > 2.34.1