* [dpdk-dev] [PATCH 00/28] ice: base code update
@ 2021-08-10 2:51 Qi Zhang
2021-08-10 2:51 ` [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe Qi Zhang
` (28 more replies)
0 siblings, 29 replies; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang
Summary:
1. Add new module to support 1588 timesync / PTP.
2. Couple FDIR / RSS enhancement to support GRE tunnel and GTPU
3. Support l3/ l4 checksum RSS
Qi Zhang (28):
net/ice/base: add 1588 capability probe
net/ice/base: add low level functions for device clock control
net/ice/base: add ethertype IPv6 check for dummy packet
net/ice/base: change dummy packets with VLAN
net/ice/base: add timestamp masks
net/ice/base: add clock initialization function
net/ice/base: add accessors to get/set the time reference
net/ice/base: print human-friendly PHY types
net/ice/base: implement Vernier calibration logic for E822 devices
net/ice/base: clarify comments on checking PFC mode
net/ice/base: add support for starting PHY in bypass mode
net/ice/base: add E810T check function
net/ice/base: implement firmware debug dump
net/ice/base: add new AQ description
net/ice/base: refine MAC rule adding
net/ice/base: support TC nodes PIR configuration
net/ice/base: support FDIR for GRE tunnel packet
net/ice/base: support RSS for GRE tunnel packet
net/ice/base: support FDIR for GTPU EH inner IPv6
net/ice/base: support RSS for GTPoGRE
net/ice/base: enable NVM update reset capabilities
net/ice/base: support FDIR for GTPoGRE
net/ice/base: add RSS support for IPv4/L4 checksum
net/ice/base: enable jumbo frame support during HW init
net/ice/base: support FDIR for GTPU UL/DL with QFI fields
net/ice/base: rename and add a setter function
net/ice/base: correct spellling of word data
net/ice/base: update Max TCAM/PTG Per Profile
drivers/net/ice/base/ice_adminq_cmd.h | 28 +
drivers/net/ice/base/ice_cgu_regs.h | 117 +
drivers/net/ice/base/ice_common.c | 513 +++-
drivers/net/ice/base/ice_common.h | 21 +
drivers/net/ice/base/ice_controlq.c | 52 +-
drivers/net/ice/base/ice_controlq.h | 2 +
drivers/net/ice/base/ice_dcb.c | 9 +-
drivers/net/ice/base/ice_devids.h | 1 +
drivers/net/ice/base/ice_fdir.c | 2387 ++++++++++++++-
drivers/net/ice/base/ice_fdir.h | 14 +
drivers/net/ice/base/ice_flex_pipe.c | 6 +
drivers/net/ice/base/ice_flex_type.h | 52 +-
drivers/net/ice/base/ice_flow.c | 231 +-
drivers/net/ice/base/ice_flow.h | 10 +
drivers/net/ice/base/ice_lan_tx_rx.h | 8 +
drivers/net/ice/base/ice_protocol_type.h | 4 +-
drivers/net/ice/base/ice_ptp_consts.h | 376 +++
drivers/net/ice/base/ice_ptp_hw.c | 3452 ++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 473 +++
drivers/net/ice/base/ice_sched.c | 3 +
drivers/net/ice/base/ice_switch.c | 172 +-
drivers/net/ice/base/ice_type.h | 231 +-
drivers/net/ice/base/meson.build | 1 +
23 files changed, 7892 insertions(+), 271 deletions(-)
create mode 100644 drivers/net/ice/base/ice_cgu_regs.h
create mode 100644 drivers/net/ice/base/ice_ptp_consts.h
create mode 100644 drivers/net/ice/base/ice_ptp_hw.c
create mode 100644 drivers/net/ice/base/ice_ptp_hw.h
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:31 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 02/28] net/ice/base: add low level functions for device clock control Qi Zhang
` (27 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
Parse 1588 timesync capability during device capability probing.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 111 ++++++++++++++++++++++++++
drivers/net/ice/base/ice_type.h | 72 +++++++++++++++++
3 files changed, 184 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 861f5a39b6..8fc0340c0d 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -108,6 +108,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_TXQS 0x0042
#define ICE_AQC_CAPS_MSIX 0x0043
#define ICE_AQC_CAPS_FD 0x0045
+#define ICE_AQC_CAPS_1588 0x0046
#define ICE_AQC_CAPS_MAX_MTU 0x0047
#define ICE_AQC_CAPS_IWARP 0x0051
#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 51fca7b166..185b900290 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2086,6 +2086,60 @@ ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
func_p->guar_num_vsi);
}
+/**
+ * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for ICE_AQC_CAPS_1588.
+ */
+static void
+ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ struct ice_ts_func_info *info = &func_p->ts_func_info;
+ u32 number = LE32_TO_CPU(cap->number);
+
+ info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
+ func_p->common_cap.ieee_1588 = info->ena;
+
+ info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
+ info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
+ info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
+ info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
+
+ info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
+ info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
+
+ if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
+ info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
+ } else {
+ /* Unknown clock frequency, so assume a (probably incorrect)
+ * default to avoid out-of-bounds look ups of frequency
+ * related information.
+ */
+ ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
+ info->clk_freq);
+ info->time_ref = ICE_TIME_REF_FREQ_25_000;
+ }
+
+ ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
+ func_p->common_cap.ieee_1588);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
+ info->src_tmr_owned);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
+ info->tmr_ena);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
+ info->tmr_index_owned);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
+ info->tmr_index_assoc);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
+ info->clk_freq);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
+ info->clk_src);
+}
+
/**
* ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
* @hw: pointer to the HW struct
@@ -2151,6 +2205,9 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
case ICE_AQC_CAPS_VSI:
ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
break;
+ case ICE_AQC_CAPS_1588:
+ ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
+ break;
case ICE_AQC_CAPS_FD:
ice_parse_fdir_func_caps(hw, func_p);
break;
@@ -2204,6 +2261,57 @@ ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
dev_p->num_vsi_allocd_to_host);
}
+/**
+ * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_1588 for device capabilities.
+ */
+static void
+ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
+ u32 logical_id = LE32_TO_CPU(cap->logical_id);
+ u32 phys_id = LE32_TO_CPU(cap->phys_id);
+ u32 number = LE32_TO_CPU(cap->number);
+
+ info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
+ dev_p->common_cap.ieee_1588 = info->ena;
+
+ info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
+ info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
+ info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
+
+ info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
+ info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
+ info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
+
+ info->ena_ports = logical_id;
+ info->tmr_own_map = phys_id;
+
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
+ dev_p->common_cap.ieee_1588);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
+ info->tmr0_owner);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
+ info->tmr0_owned);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
+ info->tmr0_ena);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
+ info->tmr1_owner);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
+ info->tmr1_owned);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
+ info->tmr1_ena);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
+ info->ena_ports);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
+ info->tmr_own_map);
+}
+
/**
* ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
* @hw: pointer to the HW struct
@@ -2262,6 +2370,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
case ICE_AQC_CAPS_VSI:
ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
break;
+ case ICE_AQC_CAPS_1588:
+ ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
+ break;
case ICE_AQC_CAPS_FD:
ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
break;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2644d5db73..daf1ac6ef6 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -439,6 +439,7 @@ struct ice_hw_common_caps {
u8 dcb;
u8 iscsi;
+ u8 ieee_1588;
u8 mgmt_cem;
/* WoL and APM support */
@@ -469,12 +470,82 @@ struct ice_hw_common_caps {
#define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
};
+/* IEEE 1588 TIME_SYNC specific info */
+/* Function specific definitions */
+#define ICE_TS_FUNC_ENA_M BIT(0)
+#define ICE_TS_SRC_TMR_OWND_M BIT(1)
+#define ICE_TS_TMR_ENA_M BIT(2)
+#define ICE_TS_TMR_IDX_OWND_S 4
+#define ICE_TS_TMR_IDX_OWND_M BIT(4)
+#define ICE_TS_CLK_FREQ_S 16
+#define ICE_TS_CLK_FREQ_M MAKEMASK(0x7, ICE_TS_CLK_FREQ_S)
+#define ICE_TS_CLK_SRC_S 20
+#define ICE_TS_CLK_SRC_M BIT(20)
+#define ICE_TS_TMR_IDX_ASSOC_S 24
+#define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
+
+/* TIME_REF clock rate specification */
+enum ice_time_ref_freq {
+ ICE_TIME_REF_FREQ_25_000 = 0,
+ ICE_TIME_REF_FREQ_122_880 = 1,
+ ICE_TIME_REF_FREQ_125_000 = 2,
+ ICE_TIME_REF_FREQ_153_600 = 3,
+ ICE_TIME_REF_FREQ_156_250 = 4,
+ ICE_TIME_REF_FREQ_245_760 = 5,
+
+ NUM_ICE_TIME_REF_FREQ
+};
+
+/* Clock source specification */
+enum ice_clk_src {
+ ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
+ ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
+
+ NUM_ICE_CLK_SRC
+};
+
+struct ice_ts_func_info {
+ /* Function specific info */
+ enum ice_time_ref_freq time_ref;
+ u8 clk_freq;
+ u8 clk_src;
+ u8 tmr_index_assoc;
+ u8 ena;
+ u8 tmr_index_owned;
+ u8 src_tmr_owned;
+ u8 tmr_ena;
+};
+
+/* Device specific definitions */
+#define ICE_TS_TMR0_OWNR_M 0x7
+#define ICE_TS_TMR0_OWND_M BIT(3)
+#define ICE_TS_TMR1_OWNR_S 4
+#define ICE_TS_TMR1_OWNR_M MAKEMASK(0x7, ICE_TS_TMR1_OWNR_S)
+#define ICE_TS_TMR1_OWND_M BIT(7)
+#define ICE_TS_DEV_ENA_M BIT(24)
+#define ICE_TS_TMR0_ENA_M BIT(25)
+#define ICE_TS_TMR1_ENA_M BIT(26)
+
+struct ice_ts_dev_info {
+ /* Device specific info */
+ u32 ena_ports;
+ u32 tmr_own_map;
+ u32 tmr0_owner;
+ u32 tmr1_owner;
+ u8 tmr0_owned;
+ u8 tmr1_owned;
+ u8 ena;
+ u8 tmr0_ena;
+ u8 tmr1_ena;
+};
+
/* Function specific capabilities */
struct ice_hw_func_caps {
struct ice_hw_common_caps common_cap;
u32 guar_num_vsi;
u32 fd_fltr_guar; /* Number of filters guaranteed */
u32 fd_fltr_best_effort; /* Number of best effort filters */
+ struct ice_ts_func_info ts_func_info;
};
/* Device wide capabilities */
@@ -482,6 +553,7 @@ struct ice_hw_dev_caps {
struct ice_hw_common_caps common_cap;
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
+ struct ice_ts_dev_info ts_dev_info;
u32 num_funcs;
};
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 02/28] net/ice/base: add low level functions for device clock control
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
2021-08-10 2:51 ` [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:33 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 03/28] net/ice/base: add ethertype IPv6 check for dummy packet Qi Zhang
` (26 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
The ice hardware supports exposing a hardware clock for high precision
timestamping. This is primarily intended for accelerating the Precision
Time Protocol.
Add several low level functions intended to be used as the basis for
enabling the device clock, and ensuring that the port timers are
synchronized properly.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 143 ++
drivers/net/ice/base/ice_common.h | 11 +
drivers/net/ice/base/ice_controlq.c | 52 +-
drivers/net/ice/base/ice_controlq.h | 2 +
drivers/net/ice/base/ice_ptp_consts.h | 86 ++
drivers/net/ice/base/ice_ptp_hw.c | 2023 +++++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 376 +++++
drivers/net/ice/base/ice_type.h | 3 +
drivers/net/ice/base/meson.build | 1 +
10 files changed, 2697 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ice/base/ice_ptp_consts.h
create mode 100644 drivers/net/ice/base/ice_ptp_hw.c
create mode 100644 drivers/net/ice/base/ice_ptp_hw.h
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 8fc0340c0d..74c4e8f120 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -3077,6 +3077,7 @@ enum ice_adminq_opc {
ice_aqc_opc_set_event_mask = 0x0613,
ice_aqc_opc_set_mac_lb = 0x0620,
ice_aqc_opc_get_link_topo = 0x06E0,
+ ice_aqc_opc_get_link_topo_pin = 0x06E1,
ice_aqc_opc_read_i2c = 0x06E2,
ice_aqc_opc_write_i2c = 0x06E3,
ice_aqc_opc_set_port_id_led = 0x06E9,
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 185b900290..e8d66aad6b 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -64,6 +64,28 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)
return ICE_SUCCESS;
}
+/**
+ * ice_is_generic_mac
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if mac_type is ICE_MAC_GENERIC, false if not
+ */
+bool ice_is_generic_mac(struct ice_hw *hw)
+{
+ return hw->mac_type == ICE_MAC_GENERIC;
+}
+
+/**
+ * ice_is_e810
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E810 based, false if not.
+ */
+bool ice_is_e810(struct ice_hw *hw)
+{
+ return hw->mac_type == ICE_MAC_E810;
+}
+
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
@@ -1350,6 +1372,127 @@ ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
return ICE_SUCCESS;
}
+/* Sideband Queue command wrappers */
+
+/**
+ * ice_get_sbq - returns the right control queue to use for sideband
+ * @hw: pointer to the hardware structure
+ */
+static struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw)
+{
+ if (!ice_is_generic_mac(hw))
+ return &hw->adminq;
+ return &hw->sbq;
+}
+
+/**
+ * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
+ * @hw: pointer to the HW struct
+ * @desc: descriptor describing the command
+ * @buf: buffer to use for indirect commands (NULL for direct commands)
+ * @buf_size: size of buffer for indirect commands (0 for direct commands)
+ * @cd: pointer to command details structure
+ */
+static enum ice_status
+ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
+ void *buf, u16 buf_size, struct ice_sq_cd *cd)
+{
+ return ice_sq_send_cmd(hw, ice_get_sbq(hw), (struct ice_aq_desc *)desc,
+ buf, buf_size, cd);
+}
+
+/**
+ * ice_sbq_send_cmd_nolock - send Sideband Queue command to Sideband Queue
+ * but do not lock sq_lock
+ * @hw: pointer to the HW struct
+ * @desc: descriptor describing the command
+ * @buf: buffer to use for indirect commands (NULL for direct commands)
+ * @buf_size: size of buffer for indirect commands (0 for direct commands)
+ * @cd: pointer to command details structure
+ */
+static enum ice_status
+ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
+ void *buf, u16 buf_size, struct ice_sq_cd *cd)
+{
+ return ice_sq_send_cmd_nolock(hw, ice_get_sbq(hw),
+ (struct ice_aq_desc *)desc, buf,
+ buf_size, cd);
+}
+
+/**
+ * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter
+ * @hw: pointer to the HW struct
+ * @in: message info to be filled in descriptor
+ * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has
+ * already been locked at a higher level
+ */
+enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
+ struct ice_sbq_msg_input *in, bool lock)
+{
+ struct ice_sbq_cmd_desc desc = {0};
+ struct ice_sbq_msg_req msg = {0};
+ enum ice_status status;
+ u16 msg_len;
+
+ msg_len = sizeof(msg);
+
+ msg.dest_dev = in->dest_dev;
+ msg.opcode = in->opcode;
+ msg.flags = ICE_SBQ_MSG_FLAGS;
+ msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
+ msg.msg_addr_low = CPU_TO_LE16(in->msg_addr_low);
+ msg.msg_addr_high = CPU_TO_LE32(in->msg_addr_high);
+
+ if (in->opcode)
+ msg.data = CPU_TO_LE32(in->data);
+ else
+ /* data read comes back in completion, so shorten the struct by
+ * sizeof(msg.data)
+ */
+ msg_len -= sizeof(msg.data);
+
+ desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
+ desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req);
+ desc.param0.cmd_len = CPU_TO_LE16(msg_len);
+ if (lock)
+ status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
+ else
+ status = ice_sbq_send_cmd_nolock(hw, &desc, &msg, msg_len,
+ NULL);
+ if (!status && !in->opcode)
+ in->data = LE32_TO_CPU
+ (((struct ice_sbq_msg_cmpl *)&msg)->data);
+ return status;
+}
+
+/**
+ * ice_sbq_rw_reg - Fill Sideband Queue command
+ * @hw: pointer to the HW struct
+ * @in: message info to be filled in descriptor
+ */
+enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in)
+{
+ return ice_sbq_rw_reg_lp(hw, in, true);
+}
+
+/**
+ * ice_sbq_lock - Lock the sideband queue's sq_lock
+ * @hw: pointer to the HW struct
+ */
+void ice_sbq_lock(struct ice_hw *hw)
+{
+ ice_acquire_lock(&ice_get_sbq(hw)->sq_lock);
+}
+
+/**
+ * ice_sbq_unlock - Unlock the sideband queue's sq_lock
+ * @hw: pointer to the HW struct
+ */
+void ice_sbq_unlock(struct ice_hw *hw)
+{
+ ice_release_lock(&ice_get_sbq(hw)->sq_lock);
+}
+
/* FW Admin Queue command wrappers */
/**
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 22ea89cbbb..de7592ba13 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -51,6 +51,10 @@ ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
enum ice_adminq_opc opc, struct ice_sq_cd *cd);
enum ice_status
+ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+ struct ice_aq_desc *desc, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd);
+enum ice_status
ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
struct ice_sq_cd *cd);
@@ -215,6 +219,11 @@ enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
void ice_replay_post(struct ice_hw *hw);
struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
+enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
+ struct ice_sbq_msg_input *in, bool lock);
+void ice_sbq_lock(struct ice_hw *hw);
+void ice_sbq_unlock(struct ice_hw *hw);
+enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
void
ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
@@ -226,6 +235,8 @@ ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
struct ice_eth_stats *cur_stats);
enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
void ice_print_rollback_msg(struct ice_hw *hw);
+bool ice_is_generic_mac(struct ice_hw *hw);
+bool ice_is_e810(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_txsched_elem_data *buf);
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 93f7bc0274..cdd067ce7f 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -54,6 +54,21 @@ static void ice_mailbox_init_regs(struct ice_hw *hw)
ICE_CQ_INIT_REGS(cq, PF_MBX);
}
+/**
+ * ice_sb_init_regs - Initialize Sideband registers
+ * @hw: pointer to the hardware structure
+ *
+ * This assumes the alloc_sq and alloc_rq functions have already been called
+ */
+static void ice_sb_init_regs(struct ice_hw *hw)
+{
+ struct ice_ctl_q_info *cq = &hw->sbq;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ ICE_CQ_INIT_REGS(cq, PF_SB);
+}
+
/**
* ice_check_sq_alive
* @hw: pointer to the HW struct
@@ -584,6 +599,10 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
ice_adminq_init_regs(hw);
cq = &hw->adminq;
break;
+ case ICE_CTL_Q_SB:
+ ice_sb_init_regs(hw);
+ cq = &hw->sbq;
+ break;
case ICE_CTL_Q_MAILBOX:
ice_mailbox_init_regs(hw);
cq = &hw->mailboxq;
@@ -620,6 +639,18 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
return ret_code;
}
+/**
+ * ice_is_sbq_supported - is the sideband queue supported
+ * @hw: pointer to the hardware structure
+ *
+ * Returns true if the sideband control queue interface is
+ * supported for the device, false otherwise
+ */
+static bool ice_is_sbq_supported(struct ice_hw *hw)
+{
+ return ice_is_generic_mac(hw);
+}
+
/**
* ice_shutdown_ctrlq - shutdown routine for any control queue
* @hw: pointer to the hardware structure
@@ -639,6 +670,9 @@ static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
if (ice_check_sq_alive(hw, cq))
ice_aq_q_shutdown(hw, true);
break;
+ case ICE_CTL_Q_SB:
+ cq = &hw->sbq;
+ break;
case ICE_CTL_Q_MAILBOX:
cq = &hw->mailboxq;
break;
@@ -663,6 +697,9 @@ void ice_shutdown_all_ctrlq(struct ice_hw *hw)
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
/* Shutdown FW admin queue */
ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
+ /* Shutdown PHY Sideband */
+ if (ice_is_sbq_supported(hw))
+ ice_shutdown_ctrlq(hw, ICE_CTL_Q_SB);
/* Shutdown PF-VF Mailbox */
ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);
}
@@ -704,6 +741,15 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)
if (status)
return status;
+ /* sideband control queue (SBQ) interface is not supported on some
+ * devices. Initialize if supported, else fallback to the admin queue
+ * interface
+ */
+ if (ice_is_sbq_supported(hw)) {
+ status = ice_init_ctrlq(hw, ICE_CTL_Q_SB);
+ if (status)
+ return status;
+ }
/* Init Mailbox queue */
return ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);
}
@@ -739,6 +785,8 @@ static void ice_init_ctrlq_locks(struct ice_ctl_q_info *cq)
enum ice_status ice_create_all_ctrlq(struct ice_hw *hw)
{
ice_init_ctrlq_locks(&hw->adminq);
+ if (ice_is_sbq_supported(hw))
+ ice_init_ctrlq_locks(&hw->sbq);
ice_init_ctrlq_locks(&hw->mailboxq);
return ice_init_all_ctrlq(hw);
@@ -771,6 +819,8 @@ void ice_destroy_all_ctrlq(struct ice_hw *hw)
ice_shutdown_all_ctrlq(hw);
ice_destroy_ctrlq_locks(&hw->adminq);
+ if (ice_is_sbq_supported(hw))
+ ice_destroy_ctrlq_locks(&hw->sbq);
ice_destroy_ctrlq_locks(&hw->mailboxq);
}
@@ -882,7 +932,7 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
* This is the main send command routine for the ATQ. It runs the queue,
* cleans the queue, etc.
*/
-static enum ice_status
+enum ice_status
ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
struct ice_sq_cd *cd)
diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index 0d54e713ca..840fb5e22e 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -10,6 +10,7 @@
/* Maximum buffer lengths for all control queue types */
#define ICE_AQ_MAX_BUF_LEN 4096
#define ICE_MBXQ_MAX_BUF_LEN 4096
+#define ICE_SBQ_MAX_BUF_LEN 512
#define ICE_CTL_Q_DESC(R, i) \
(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
@@ -30,6 +31,7 @@ enum ice_ctl_q {
ICE_CTL_Q_UNKNOWN = 0,
ICE_CTL_Q_ADMIN,
ICE_CTL_Q_MAILBOX,
+ ICE_CTL_Q_SB,
};
/* Control Queue timeout settings - max delay 1s */
diff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h
new file mode 100644
index 0000000000..2bd338c88c
--- /dev/null
+++ b/drivers/net/ice/base/ice_ptp_consts.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2021 Intel Corporation
+ */
+
+#ifndef _ICE_PTP_CONSTS_H_
+#define _ICE_PTP_CONSTS_H_
+
+/* Constant definitions related to the hardware clock used for PTP 1588
+ * features and functionality.
+ */
+/* Constants defined for the PTP 1588 clock hardware. */
+
+/*
+ * struct ice_time_ref_info_e822
+ *
+ * E822 hardware can use different sources as the reference for the PTP
+ * hardware clock. Each clock has different characteristics such as a slightly
+ * different frequency, etc.
+ *
+ * This lookup table defines several constants that depend on the current time
+ * reference. See the struct ice_time_ref_info_e822 for information about the
+ * meaning of each constant.
+ */
+const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {
+ /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ {
+ /* pll_freq */
+ 823437500, /* 823.4375 MHz PLL */
+ /* nominal_incval */
+ 0x136e44fabULL,
+ /* pps_delay */
+ 11,
+ },
+
+ /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ {
+ /* pll_freq */
+ 783360000, /* 783.36 MHz */
+ /* nominal_incval */
+ 0x146cc2177ULL,
+ /* pps_delay */
+ 12,
+ },
+
+ /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ {
+ /* pll_freq */
+ 796875000, /* 796.875 MHz */
+ /* nominal_incval */
+ 0x141414141ULL,
+ /* pps_delay */
+ 12,
+ },
+
+ /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ {
+ /* pll_freq */
+ 816000000, /* 816 MHz */
+ /* nominal_incval */
+ 0x139b9b9baULL,
+ /* pps_delay */
+ 12,
+ },
+
+ /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ {
+ /* pll_freq */
+ 830078125, /* 830.78125 MHz */
+ /* nominal_incval */
+ 0x134679aceULL,
+ /* pps_delay */
+ 11,
+ },
+
+ /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ {
+ /* pll_freq */
+ 783360000, /* 783.36 MHz */
+ /* nominal_incval */
+ 0x146cc2177ULL,
+ /* pps_delay */
+ 12,
+ },
+};
+
+#endif /* _ICE_PTP_CONSTS_H_ */
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
new file mode 100644
index 0000000000..8aefcf93fd
--- /dev/null
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -0,0 +1,2023 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2021 Intel Corporation
+ */
+
+#include "ice_type.h"
+#include "ice_common.h"
+#include "ice_ptp_hw.h"
+#include "ice_ptp_consts.h"
+
+
+/* Low level functions for interacting with and managing the device clock used
+ * for the Precision Time Protocol.
+ *
+ * The ice hardware represents the current time using three registers:
+ *
+ * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
+ * +---------------+ +---------------+ +---------------+
+ * | 32 bits | | 32 bits | | 32 bits |
+ * +---------------+ +---------------+ +---------------+
+ *
+ * The registers are incremented every clock tick using a 40bit increment
+ * value defined over two registers:
+ *
+ * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
+ * +---------------+ +---------------+
+ * | 8 bit s | | 32 bits |
+ * +---------------+ +---------------+
+ *
+ * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
+ * registers every clock source tick. Depending on the specific device
+ * configuration, the clock source frequency could be one of a number of
+ * values.
+ *
+ * For E810 devices, the increment frequency is 812.5 MHz
+ *
+ * For E822 devices the clock can be derived from different sources, and the
+ * increment has an effective frequency of one of the following:
+ * - 823.4375 MHz
+ * - 783.36 MHz
+ * - 796.875 MHz
+ * - 816 MHz
+ * - 830.078125 MHz
+ * - 783.36 MHz
+ *
+ * The hardware captures timestamps in the PHY for incoming packets, and for
+ * outgoing packets on request. To support this, the PHY maintains a timer
+ * that matches the lower 64 bits of the global source timer.
+ *
+ * In order to ensure that the PHY timers and the source timer are equivalent,
+ * shadow registers are used to prepare the desired initial values. A special
+ * sync command is issued to trigger copying from the shadow registers into
+ * the appropriate source and PHY registers simultaneously.
+ *
+ * The driver supports devices which have different PHYs with subtly different
+ * mechanisms to program and control the timers. We divide the devices into
+ * families named after the first major device, E810 and similar devices, and
+ * E822 and similar devices.
+ *
+ * - E822 based devices have additional support for fine grained Vernier
+ * calibration which requires significant setup
+ * - The layout of timestamp data in the PHY register blocks is different
+ * - The way timer synchronization commands are issued is different.
+ *
+ * To support this, very low level functions have an e810 or e822 suffix
+ * indicating what type of device they work on. Higher level abstractions for
+ * tasks that can be done on both devices do not have the suffix and will
+ * correctly look up the appropriate low level function when running.
+ *
+ * Functions which only make sense on a single device family may not have
+ * a suitable generic implementation
+ */
+
+/**
+ * ice_get_ptp_src_clock_index - determine source clock index
+ * @hw: pointer to HW struct
+ *
+ * Determine the source clock index currently in use, based on device
+ * capabilities reported during initialization.
+ */
+u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
+{
+ return hw->func_caps.ts_func_info.tmr_index_assoc;
+}
+
+/**
+ * ice_ptp_read_src_incval - Read source timer increment value
+ * @hw: pointer to HW struct
+ *
+ * Read the increment value of the source timer and return it.
+ */
+u64 ice_ptp_read_src_incval(struct ice_hw *hw)
+{
+ u32 lo, hi;
+ u8 tmr_idx;
+
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+
+ lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
+ hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
+
+ return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
+}
+
+/**
+ * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
+ * @hw: pointer to HW struct
+ *
+ * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
+ * write immediately. This triggers the hardware to begin executing all of the
+ * source and PHY timer commands synchronously.
+ */
+static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
+{
+ wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
+ ice_flush(hw);
+}
+
+/* E822 family functions
+ *
+ * The following functions operate on the E822 family of devices.
+ */
+
+/**
+ * ice_fill_phy_msg_e822 - Fill message data for a PHY register access
+ * @msg: the PHY message buffer to fill in
+ * @port: the port to access
+ * @offset: the register offset
+ */
+static void
+ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)
+{
+ int phy_port, phy, quadtype;
+
+ phy_port = port % ICE_PORTS_PER_PHY;
+ phy = port / ICE_PORTS_PER_PHY;
+ quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE;
+
+ if (quadtype == 0) {
+ msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
+ msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
+ } else {
+ msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
+ msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
+ }
+
+ if (phy == 0)
+ msg->dest_dev = rmn_0;
+ else if (phy == 1)
+ msg->dest_dev = rmn_1;
+ else
+ msg->dest_dev = rmn_2;
+}
+
+/**
+ * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register
+ * @low_addr: the low address to check
+ * @high_addr: on return, contains the high address of the 64bit register
+ *
+ * Checks if the provided low address is one of the known 64bit PHY values
+ * represented as two 32bit registers. If it is, return the appropriate high
+ * register offset to use.
+ */
+static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)
+{
+ switch (low_addr) {
+ case P_REG_PAR_PCS_TX_OFFSET_L:
+ *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
+ return true;
+ case P_REG_PAR_PCS_RX_OFFSET_L:
+ *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
+ return true;
+ case P_REG_PAR_TX_TIME_L:
+ *high_addr = P_REG_PAR_TX_TIME_U;
+ return true;
+ case P_REG_PAR_RX_TIME_L:
+ *high_addr = P_REG_PAR_RX_TIME_U;
+ return true;
+ case P_REG_TOTAL_TX_OFFSET_L:
+ *high_addr = P_REG_TOTAL_TX_OFFSET_U;
+ return true;
+ case P_REG_TOTAL_RX_OFFSET_L:
+ *high_addr = P_REG_TOTAL_RX_OFFSET_U;
+ return true;
+ case P_REG_UIX66_10G_40G_L:
+ *high_addr = P_REG_UIX66_10G_40G_U;
+ return true;
+ case P_REG_UIX66_25G_100G_L:
+ *high_addr = P_REG_UIX66_25G_100G_U;
+ return true;
+ case P_REG_TX_CAPTURE_L:
+ *high_addr = P_REG_TX_CAPTURE_U;
+ return true;
+ case P_REG_RX_CAPTURE_L:
+ *high_addr = P_REG_RX_CAPTURE_U;
+ return true;
+ case P_REG_TX_TIMER_INC_PRE_L:
+ *high_addr = P_REG_TX_TIMER_INC_PRE_U;
+ return true;
+ case P_REG_RX_TIMER_INC_PRE_L:
+ *high_addr = P_REG_RX_TIMER_INC_PRE_U;
+ return true;
+ default:
+ return false;
+ }
+}
+
+/**
+ * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register
+ * @low_addr: the low address to check
+ * @high_addr: on return, contains the high address of the 40bit value
+ *
+ * Checks if the provided low address is one of the known 40bit PHY values
+ * split into two registers with the lower 8 bits in the low register and the
+ * upper 32 bits in the high register. If it is, return the appropriate high
+ * register offset to use.
+ */
+static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)
+{
+ switch (low_addr) {
+ case P_REG_TIMETUS_L:
+ *high_addr = P_REG_TIMETUS_U;
+ return true;
+ case P_REG_PAR_RX_TUS_L:
+ *high_addr = P_REG_PAR_RX_TUS_U;
+ return true;
+ case P_REG_PAR_TX_TUS_L:
+ *high_addr = P_REG_PAR_TX_TUS_U;
+ return true;
+ case P_REG_PCS_RX_TUS_L:
+ *high_addr = P_REG_PCS_RX_TUS_U;
+ return true;
+ case P_REG_PCS_TX_TUS_L:
+ *high_addr = P_REG_PCS_TX_TUS_U;
+ return true;
+ case P_REG_DESK_PAR_RX_TUS_L:
+ *high_addr = P_REG_DESK_PAR_RX_TUS_U;
+ return true;
+ case P_REG_DESK_PAR_TX_TUS_L:
+ *high_addr = P_REG_DESK_PAR_TX_TUS_U;
+ return true;
+ case P_REG_DESK_PCS_RX_TUS_L:
+ *high_addr = P_REG_DESK_PCS_RX_TUS_U;
+ return true;
+ case P_REG_DESK_PCS_TX_TUS_L:
+ *high_addr = P_REG_DESK_PCS_TX_TUS_U;
+ return true;
+ default:
+ return false;
+ }
+}
+
+/**
+ * ice_read_phy_reg_e822_lp - Read a PHY register
+ * @hw: pointer to the HW struct
+ * @port: PHY port to read from
+ * @offset: PHY register offset to read
+ * @val: on return, the contents read from the PHY
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Read a PHY register for the given port over the device sideband queue.
+ */
+static enum ice_status
+ice_read_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
+ bool lock_sbq)
+{
+ struct ice_sbq_msg_input msg = {0};
+ enum ice_status status;
+
+ ice_fill_phy_msg_e822(&msg, port, offset);
+ msg.opcode = ice_sbq_msg_rd;
+
+ status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
+ status);
+ return status;
+ }
+
+ *val = msg.data;
+
+ return ICE_SUCCESS;
+}
+
+enum ice_status
+ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
+{
+ return ice_read_phy_reg_e822_lp(hw, port, offset, val, true);
+}
+
+/**
+ * ice_read_40b_phy_reg_e822 - Read a 40bit value from PHY registers
+ * @hw: pointer to the HW struct
+ * @port: PHY port to read from
+ * @low_addr: offset of the lower register to read from
+ * @val: on return, the contents of the 40bit value from the PHY registers
+ *
+ * Reads the two registers associated with a 40bit value and returns it in the
+ * val pointer. The offset always specifies the lower register offset to use.
+ * The high offset is looked up. This function only operates on registers
+ * known to be split into a lower 8 bit chunk and an upper 32 bit chunk.
+ */
+static enum ice_status
+ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
+{
+ enum ice_status status;
+ u32 low, high;
+ u16 high_addr;
+
+ /* Only operate on registers known to be split into two 32bit
+ * registers.
+ */
+ if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
+ ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
+ low_addr);
+ return ICE_ERR_PARAM;
+ }
+
+ status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
+ low_addr, status);
+ return status;
+ }
+
+ status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
+ high_addr, status);
+ return status;
+ }
+
+ *val = (u64)high << P_REG_40B_HIGH_S | (low & P_REG_40B_LOW_M);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers
+ * @hw: pointer to the HW struct
+ * @port: PHY port to read from
+ * @low_addr: offset of the lower register to read from
+ * @val: on return, the contents of the 64bit value from the PHY registers
+ *
+ * Reads the two registers associated with a 64bit value and returns it in the
+ * val pointer. The offset always specifies the lower register offset to use.
+ * The high offset is looked up. This function only operates on registers
+ * known to be two parts of a 64bit value.
+ */
+static enum ice_status
+ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
+{
+ enum ice_status status;
+ u32 low, high;
+ u16 high_addr;
+
+ /* Only operate on registers known to be split into two 32bit
+ * registers.
+ */
+ if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
+ ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
+ low_addr);
+ return ICE_ERR_PARAM;
+ }
+
+ status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
+ low_addr, status);
+ return status;
+ }
+
+ status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
+ high_addr, status);
+ return status;
+ }
+
+ *val = (u64)high << 32 | low;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_write_phy_reg_e822_lp - Write a PHY register
+ * @hw: pointer to the HW struct
+ * @port: PHY port to write to
+ * @offset: PHY register offset to write
+ * @val: The value to write to the register
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Write a PHY register for the given port over the device sideband queue.
+ */
+static enum ice_status
+ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
+ bool lock_sbq)
+{
+ struct ice_sbq_msg_input msg = {0};
+ enum ice_status status;
+
+ ice_fill_phy_msg_e822(&msg, port, offset);
+ msg.opcode = ice_sbq_msg_wr;
+ msg.data = val;
+
+ status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+enum ice_status
+ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)
+{
+ return ice_write_phy_reg_e822_lp(hw, port, offset, val, true);
+}
+
+/**
+ * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY
+ * @hw: pointer to the HW struct
+ * @port: port to write to
+ * @low_addr: offset of the low register
+ * @val: 40b value to write
+ *
+ * Write the provided 40b value to the two associated registers by splitting
+ * it up into two chunks, the lower 8 bits and the upper 32 bits.
+ */
+static enum ice_status
+ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
+{
+ enum ice_status status;
+ u32 low, high;
+ u16 high_addr;
+
+ /* Only operate on registers known to be split into a lower 8 bit
+ * register and an upper 32 bit register.
+ */
+ if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {
+ ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
+ low_addr);
+ return ICE_ERR_PARAM;
+ }
+
+ low = (u32)(val & P_REG_40B_LOW_M);
+ high = (u32)(val >> P_REG_40B_HIGH_S);
+
+ status = ice_write_phy_reg_e822(hw, port, low_addr, low);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
+ low_addr, status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e822(hw, port, high_addr, high);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
+ high_addr, status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers
+ * @hw: pointer to the HW struct
+ * @port: PHY port to read from
+ * @low_addr: offset of the lower register to read from
+ * @val: the contents of the 64bit value to write to PHY
+ *
+ * Write the 64bit value to the two associated 32bit PHY registers. The offset
+ * is always specified as the lower register, and the high address is looked
+ * up. This function only operates on registers known to be two parts of
+ * a 64bit value.
+ */
+static enum ice_status
+ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
+{
+ enum ice_status status;
+ u32 low, high;
+ u16 high_addr;
+
+ /* Only operate on registers known to be split into two 32bit
+ * registers.
+ */
+ if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {
+ ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
+ low_addr);
+ return ICE_ERR_PARAM;
+ }
+
+ low = ICE_LO_DWORD(val);
+ high = ICE_HI_DWORD(val);
+
+ status = ice_write_phy_reg_e822(hw, port, low_addr, low);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
+ low_addr, status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e822(hw, port, high_addr, high);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
+ high_addr, status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_fill_quad_msg_e822 - Fill message data for quad register access
+ * @msg: the PHY message buffer to fill in
+ * @quad: the quad to access
+ * @offset: the register offset
+ *
+ * Fill a message buffer for accessing a register in a quad shared between
+ * multiple PHYs.
+ */
+static void
+ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)
+{
+ u32 addr;
+
+ msg->dest_dev = rmn_0;
+
+ if ((quad % ICE_NUM_QUAD_TYPE) == 0)
+ addr = Q_0_BASE + offset;
+ else
+ addr = Q_1_BASE + offset;
+
+ msg->msg_addr_low = ICE_LO_WORD(addr);
+ msg->msg_addr_high = ICE_HI_WORD(addr);
+}
+
+/**
+ * ice_read_quad_reg_e822_lp - Read a PHY quad register
+ * @hw: pointer to the HW struct
+ * @quad: quad to read from
+ * @offset: quad register offset to read
+ * @val: on return, the contents read from the quad
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Read a quad register over the device sideband queue. Quad registers are
+ * shared between multiple PHYs.
+ */
+static enum ice_status
+ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val,
+ bool lock_sbq)
+{
+ struct ice_sbq_msg_input msg = {0};
+ enum ice_status status;
+
+ if (quad >= ICE_MAX_QUAD)
+ return ICE_ERR_PARAM;
+
+ ice_fill_quad_msg_e822(&msg, quad, offset);
+ msg.opcode = ice_sbq_msg_rd;
+
+ status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
+ status);
+ return status;
+ }
+
+ *val = msg.data;
+
+ return ICE_SUCCESS;
+}
+
+enum ice_status
+ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
+{
+ return ice_read_quad_reg_e822_lp(hw, quad, offset, val, true);
+}
+
+/**
+ * ice_write_quad_reg_e822_lp - Write a PHY quad register
+ * @hw: pointer to the HW struct
+ * @quad: quad to write to
+ * @offset: quad register offset to write
+ * @val: The value to write to the register
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Write a quad register over the device sideband queue. Quad registers are
+ * shared between multiple PHYs.
+ */
+static enum ice_status
+ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,
+ bool lock_sbq)
+{
+ struct ice_sbq_msg_input msg = {0};
+ enum ice_status status;
+
+ if (quad >= ICE_MAX_QUAD)
+ return ICE_ERR_PARAM;
+
+ ice_fill_quad_msg_e822(&msg, quad, offset);
+ msg.opcode = ice_sbq_msg_wr;
+ msg.data = val;
+
+ status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+enum ice_status
+ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
+{
+ return ice_write_quad_reg_e822_lp(hw, quad, offset, val, true);
+}
+
+/**
+ * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block
+ * @hw: pointer to the HW struct
+ * @quad: the quad to read from
+ * @idx: the timestamp index to read
+ * @tstamp: on return, the 40bit timestamp value
+ *
+ * Read a 40bit timestamp value out of the two associated registers in the
+ * quad memory block that is shared between the internal PHYs of the E822
+ * family of devices.
+ */
+static enum ice_status
+ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
+{
+ enum ice_status status;
+ u16 lo_addr, hi_addr;
+ u32 lo, hi;
+
+ lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
+ hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
+
+ status = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ /* For E822 based internal PHYs, the timestamp is reported with the
+ * lower 8 bits in the low register, and the upper 32 bits in the high
+ * register.
+ */
+ *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block
+ * @hw: pointer to the HW struct
+ * @quad: the quad to read from
+ * @idx: the timestamp index to reset
+ *
+ * Clear a timestamp, resetting its valid bit, from the PHY quad block that is
+ * shared between the internal PHYs on the E822 devices.
+ */
+static enum ice_status
+ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
+{
+ enum ice_status status;
+ u16 lo_addr, hi_addr;
+
+ lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
+ hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
+
+ status = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time
+ * @hw: pointer to the HW struct
+ * @time: Time to initialize the PHY port clocks to
+ *
+ * Program the PHY port registers with a new initial time value. The port
+ * clock will be initialized once the driver issues an INIT_TIME sync
+ * command. The time value is the upper 32 bits of the PHY timer, usually in
+ * units of nominal nanoseconds.
+ */
+static enum ice_status
+ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)
+{
+ enum ice_status status;
+ u64 phy_time;
+ u8 port;
+
+ /* The time represents the upper 32 bits of the PHY timer, so we need
+ * to shift to account for this when programming.
+ */
+ phy_time = (u64)time << 32;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+
+ /* Tx case */
+ status = ice_write_64b_phy_reg_e822(hw, port,
+ P_REG_TX_TIMER_INC_PRE_L,
+ phy_time);
+ if (status)
+ goto exit_err;
+
+ /* Rx case */
+ status = ice_write_64b_phy_reg_e822(hw, port,
+ P_REG_RX_TIMER_INC_PRE_L,
+ phy_time);
+ if (status)
+ goto exit_err;
+ }
+
+ return ICE_SUCCESS;
+
+exit_err:
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
+ port, status);
+
+ return status;
+}
+
+/**
+ * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust
+ * @hw: pointer to HW struct
+ * @port: Port number to be programmed
+ * @time: time in cycles to adjust the port Tx and Rx clocks
+ * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
+ * sq_lock has already been locked at a higher level
+ *
+ * Program the port for an atomic adjustment by writing the Tx and Rx timer
+ * registers. The atomic adjustment won't be completed until the driver issues
+ * an ADJ_TIME command.
+ *
+ * Note that time is not in units of nanoseconds. It is in clock time
+ * including the lower sub-nanosecond portion of the port timer.
+ *
+ * Negative adjustments are supported using 2s complement arithmetic.
+ */
+enum ice_status
+ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,
+ bool lock_sbq)
+{
+ enum ice_status status;
+ u32 l_time, u_time;
+
+ l_time = ICE_LO_DWORD(time);
+ u_time = ICE_HI_DWORD(time);
+
+ /* Tx case */
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_L,
+ l_time, lock_sbq);
+ if (status)
+ goto exit_err;
+
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_U,
+ u_time, lock_sbq);
+ if (status)
+ goto exit_err;
+
+ /* Rx case */
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_L,
+ l_time, lock_sbq);
+ if (status)
+ goto exit_err;
+
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_U,
+ u_time, lock_sbq);
+ if (status)
+ goto exit_err;
+
+ return ICE_SUCCESS;
+
+exit_err:
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
+ port, status);
+ return status;
+}
+
+/**
+ * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment
+ * @hw: pointer to HW struct
+ * @adj: adjustment in nanoseconds
+ * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
+ * sq_lock has already been locked at a higher level
+ *
+ * Prepare the PHY ports for an atomic time adjustment by programming the PHY
+ * Tx and Rx port registers. The actual adjustment is completed by issuing an
+ * ADJ_TIME or ADJ_TIME_AT_TIME sync command.
+ */
+static enum ice_status
+ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)
+{
+ s64 cycles;
+ u8 port;
+
+ /* The port clock supports adjustment of the sub-nanosecond portion of
+ * the clock. We shift the provided adjustment in nanoseconds to
+ * calculate the appropriate adjustment to program into the PHY ports.
+ */
+ if (adj > 0)
+ cycles = (s64)adj << 32;
+ else
+ cycles = -(((s64)-adj) << 32);
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ enum ice_status status;
+
+ status = ice_ptp_prep_port_adj_e822(hw, port, cycles,
+ lock_sbq);
+ if (status)
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment
+ * @hw: pointer to HW struct
+ * @incval: new increment value to prepare
+ *
+ * Prepare each of the PHY ports for a new increment value by programming the
+ * port's TIMETUS registers. The new increment value will be updated after
+ * issuing an INIT_INCVAL command.
+ */
+static enum ice_status
+ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)
+{
+ enum ice_status status;
+ u8 port;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,
+ incval);
+ if (status)
+ goto exit_err;
+ }
+
+ return ICE_SUCCESS;
+
+exit_err:
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
+ port, status);
+
+ return status;
+}
+
+/**
+ * ice_ptp_read_phy_incval_e822 - Read a PHY port's current incval
+ * @hw: pointer to the HW struct
+ * @port: the port to read
+ * @incval: on return, the time_clk_cyc incval for this port
+ *
+ * Read the time_clk_cyc increment value for a given PHY port.
+ */
+enum ice_status
+ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval)
+{
+ enum ice_status status;
+
+ status = ice_read_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
+ status);
+ return status;
+ }
+
+ ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
+ (unsigned long long)*incval);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_prep_phy_adj_target_e822 - Prepare PHY for adjust at target time
+ * @hw: pointer to HW struct
+ * @target_time: target time to program
+ *
+ * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the
+ * ADJ_TIME_AT_TIME command. This should be used in conjunction with
+ * ice_ptp_prep_phy_adj_e822 to program an atomic adjustment that is
+ * delayed until a specified target time.
+ *
+ * Note that a target time adjustment is not currently supported on E810
+ * devices.
+ */
+static enum ice_status
+ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32 target_time)
+{
+ enum ice_status status;
+ u8 port;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+
+ /* Tx case */
+ /* No sub-nanoseconds data */
+ status = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_TX_TIMER_CNT_ADJ_L,
+ 0, true);
+ if (status)
+ goto exit_err;
+
+ status = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_TX_TIMER_CNT_ADJ_U,
+ target_time, true);
+ if (status)
+ goto exit_err;
+
+ /* Rx case */
+ /* No sub-nanoseconds data */
+ status = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_RX_TIMER_CNT_ADJ_L,
+ 0, true);
+ if (status)
+ goto exit_err;
+
+ status = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_RX_TIMER_CNT_ADJ_U,
+ target_time, true);
+ if (status)
+ goto exit_err;
+ }
+
+ return ICE_SUCCESS;
+
+exit_err:
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
+ port, status);
+
+ return status;
+}
+
+/**
+ * ice_ptp_read_port_capture - Read a port's local time capture
+ * @hw: pointer to HW struct
+ * @port: Port number to read
+ * @tx_ts: on return, the Tx port time capture
+ * @rx_ts: on return, the Rx port time capture
+ *
+ * Read the port's Tx and Rx local time capture values.
+ *
+ * Note this has no equivalent for the E810 devices.
+ */
+enum ice_status
+ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
+{
+ enum ice_status status;
+
+ /* Tx case */
+ status = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
+ status);
+ return status;
+ }
+
+ ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
+ (unsigned long long)*tx_ts);
+
+ /* Rx case */
+ status = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
+ status);
+ return status;
+ }
+
+ ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
+ (unsigned long long)*rx_ts);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command
+ * @hw: pointer to HW struct
+ * @port: Port to which cmd has to be sent
+ * @cmd: Command to be sent to the port
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare the requested port for an upcoming timer sync command.
+ *
+ * Note there is no equivalent of this operation on E810, as that device
+ * always handles all external PHYs internally.
+ */
+enum ice_status
+ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
+ bool lock_sbq)
+{
+ enum ice_status status;
+ u32 cmd_val, val;
+ u8 tmr_idx;
+
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+ cmd_val = tmr_idx << SEL_PHY_SRC;
+ switch (cmd) {
+ case INIT_TIME:
+ cmd_val |= PHY_CMD_INIT_TIME;
+ break;
+ case INIT_INCVAL:
+ cmd_val |= PHY_CMD_INIT_INCVAL;
+ break;
+ case ADJ_TIME:
+ cmd_val |= PHY_CMD_ADJ_TIME;
+ break;
+ case ADJ_TIME_AT_TIME:
+ cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
+ break;
+ case READ_TIME:
+ cmd_val |= PHY_CMD_READ_TIME;
+ break;
+ default:
+ ice_warn(hw, "Unknown timer command %u\n", cmd);
+ return ICE_ERR_PARAM;
+ }
+
+ /* Tx case */
+ /* Read, modify, write */
+ status = ice_read_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, &val,
+ lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n",
+ status);
+ return status;
+ }
+
+ /* Modify necessary bits only and perform write */
+ val &= ~TS_CMD_MASK;
+ val |= cmd_val;
+
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, val,
+ lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
+ status);
+ return status;
+ }
+
+ /* Rx case */
+ /* Read, modify, write */
+ status = ice_read_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, &val,
+ lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n",
+ status);
+ return status;
+ }
+
+ /* Modify necessary bits only and perform write */
+ val &= ~TS_CMD_MASK;
+ val |= cmd_val;
+
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, val,
+ lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
+ * @hw: pointer to the HW struct
+ * @cmd: timer command to prepare
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare all ports connected to this device for an upcoming timer sync
+ * command.
+ */
+static enum ice_status
+ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+ bool lock_sbq)
+{
+ u8 port;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ enum ice_status status;
+
+ status = ice_ptp_one_port_cmd(hw, port, cmd, lock_sbq);
+ if (status)
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/* E822 Vernier calibration functions
+ *
+ * The following functions are used as part of the vernier calibration of
+ * a port. This calibration increases the precision of the timestamps on the
+ * port.
+ */
+
+/**
+ * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
+ * @hw: pointer to the HW struct
+ *
+ * Set the window length used for the vernier port calibration process.
+ */
+enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)
+{
+ u8 port;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ enum ice_status status;
+
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
+ PTP_VERNIER_WL, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode
+ * @hw: pointer to HW struct
+ * @port: the port to read from
+ * @link_out: if non-NULL, holds link speed on success
+ * @fec_out: if non-NULL, holds FEC algorithm on success
+ *
+ * Read the serdes data for the PHY port and extract the link speed and FEC
+ * algorithm.
+ */
+enum ice_status
+ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
+ enum ice_ptp_link_spd *link_out,
+ enum ice_ptp_fec_mode *fec_out)
+{
+ enum ice_ptp_link_spd link;
+ enum ice_ptp_fec_mode fec;
+ enum ice_status status;
+ u32 serdes;
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
+ return status;
+ }
+
+ /* Determine the FEC algorithm */
+ fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
+
+ serdes &= P_REG_LINK_SPEED_SERDES_M;
+
+ /* Determine the link speed */
+ if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
+ switch (serdes) {
+ case ICE_PTP_SERDES_25G:
+ link = ICE_PTP_LNK_SPD_25G_RS;
+ break;
+ case ICE_PTP_SERDES_50G:
+ link = ICE_PTP_LNK_SPD_50G_RS;
+ break;
+ case ICE_PTP_SERDES_100G:
+ link = ICE_PTP_LNK_SPD_100G_RS;
+ break;
+ default:
+ return ICE_ERR_OUT_OF_RANGE;
+ }
+ } else {
+ switch (serdes) {
+ case ICE_PTP_SERDES_1G:
+ link = ICE_PTP_LNK_SPD_1G;
+ break;
+ case ICE_PTP_SERDES_10G:
+ link = ICE_PTP_LNK_SPD_10G;
+ break;
+ case ICE_PTP_SERDES_25G:
+ link = ICE_PTP_LNK_SPD_25G;
+ break;
+ case ICE_PTP_SERDES_40G:
+ link = ICE_PTP_LNK_SPD_40G;
+ break;
+ case ICE_PTP_SERDES_50G:
+ link = ICE_PTP_LNK_SPD_50G;
+ break;
+ default:
+ return ICE_ERR_OUT_OF_RANGE;
+ }
+ }
+
+ if (link_out)
+ *link_out = link;
+ if (fec_out)
+ *fec_out = fec;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp
+ * @hw: pointer to HW struct
+ * @port: to configure the quad for
+ */
+void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_status status;
+ u32 val;
+ u8 quad;
+
+ status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, status %d\n",
+ status);
+ return;
+ }
+
+ quad = port / ICE_PORTS_PER_QUAD;
+
+ status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, status %d\n",
+ status);
+ return;
+ }
+
+ if (link_spd >= ICE_PTP_LNK_SPD_40G)
+ val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
+ else
+ val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
+
+ status = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, status %d\n",
+ status);
+ return;
+ }
+}
+
+/* E810 functions
+ *
+ * The following functions operate on the E810 series devices which use
+ * a separate external PHY.
+ */
+
+/**
+ * ice_read_phy_reg_e810_lp - Read register from external PHY on E810
+ * @hw: pointer to the HW struct
+ * @addr: the address to read from
+ * @val: On return, the value read from the PHY
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Read a register from the external PHY on the E810 device.
+ */
+static enum ice_status
+ice_read_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 *val, bool lock_sbq)
+{
+ struct ice_sbq_msg_input msg = {0};
+ enum ice_status status;
+
+ msg.msg_addr_low = ICE_LO_WORD(addr);
+ msg.msg_addr_high = ICE_HI_WORD(addr);
+ msg.opcode = ice_sbq_msg_rd;
+ msg.dest_dev = rmn_0;
+
+ status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
+ status);
+ return status;
+ }
+
+ *val = msg.data;
+
+ return ICE_SUCCESS;
+}
+
+static enum ice_status
+ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
+{
+ return ice_read_phy_reg_e810_lp(hw, addr, val, true);
+}
+
+/**
+ * ice_write_phy_reg_e810_lp - Write register on external PHY on E810
+ * @hw: pointer to the HW struct
+ * @addr: the address to writem to
+ * @val: the value to write to the PHY
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Write a value to a register of the external PHY on the E810 device.
+ */
+static enum ice_status
+ice_write_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 val, bool lock_sbq)
+{
+ struct ice_sbq_msg_input msg = {0};
+ enum ice_status status;
+
+ msg.msg_addr_low = ICE_LO_WORD(addr);
+ msg.msg_addr_high = ICE_HI_WORD(addr);
+ msg.opcode = ice_sbq_msg_wr;
+ msg.dest_dev = rmn_0;
+ msg.data = val;
+
+ status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+static enum ice_status
+ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
+{
+ return ice_write_phy_reg_e810_lp(hw, addr, val, true);
+}
+
+/**
+ * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
+ * @hw: pointer to the HW struct
+ * @lport: the lport to read from
+ * @idx: the timestamp index to read
+ * @tstamp: on return, the 40bit timestamp value
+ *
+ * Read a 40bit timestamp value out of the timestamp block of the external PHY
+ * on the E810 device.
+ */
+static enum ice_status
+ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
+{
+ enum ice_status status;
+ u32 lo_addr, hi_addr, lo, hi;
+
+ lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
+ hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
+
+ status = ice_read_phy_reg_e810(hw, lo_addr, &lo);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_read_phy_reg_e810(hw, hi_addr, &hi);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ /* For E810 devices, the timestamp is reported with the lower 32 bits
+ * in the low register, and the upper 8 bits in the high register.
+ */
+ *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
+ * @hw: pointer to the HW struct
+ * @lport: the lport to read from
+ * @idx: the timestamp index to reset
+ *
+ * Clear a timestamp, resetting its valid bit, from the timestamp block of the
+ * external PHY on the E810 device.
+ */
+static enum ice_status
+ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
+{
+ enum ice_status status;
+ u32 lo_addr, hi_addr;
+
+ lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
+ hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
+
+ status = ice_write_phy_reg_e810(hw, lo_addr, 0);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e810(hw, hi_addr, 0);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY
+ * @hw: pointer to HW struct
+ *
+ * Enable the timesync PTP functionality for the external PHY connected to
+ * this function.
+ *
+ * Note there is no equivalent function needed on E822 based devices.
+ */
+enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
+ GLTSYN_ENA_TSYN_ENA_M);
+ if (status)
+ ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
+ status);
+
+ return status;
+}
+
+/**
+ * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
+ * @hw: Board private structure
+ * @time: Time to initialize the PHY port clock to
+ *
+ * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
+ * initial clock time. The time will not actually be programmed until the
+ * driver issues an INIT_TIME command.
+ *
+ * The time value is the upper 32 bits of the PHY timer, usually in units of
+ * nominal nanoseconds.
+ */
+static enum ice_status ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
+ * @hw: pointer to HW struct
+ * @adj: adjustment value to program
+ * @lock_sbq: true if the sideband queue luck must be acquired
+ *
+ * Prepare the PHY port for an atomic adjustment by programming the PHY
+ * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
+ * is completed by issuing an ADJ_TIME sync command.
+ *
+ * The adjustment value only contains the portion used for the upper 32bits of
+ * the PHY timer, usually in units of nominal nanoseconds. Negative
+ * adjustments are supported using 2s complement arithmetic.
+ */
+static enum ice_status
+ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj, bool lock_sbq)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+
+ /* Adjustments are represented as signed 2's complement values in
+ * nanoseconds. Sub-nanosecond adjustment is not supported.
+ */
+ status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_L(tmr_idx),
+ 0, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_H(tmr_idx),
+ adj, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
+ * @hw: pointer to HW struct
+ * @incval: The new 40bit increment value to prepare
+ *
+ * Prepare the PHY port for a new increment value by programming the PHY
+ * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
+ * completed by issuing an INIT_INCVAL command.
+ */
+static enum ice_status
+ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
+{
+ enum ice_status status;
+ u32 high, low;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+ low = ICE_LO_DWORD(incval);
+ high = ICE_HI_DWORD(incval);
+
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_prep_phy_adj_target_e810 - Prepare PHY port with adjust target
+ * @hw: Board private structure
+ * @target_time: Time to trigger the clock adjustment at
+ *
+ * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation for
+ * a target time adjust, which will trigger an adjustment of the clock in the
+ * future. The actual adjustment will occur the next time the PHY port timer
+ * crosses over the provided value after the driver issues an ADJ_TIME_AT_TIME
+ * command.
+ *
+ * The time value is the upper 32 bits of the PHY timer, usually in units of
+ * nominal nanoseconds.
+ */
+static enum ice_status
+ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_0, status %d\n",
+ status);
+ return status;
+ }
+
+ status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx),
+ target_time);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_L, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
+ * @hw: pointer to HW struct
+ * @cmd: Command to be sent to the port
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare the external PHYs connected to this device for a timer sync
+ * command.
+ */
+static enum ice_status
+ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+ bool lock_sbq)
+{
+ enum ice_status status;
+ u32 cmd_val, val;
+
+ switch (cmd) {
+ case INIT_TIME:
+ cmd_val = GLTSYN_CMD_INIT_TIME;
+ break;
+ case INIT_INCVAL:
+ cmd_val = GLTSYN_CMD_INIT_INCVAL;
+ break;
+ case ADJ_TIME:
+ cmd_val = GLTSYN_CMD_ADJ_TIME;
+ break;
+ case ADJ_TIME_AT_TIME:
+ cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
+ break;
+ case READ_TIME:
+ cmd_val = GLTSYN_CMD_READ_TIME;
+ break;
+ default:
+ ice_warn(hw, "Unknown timer command %u\n", cmd);
+ return ICE_ERR_PARAM;
+ }
+
+ /* Read, modify, write */
+ status = ice_read_phy_reg_e810_lp(hw, ETH_GLTSYN_CMD, &val, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, status %d\n",
+ status);
+ return status;
+ }
+
+ /* Modify necessary bits only and perform write */
+ val &= ~TS_CMD_MASK_E810;
+ val |= cmd_val;
+
+ status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_CMD, val, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/* Device agnostic functions
+ *
+ * The following functions implement shared behavior common to both E822 and
+ * E810 devices, possibly calling a device specific implementation where
+ * necessary.
+ */
+
+/**
+ * ice_ptp_lock - Acquire PTP global semaphore register lock
+ * @hw: pointer to the HW struct
+ *
+ * Acquire the global PTP hardware semaphore lock. Returns true if the lock
+ * was acquired, false otherwise.
+ *
+ * The PFTSYN_SEM register sets the busy bit on read, returning the previous
+ * value. If software sees the busy bit cleared, this means that this function
+ * acquired the lock (and the busy bit is now set). If software sees the busy
+ * bit set, it means that another function acquired the lock.
+ *
+ * Software must clear the busy bit with a write to release the lock for other
+ * functions when done.
+ */
+bool ice_ptp_lock(struct ice_hw *hw)
+{
+ u32 hw_lock;
+ int i;
+
+#define MAX_TRIES 5
+
+ for (i = 0; i < MAX_TRIES; i++) {
+ hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
+ hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
+ if (hw_lock) {
+ /* Somebody is holding the lock */
+ ice_msec_delay(10, true);
+ continue;
+ } else {
+ break;
+ }
+ }
+
+ return !hw_lock;
+}
+
+/**
+ * ice_ptp_unlock - Release PTP global semaphore register lock
+ * @hw: pointer to the HW struct
+ *
+ * Release the global PTP hardware semaphore lock. This is done by writing to
+ * the PFTSYN_SEM register.
+ */
+void ice_ptp_unlock(struct ice_hw *hw)
+{
+ wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
+}
+
+/**
+ * ice_ptp_src_cmd - Prepare source timer for a timer command
+ * @hw: pointer to HW structure
+ * @cmd: Timer command
+ *
+ * Prepare the source timer for an upcoming timer sync command.
+ */
+void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
+{
+ u32 cmd_val;
+ u8 tmr_idx;
+
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+ cmd_val = tmr_idx << SEL_CPK_SRC;
+
+ switch (cmd) {
+ case INIT_TIME:
+ cmd_val |= GLTSYN_CMD_INIT_TIME;
+ break;
+ case INIT_INCVAL:
+ cmd_val |= GLTSYN_CMD_INIT_INCVAL;
+ break;
+ case ADJ_TIME:
+ cmd_val |= GLTSYN_CMD_ADJ_TIME;
+ break;
+ case ADJ_TIME_AT_TIME:
+ cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
+ break;
+ case READ_TIME:
+ cmd_val |= GLTSYN_CMD_READ_TIME;
+ break;
+ default:
+ ice_warn(hw, "Unknown timer command %u\n", cmd);
+ return;
+ }
+
+ wr32(hw, GLTSYN_CMD, cmd_val);
+}
+
+/**
+ * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
+ * @hw: pointer to HW struct
+ * @cmd: the command to issue
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare the source timer and PHY timers and then trigger the requested
+ * command. This causes the shadow registers previously written in preparation
+ * for the command to be synchronously applied to both the source and PHY
+ * timers.
+ */
+static enum ice_status
+ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
+{
+ enum ice_status status;
+
+ /* First, prepare the source timer */
+ ice_ptp_src_cmd(hw, cmd);
+
+ /* Next, prepare the ports */
+ if (ice_is_e810(hw))
+ status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
+ else
+ status = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n",
+ cmd, status);
+ return status;
+ }
+
+ /* Write the sync command register to drive both source and PHY timer
+ * commands synchronously
+ */
+ ice_ptp_exec_tmr_cmd(hw);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_init_time - Initialize device time to provided value
+ * @hw: pointer to HW struct
+ * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
+ *
+ * Initialize the device to the specified time provided. This requires a three
+ * step process:
+ *
+ * 1) write the new init time to the source timer shadow registers
+ * 2) write the new init time to the phy timer shadow registers
+ * 3) issue an init_time timer command to synchronously switch both the source
+ * and port timers to the new init time value at the next clock cycle.
+ */
+enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+
+ /* Source timers */
+ wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));
+ wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));
+ wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
+
+ /* PHY Clks */
+ /* Fill Rx and Tx ports and send msg to PHY */
+ if (ice_is_e810(hw))
+ status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
+ else
+ status = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
+ if (status)
+ return status;
+
+ return ice_ptp_tmr_cmd(hw, INIT_TIME, true);
+}
+
+/**
+ * ice_ptp_write_incval - Program PHC with new increment value
+ * @hw: pointer to HW struct
+ * @incval: Source timer increment value per clock cycle
+ *
+ * Program the PHC with a new increment value. This requires a three-step
+ * process:
+ *
+ * 1) Write the increment value to the source timer shadow registers
+ * 2) Write the increment value to the PHY timer shadow registers
+ * 3) Issue an INIT_INCVAL timer command to synchronously switch both the
+ * source and port timers to the new increment value at the next clock
+ * cycle.
+ */
+enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+
+ /* Shadow Adjust */
+ wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));
+ wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
+
+ if (ice_is_e810(hw))
+ status = ice_ptp_prep_phy_incval_e810(hw, incval);
+ else
+ status = ice_ptp_prep_phy_incval_e822(hw, incval);
+ if (status)
+ return status;
+
+ return ice_ptp_tmr_cmd(hw, INIT_INCVAL, true);
+}
+
+/**
+ * ice_ptp_write_incval_locked - Program new incval while holding semaphore
+ * @hw: pointer to HW struct
+ * @incval: Source timer increment value per clock cycle
+ *
+ * Program a new PHC incval while holding the PTP semaphore.
+ */
+enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
+{
+ enum ice_status status;
+
+ if (!ice_ptp_lock(hw))
+ return ICE_ERR_NOT_READY;
+
+ status = ice_ptp_write_incval(hw, incval);
+
+ ice_ptp_unlock(hw);
+
+ return status;
+}
+
+/**
+ * ice_ptp_adj_clock - Adjust PHC clock time atomically
+ * @hw: pointer to HW struct
+ * @adj: Adjustment in nanoseconds
+ * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
+ * sq_lock has already been locked at a higher level
+ *
+ * Perform an atomic adjustment of the PHC time by the specified number of
+ * nanoseconds. This requires a three-step process:
+ *
+ * 1) Write the adjustment to the source timer shadow registers
+ * 2) Write the adjustment to the PHY timer shadow registers
+ * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to
+ * both the source and port timers at the next clock cycle.
+ */
+enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
+{
+ enum ice_status status;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+
+ /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
+ * For an ADJ_TIME command, this set of registers represents the value
+ * to add to the clock time. It supports subtraction by interpreting
+ * the value as a 2's complement integer.
+ */
+ wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
+ wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
+
+ if (ice_is_e810(hw))
+ status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
+ else
+ status = ice_ptp_prep_phy_adj_e822(hw, adj, lock_sbq);
+ if (status)
+ return status;
+
+ return ice_ptp_tmr_cmd(hw, ADJ_TIME, lock_sbq);
+}
+
+/**
+ * ice_ptp_adj_clock_at_time - Adjust PHC atomically at specified time
+ * @hw: pointer to HW struct
+ * @at_time: Time in nanoseconds at which to perform the adjustment
+ * @adj: Adjustment in nanoseconds
+ *
+ * Perform an atomic adjustment to the PHC clock at the specified time. This
+ * requires a five-step process:
+ *
+ * 1) Write the adjustment to the source timer shadow adjust registers
+ * 2) Write the target time to the source timer shadow time registers
+ * 3) Write the adjustment to the PHY timers shadow adjust registers
+ * 4) Write the target time to the PHY timers shadow adjust registers
+ * 5) Issue an ADJ_TIME_AT_TIME command to initiate the atomic adjustment.
+ */
+enum ice_status
+ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
+{
+ enum ice_status status;
+ u32 time_lo, time_hi;
+ u8 tmr_idx;
+
+ tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+ time_lo = ICE_LO_DWORD(at_time);
+ time_hi = ICE_HI_DWORD(at_time);
+
+ /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
+ * For an ADJ_TIME_AT_TIME command, this set of registers represents
+ * the value to add to the clock time. It supports subtraction by
+ * interpreting the value as a 2's complement integer.
+ */
+ wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
+ wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
+
+ /* Write the target time to trigger the adjustment for source clock */
+ wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
+ wr32(hw, GLTSYN_SHTIME_L(tmr_idx), time_lo);
+ wr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi);
+
+ /* Prepare PHY port adjustments */
+ if (ice_is_e810(hw))
+ status = ice_ptp_prep_phy_adj_e810(hw, adj, true);
+ else
+ status = ice_ptp_prep_phy_adj_e822(hw, adj, true);
+ if (status)
+ return status;
+
+ /* Set target time for each PHY port */
+ if (ice_is_e810(hw))
+ status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
+ else
+ status = ice_ptp_prep_phy_adj_target_e822(hw, time_lo);
+ if (status)
+ return status;
+
+ return ice_ptp_tmr_cmd(hw, ADJ_TIME_AT_TIME, true);
+}
+
+/**
+ * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
+ * @hw: pointer to the HW struct
+ * @block: the block to read from
+ * @idx: the timestamp index to read
+ * @tstamp: on return, the 40bit timestamp value
+ *
+ * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
+ * the block is the quad to read from. For E810 devices, the block is the
+ * logical port to read from.
+ */
+enum ice_status
+ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
+{
+ if (ice_is_e810(hw))
+ return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
+ else
+ return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
+}
+
+/**
+ * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
+ * @hw: pointer to the HW struct
+ * @block: the block to read from
+ * @idx: the timestamp index to reset
+ *
+ * Clear a timestamp, resetting its valid bit, from the timestamp block. For
+ * E822 devices, the block is the quad to clear from. For E810 devices, the
+ * block is the logical port to clear from.
+ */
+enum ice_status
+ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
+{
+ if (ice_is_e810(hw))
+ return ice_clear_phy_tstamp_e810(hw, block, idx);
+ else
+ return ice_clear_phy_tstamp_e822(hw, block, idx);
+}
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
new file mode 100644
index 0000000000..8cbe81792d
--- /dev/null
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -0,0 +1,376 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2021 Intel Corporation
+ */
+
+#ifndef _ICE_PTP_HW_H_
+#define _ICE_PTP_HW_H_
+
+enum ice_ptp_tmr_cmd {
+ INIT_TIME,
+ INIT_INCVAL,
+ ADJ_TIME,
+ ADJ_TIME_AT_TIME,
+ READ_TIME
+};
+
+enum ice_ptp_serdes {
+ ICE_PTP_SERDES_1G,
+ ICE_PTP_SERDES_10G,
+ ICE_PTP_SERDES_25G,
+ ICE_PTP_SERDES_40G,
+ ICE_PTP_SERDES_50G,
+ ICE_PTP_SERDES_100G
+};
+
+enum ice_ptp_link_spd {
+ ICE_PTP_LNK_SPD_1G,
+ ICE_PTP_LNK_SPD_10G,
+ ICE_PTP_LNK_SPD_25G,
+ ICE_PTP_LNK_SPD_25G_RS,
+ ICE_PTP_LNK_SPD_40G,
+ ICE_PTP_LNK_SPD_50G,
+ ICE_PTP_LNK_SPD_50G_RS,
+ ICE_PTP_LNK_SPD_100G_RS,
+ NUM_ICE_PTP_LNK_SPD /* Must be last */
+};
+
+enum ice_ptp_fec_mode {
+ ICE_PTP_FEC_MODE_NONE,
+ ICE_PTP_FEC_MODE_CLAUSE74,
+ ICE_PTP_FEC_MODE_RS_FEC
+};
+
+/**
+ * struct ice_time_ref_info_e822
+ * @pll_freq: Frequency of PLL that drives timer ticks in Hz
+ * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
+ * @pps_delay: propagation delay of the PPS output signal
+ *
+ * Characteristic information for the various TIME_REF sources possible in the
+ * E822 devices
+ */
+struct ice_time_ref_info_e822 {
+ u64 pll_freq;
+ u64 nominal_incval;
+ u8 pps_delay;
+};
+
+/* Table of constants related to possible TIME_REF sources */
+extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
+
+/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
+ * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
+ */
+#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
+
+/* Device agnostic functions */
+u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
+u64 ice_ptp_read_src_incval(struct ice_hw *hw);
+bool ice_ptp_lock(struct ice_hw *hw);
+void ice_ptp_unlock(struct ice_hw *hw);
+void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
+enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time);
+enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
+enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
+enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq);
+enum ice_status
+ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj);
+enum ice_status
+ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
+enum ice_status
+ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
+
+/* E822 family functions */
+enum ice_status
+ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
+enum ice_status
+ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val);
+enum ice_status
+ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
+enum ice_status
+ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
+enum ice_status
+ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,
+ bool lock_sbq);
+enum ice_status
+ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval);
+enum ice_status
+ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);
+enum ice_status
+ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
+ bool lock_sbq);
+
+static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
+{
+ return e822_time_ref[time_ref].pll_freq;
+}
+
+static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
+{
+ return e822_time_ref[time_ref].nominal_incval;
+}
+
+static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
+{
+ return e822_time_ref[time_ref].pps_delay;
+}
+
+/* E822 Vernier calibration functions */
+enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw);
+enum ice_status
+ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
+ enum ice_ptp_link_spd *link_out,
+ enum ice_ptp_fec_mode *fec_out);
+void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
+
+/* E810 family functions */
+enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
+
+#define PFTSYN_SEM_BYTES 4
+
+#define ICE_PTP_CLOCK_INDEX_0 0x00
+#define ICE_PTP_CLOCK_INDEX_1 0x01
+
+/* PHY timer commands */
+#define SEL_CPK_SRC 8
+#define SEL_PHY_SRC 3
+
+/* Time Sync command Definitions */
+#define GLTSYN_CMD_INIT_TIME BIT(0)
+#define GLTSYN_CMD_INIT_INCVAL BIT(1)
+#define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
+#define GLTSYN_CMD_ADJ_TIME BIT(2)
+#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
+#define GLTSYN_CMD_READ_TIME BIT(7)
+
+/* PHY port Time Sync command definitions */
+#define PHY_CMD_INIT_TIME BIT(0)
+#define PHY_CMD_INIT_INCVAL BIT(1)
+#define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
+#define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
+#define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
+
+#define TS_CMD_MASK_E810 0xFF
+#define TS_CMD_MASK 0xF
+#define SYNC_EXEC_CMD 0x3
+
+/* Macros to derive port low and high addresses on both quads */
+#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
+#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
+#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
+#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
+
+/* PHY QUAD register base addresses */
+#define Q_0_BASE 0x94000
+#define Q_1_BASE 0x114000
+
+/* Timestamp memory reset registers */
+#define Q_REG_TS_CTRL 0x618
+#define Q_REG_TS_CTRL_S 0
+#define Q_REG_TS_CTRL_M BIT(0)
+
+/* Timestamp availability status registers */
+#define Q_REG_TX_MEMORY_STATUS_L 0xCF0
+#define Q_REG_TX_MEMORY_STATUS_U 0xCF4
+
+/* Tx FIFO status registers */
+#define Q_REG_FIFO23_STATUS 0xCF8
+#define Q_REG_FIFO01_STATUS 0xCFC
+#define Q_REG_FIFO02_S 0
+#define Q_REG_FIFO02_M MAKEMASK(0x3FF, 0)
+#define Q_REG_FIFO13_S 10
+#define Q_REG_FIFO13_M MAKEMASK(0x3FF, 10)
+
+/* Interrupt control Config registers */
+#define Q_REG_TX_MEM_GBL_CFG 0xC08
+#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
+#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
+#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
+#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M MAKEMASK(0xFF, 1)
+#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
+#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M MAKEMASK(0x3F, 9)
+#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
+#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
+
+/* Tx Timestamp data registers */
+#define Q_REG_TX_MEMORY_BANK_START 0xA00
+
+/* PHY port register base addresses */
+#define P_0_BASE 0x80000
+#define P_4_BASE 0x106000
+
+/* Timestamp init registers */
+#define P_REG_RX_TIMER_INC_PRE_L 0x46C
+#define P_REG_RX_TIMER_INC_PRE_U 0x470
+#define P_REG_TX_TIMER_INC_PRE_L 0x44C
+#define P_REG_TX_TIMER_INC_PRE_U 0x450
+
+/* Timestamp match and adjust target registers */
+#define P_REG_RX_TIMER_CNT_ADJ_L 0x474
+#define P_REG_RX_TIMER_CNT_ADJ_U 0x478
+#define P_REG_TX_TIMER_CNT_ADJ_L 0x454
+#define P_REG_TX_TIMER_CNT_ADJ_U 0x458
+
+/* Timestamp capture registers */
+#define P_REG_RX_CAPTURE_L 0x4D8
+#define P_REG_RX_CAPTURE_U 0x4DC
+#define P_REG_TX_CAPTURE_L 0x4B4
+#define P_REG_TX_CAPTURE_U 0x4B8
+
+/* Timestamp PHY incval registers */
+#define P_REG_TIMETUS_L 0x410
+#define P_REG_TIMETUS_U 0x414
+
+#define P_REG_40B_LOW_M 0xFF
+#define P_REG_40B_HIGH_S 8
+
+/* PHY window length registers */
+#define P_REG_WL 0x40C
+
+#define PTP_VERNIER_WL 0x111ed
+
+/* PHY start registers */
+#define P_REG_PS 0x408
+#define P_REG_PS_START_S 0
+#define P_REG_PS_START_M BIT(0)
+#define P_REG_PS_BYPASS_MODE_S 1
+#define P_REG_PS_BYPASS_MODE_M BIT(1)
+#define P_REG_PS_ENA_CLK_S 2
+#define P_REG_PS_ENA_CLK_M BIT(2)
+#define P_REG_PS_LOAD_OFFSET_S 3
+#define P_REG_PS_LOAD_OFFSET_M BIT(3)
+#define P_REG_PS_SFT_RESET_S 11
+#define P_REG_PS_SFT_RESET_M BIT(11)
+
+/* PHY offset valid registers */
+#define P_REG_TX_OV_STATUS 0x4D4
+#define P_REG_TX_OV_STATUS_OV_S 0
+#define P_REG_TX_OV_STATUS_OV_M BIT(0)
+#define P_REG_RX_OV_STATUS 0x4F8
+#define P_REG_RX_OV_STATUS_OV_S 0
+#define P_REG_RX_OV_STATUS_OV_M BIT(0)
+
+/* PHY offset ready registers */
+#define P_REG_TX_OR 0x45C
+#define P_REG_RX_OR 0x47C
+
+/* PHY total offset registers */
+#define P_REG_TOTAL_RX_OFFSET_L 0x460
+#define P_REG_TOTAL_RX_OFFSET_U 0x464
+#define P_REG_TOTAL_TX_OFFSET_L 0x440
+#define P_REG_TOTAL_TX_OFFSET_U 0x444
+
+/* Timestamp PAR/PCS registers */
+#define P_REG_UIX66_10G_40G_L 0x480
+#define P_REG_UIX66_10G_40G_U 0x484
+#define P_REG_UIX66_25G_100G_L 0x488
+#define P_REG_UIX66_25G_100G_U 0x48C
+#define P_REG_DESK_PAR_RX_TUS_L 0x490
+#define P_REG_DESK_PAR_RX_TUS_U 0x494
+#define P_REG_DESK_PAR_TX_TUS_L 0x498
+#define P_REG_DESK_PAR_TX_TUS_U 0x49C
+#define P_REG_DESK_PCS_RX_TUS_L 0x4A0
+#define P_REG_DESK_PCS_RX_TUS_U 0x4A4
+#define P_REG_DESK_PCS_TX_TUS_L 0x4A8
+#define P_REG_DESK_PCS_TX_TUS_U 0x4AC
+#define P_REG_PAR_RX_TUS_L 0x420
+#define P_REG_PAR_RX_TUS_U 0x424
+#define P_REG_PAR_TX_TUS_L 0x428
+#define P_REG_PAR_TX_TUS_U 0x42C
+#define P_REG_PCS_RX_TUS_L 0x430
+#define P_REG_PCS_RX_TUS_U 0x434
+#define P_REG_PCS_TX_TUS_L 0x438
+#define P_REG_PCS_TX_TUS_U 0x43C
+#define P_REG_PAR_RX_TIME_L 0x4F0
+#define P_REG_PAR_RX_TIME_U 0x4F4
+#define P_REG_PAR_TX_TIME_L 0x4CC
+#define P_REG_PAR_TX_TIME_U 0x4D0
+#define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
+#define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
+#define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
+#define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
+#define P_REG_LINK_SPEED 0x4FC
+#define P_REG_LINK_SPEED_SERDES_S 0
+#define P_REG_LINK_SPEED_SERDES_M MAKEMASK(0x7, 0)
+#define P_REG_LINK_SPEED_FEC_MODE_S 3
+#define P_REG_LINK_SPEED_FEC_MODE_M MAKEMASK(0x3, 3)
+#define P_REG_LINK_SPEED_FEC_MODE(reg) \
+ (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
+ P_REG_LINK_SPEED_FEC_MODE_S)
+
+/* PHY timestamp related registers */
+#define P_REG_PMD_ALIGNMENT 0x0FC
+#define P_REG_RX_80_TO_160_CNT 0x6FC
+#define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
+#define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
+#define P_REG_RX_40_TO_160_CNT 0x8FC
+#define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
+#define P_REG_RX_40_TO_160_CNT_RXCYC_M MAKEMASK(0x3, 0)
+
+/* Rx FIFO status registers */
+#define P_REG_RX_OV_FS 0x4F8
+#define P_REG_RX_OV_FS_FIFO_STATUS_S 2
+#define P_REG_RX_OV_FS_FIFO_STATUS_M MAKEMASK(0x3FF, 2)
+
+/* Timestamp command registers */
+#define P_REG_TX_TMR_CMD 0x448
+#define P_REG_RX_TMR_CMD 0x468
+
+/* E810 timesync enable register */
+#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
+
+/* E810 shadow init time registers */
+#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
+#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
+
+/* E810 shadow time adjust registers */
+#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
+#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
+
+/* E810 timer command register */
+#define ETH_GLTSYN_CMD 0x03000344
+
+/* Source timer incval macros */
+#define INCVAL_HIGH_M 0xFF
+
+/* Timestamp block macros */
+#define TS_LOW_M 0xFFFFFFFF
+#define TS_HIGH_M 0xFF
+#define TS_HIGH_S 32
+
+#define TS_PHY_LOW_M 0xFF
+#define TS_PHY_HIGH_M 0xFFFFFFFF
+#define TS_PHY_HIGH_S 8
+
+#define BYTES_PER_IDX_ADDR_L_U 8
+#define BYTES_PER_IDX_ADDR_L 4
+
+/* Internal PHY timestamp address */
+#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
+#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
+ BYTES_PER_IDX_ADDR_L))
+
+/* External PHY timestamp address */
+#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
+ ((idx) * BYTES_PER_IDX_ADDR_L_U))
+
+#define LOW_TX_MEMORY_BANK_START 0x03090000
+#define HIGH_TX_MEMORY_BANK_START 0x03090004
+
+/* E810T PCA9575 IO controller registers */
+#define ICE_PCA9575_P0_IN 0x0
+#define ICE_PCA9575_P1_IN 0x1
+#define ICE_PCA9575_P0_CFG 0x8
+#define ICE_PCA9575_P1_CFG 0x9
+#define ICE_PCA9575_P0_OUT 0xA
+#define ICE_PCA9575_P1_OUT 0xB
+
+/* E810T PCA9575 IO controller pin control */
+#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
+#define ICE_E810T_P1_SMA1_DIR_EN BIT(4)
+#define ICE_E810T_P1_SMA1_TX_EN BIT(5)
+#define ICE_E810T_P1_SMA2_UFL2_RX_DIS BIT(3)
+#define ICE_E810T_P1_SMA2_DIR_EN BIT(6)
+#define ICE_E810T_P1_SMA2_TX_EN BIT(7)
+
+#endif /* _ICE_PTP_HW_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index daf1ac6ef6..2bd2318b13 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -55,6 +55,7 @@
#include "ice_lan_tx_rx.h"
#include "ice_flex_type.h"
#include "ice_protocol_type.h"
+#include "ice_sbq_cmd.h"
#include "ice_vlan_mode.h"
/**
@@ -131,6 +132,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
#define ICE_DBG_PKG BIT_ULL(16)
#define ICE_DBG_RES BIT_ULL(17)
#define ICE_DBG_ACL BIT_ULL(18)
+#define ICE_DBG_PTP BIT_ULL(19)
#define ICE_DBG_AQ_MSG BIT_ULL(24)
#define ICE_DBG_AQ_DESC BIT_ULL(25)
#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
@@ -1016,6 +1018,7 @@ struct ice_hw {
/* Control Queue info */
struct ice_ctl_q_info adminq;
+ struct ice_ctl_q_info sbq;
struct ice_ctl_q_info mailboxq;
/* Additional function to send AdminQ command */
int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
diff --git a/drivers/net/ice/base/meson.build b/drivers/net/ice/base/meson.build
index 3305e5dd18..a5db1a5b00 100644
--- a/drivers/net/ice/base/meson.build
+++ b/drivers/net/ice/base/meson.build
@@ -14,6 +14,7 @@ sources = [
'ice_acl.c',
'ice_acl_ctrl.c',
'ice_vlan_mode.c',
+ 'ice_ptp_hw.c',
]
error_cflags = [
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 03/28] net/ice/base: add ethertype IPv6 check for dummy packet
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
2021-08-10 2:51 ` [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe Qi Zhang
2021-08-10 2:51 ` [dpdk-dev] [PATCH 02/28] net/ice/base: add low level functions for device clock control Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:34 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 04/28] net/ice/base: change dummy packets with VLAN Qi Zhang
` (25 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Grzegorz Nitka
In order to support switch rule for ethertype filter
with ipv6 ethertype id, it has to check ethertype and
then find a proper dummy packet. There was a silent
assumption that packet is ipv4, unless src or dst ipv6
address is specified in a flow.
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 5926635088..4a829859f4 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -10,9 +10,9 @@
#define ICE_ETH_ETHTYPE_OFFSET 12
#define ICE_ETH_VLAN_TCI_OFFSET 14
#define ICE_MAX_VLAN_ID 0xFFF
+#define ICE_IPV6_ETHER_ID 0x86DD
#define ICE_IPV4_NVGRE_PROTO_ID 0x002F
#define ICE_PPP_IPV6_PROTO_ID 0x0057
-#define ICE_IPV6_ETHER_ID 0x86DD
#define ICE_TCP_PROTO_ID 0x06
#define ICE_GTPU_PROFILE 24
#define ICE_ETH_P_8021Q 0x8100
@@ -7889,6 +7889,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
ipv6 = true;
else if (lkups[i].type == ICE_VLAN_OFOS)
vlan = true;
+ else if (lkups[i].type == ICE_ETYPE_OL &&
+ lkups[i].h_u.ethertype.ethtype_id ==
+ CPU_TO_BE16(ICE_IPV6_ETHER_ID) &&
+ lkups[i].m_u.ethertype.ethtype_id ==
+ CPU_TO_BE16(0xFFFF))
+ ipv6 = true;
else if (lkups[i].type == ICE_IPV4_OFOS &&
lkups[i].h_u.ipv4_hdr.protocol ==
ICE_IPV4_NVGRE_PROTO_ID &&
@@ -7901,12 +7907,6 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
lkups[i].m_u.pppoe_hdr.ppp_prot_id ==
0xFFFF)
ipv6 = true;
- else if (lkups[i].type == ICE_ETYPE_OL &&
- lkups[i].h_u.ethertype.ethtype_id ==
- CPU_TO_BE16(ICE_IPV6_ETHER_ID) &&
- lkups[i].m_u.ethertype.ethtype_id ==
- 0xFFFF)
- ipv6 = true;
else if (lkups[i].type == ICE_IPV4_IL &&
lkups[i].h_u.ipv4_hdr.protocol ==
ICE_TCP_PROTO_ID &&
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 04/28] net/ice/base: change dummy packets with VLAN
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (2 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 03/28] net/ice/base: add ethertype IPv6 check for dummy packet Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:35 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks Qi Zhang
` (24 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Michal Swiatkowski
Ethertype was traded as VLAN tpid in dummy packets with VLAN.
This led to a problem when user wanted to add filter for VLAN and
ethertype.
Change ice_vlan_hdr to reflect correct order of VLAN fields in
packets (VLAN tpid, VLAN id). Correct all dummy packets with VLAN.
Move VLAN fields before ethertype and change offsets. Leave values
from dummy packets unchanged as they fit to new VLAN layout.
Order of offsets in ice_prot_ext_tbl_entry for VLAN protocol should
reflect order of fields in ice_vlan_hdr. However, hardware doesn't
support matching on all tpid. This should be done by matching on
packet flags. There is no FV word with protocol for VLAN and offset
2. Because of that, adding vlan tpid with not zero mask will lead
to error in creating recipe.
Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_protocol_type.h | 2 +-
drivers/net/ice/base/ice_switch.c | 148 +++++++++++------------
2 files changed, 73 insertions(+), 77 deletions(-)
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index d1d266ffd2..220ff3b773 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -245,8 +245,8 @@ struct ice_ether_vlan_hdr {
};
struct ice_vlan_hdr {
- __be16 vlan;
__be16 type;
+ __be16 vlan;
};
struct ice_ipv4_hdr {
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 4a829859f4..0b2347ba3a 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -260,8 +260,8 @@ static const u8 dummy_udp_packet[] = {
/* offset info for MAC + VLAN + IPv4 + UDP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_vlan_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14 },
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_IPV4_OFOS, 18 },
{ ICE_UDP_ILOS, 38 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -273,9 +273,9 @@ static const u8 dummy_vlan_udp_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x08, 0x00, /* ICE_VLAN_OFOS 14 */
+ 0x08, 0x00, /* ICE_ETYPE_OL 16 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 18 */
0x00, 0x01, 0x00, 0x00,
@@ -343,8 +343,8 @@ static const u8 dummy_mpls_packet[] = {
/* offset info for MAC + VLAN (C-tag, 802.1Q) + IPv4 + TCP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_vlan_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14 },
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_IPV4_OFOS, 18 },
{ ICE_TCP_IL, 38 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -356,9 +356,9 @@ static const u8 dummy_vlan_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x08, 0x00, /* ICE_VLAN_OFOS 14 */
+ 0x08, 0x00, /* ICE_ETYPE_OL 16 */
0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 18 */
0x00, 0x01, 0x00, 0x00,
@@ -414,8 +414,8 @@ static const u8 dummy_tcp_ipv6_packet[] = {
static const struct ice_dummy_pkt_offsets
dummy_vlan_tcp_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14 },
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_IPV6_OFOS, 18 },
{ ICE_TCP_IL, 58 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -427,9 +427,9 @@ static const u8 dummy_vlan_tcp_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x86, 0xDD, /* ICE_VLAN_OFOS 14 */
+ 0x86, 0xDD, /* ICE_ETYPE_OL 16 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 18 */
0x00, 0x14, 0x06, 0x00, /* Next header is TCP */
@@ -492,8 +492,8 @@ static const u8 dummy_udp_ipv6_packet[] = {
static const struct ice_dummy_pkt_offsets
dummy_vlan_udp_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14 },
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_IPV6_OFOS, 18 },
{ ICE_UDP_ILOS, 58 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -505,9 +505,9 @@ static const u8 dummy_vlan_udp_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00,/* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x86, 0xDD, /* ICE_VLAN_OFOS 14 */
+ 0x86, 0xDD, /* ICE_ETYPE_OL 16 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 18 */
0x00, 0x08, 0x11, 0x00, /* Next header UDP */
@@ -1192,16 +1192,16 @@ static const u8 dummy_ipv6_gtp_packet[] = {
static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_PROTOCOL_LAST, 0 },
};
static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv4_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV4_OFOS, 26 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -1212,9 +1212,9 @@ static const u8 dummy_pppoe_ipv4_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x16,
@@ -1233,8 +1233,8 @@ static const u8 dummy_pppoe_ipv4_packet[] = {
static const
struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV4_OFOS, 26 },
{ ICE_TCP_IL, 46 },
@@ -1246,9 +1246,9 @@ static const u8 dummy_pppoe_ipv4_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x16,
@@ -1273,8 +1273,8 @@ static const u8 dummy_pppoe_ipv4_tcp_packet[] = {
static const
struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_udp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV4_OFOS, 26 },
{ ICE_UDP_ILOS, 46 },
@@ -1286,9 +1286,9 @@ static const u8 dummy_pppoe_ipv4_udp_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x16,
@@ -1309,8 +1309,8 @@ static const u8 dummy_pppoe_ipv4_udp_packet[] = {
static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV6_OFOS, 26 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -1321,9 +1321,9 @@ static const u8 dummy_pppoe_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x2a,
@@ -1347,8 +1347,8 @@ static const u8 dummy_pppoe_ipv6_packet[] = {
static const
struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_tcp_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV6_OFOS, 26 },
{ ICE_TCP_IL, 66 },
@@ -1360,9 +1360,9 @@ static const u8 dummy_pppoe_ipv6_tcp_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x2a,
@@ -1392,8 +1392,8 @@ static const u8 dummy_pppoe_ipv6_tcp_packet[] = {
static const
struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_udp_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_OFOS, 14},
+ { ICE_VLAN_OFOS, 12 },
+ { ICE_ETYPE_OL, 16 },
{ ICE_PPPOE, 18 },
{ ICE_IPV6_OFOS, 26 },
{ ICE_UDP_ILOS, 66 },
@@ -1405,9 +1405,9 @@ static const u8 dummy_pppoe_ipv6_udp_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x81, 0x00, /* ICE_ETYPE_OL 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 16 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */
0x00, 0x2a,
@@ -1658,9 +1658,9 @@ static const u8 dummy_ipv6_l2tpv3_pkt[] = {
static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_EX, 14 },
- { ICE_VLAN_IN, 18 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_IPV4_OFOS, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
@@ -1670,10 +1670,9 @@ static const u8 dummy_qinq_ipv4_pkt[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x91, 0x00, /* ICE_ETYPE_OL 12 */
-
- 0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
- 0x00, 0x00, 0x08, 0x00, /* ICE_VLAN_IN 18 */
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x08, 0x00, /* ICE_ETYPE_OL 20 */
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 22 */
0x00, 0x01, 0x00, 0x00,
@@ -1689,9 +1688,9 @@ static const u8 dummy_qinq_ipv4_pkt[] = {
static const struct ice_dummy_pkt_offsets dummy_qinq_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_EX, 14 },
- { ICE_VLAN_IN, 18 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_IPV6_OFOS, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
@@ -1701,10 +1700,9 @@ static const u8 dummy_qinq_ipv6_pkt[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x91, 0x00, /* ICE_ETYPE_OL 12 */
-
- 0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
- 0x00, 0x00, 0x86, 0xDD, /* ICE_VLAN_IN 18 */
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x86, 0xDD, /* ICE_ETYPE_OL 20 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
0x00, 0x10, 0x11, 0x00, /* Next header UDP */
@@ -1728,9 +1726,9 @@ static const u8 dummy_qinq_ipv6_pkt[] = {
static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_EX, 14 },
- { ICE_VLAN_IN, 18 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_PPPOE, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
@@ -1738,9 +1736,9 @@ static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = {
static const
struct ice_dummy_pkt_offsets dummy_qinq_pppoe_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_EX, 14 },
- { ICE_VLAN_IN, 18 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_PPPOE, 22 },
{ ICE_IPV4_OFOS, 30 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -1751,10 +1749,9 @@ static const u8 dummy_qinq_pppoe_ipv4_pkt[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x91, 0x00, /* ICE_ETYPE_OL 12 */
-
- 0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_IN 18 */
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 20 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */
0x00, 0x16,
@@ -1773,9 +1770,9 @@ static const u8 dummy_qinq_pppoe_ipv4_pkt[] = {
static const
struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_ipv6_offsets[] = {
{ ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_VLAN_EX, 14},
- { ICE_VLAN_IN, 18 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_PPPOE, 22 },
{ ICE_IPV6_OFOS, 30 },
{ ICE_PROTOCOL_LAST, 0 },
@@ -1786,10 +1783,9 @@ static const u8 dummy_qinq_pppoe_ipv6_packet[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x91, 0x00, /* ICE_ETYPE_OL 12 */
-
- 0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
- 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_IN 18 */
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x88, 0x64, /* ICE_ETYPE_OL 20 */
0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */
0x00, 0x2a,
@@ -6575,7 +6571,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = {
{ ICE_MAC_OFOS, { 0, 2, 4, 6, 8, 10, 12 } },
{ ICE_MAC_IL, { 0, 2, 4, 6, 8, 10, 12 } },
{ ICE_ETYPE_OL, { 0 } },
- { ICE_VLAN_OFOS, { 0, 2 } },
+ { ICE_VLAN_OFOS, { 2, 0 } },
{ ICE_IPV4_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } },
{ ICE_IPV4_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } },
{ ICE_IPV6_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24,
@@ -6598,8 +6594,8 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = {
{ ICE_AH, { 0, 2, 4, 6, 8, 10 } },
{ ICE_NAT_T, { 8, 10, 12, 14 } },
{ ICE_GTP_NO_PAY, { 8, 10, 12, 14 } },
- { ICE_VLAN_EX, { 0, 2 } },
- { ICE_VLAN_IN, { 0, 2 } },
+ { ICE_VLAN_EX, { 2, 0 } },
+ { ICE_VLAN_IN, { 2, 0 } },
};
/* The following table describes preferred grouping of recipes.
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (3 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 04/28] net/ice/base: change dummy packets with VLAN Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:35 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization function Qi Zhang
` (23 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Vignesh Sridhar
Adding macros for shift and masking of the lower timestamp work in the
Rx flex descriptor. The LSB of the timestamp-low word indicates the
validity of the timestamp while the rest 7 bits contain the timestamp.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 696c6a30ae..4255e9963e 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -879,6 +879,14 @@ enum ice_rx_flex_desc_exstat_bits {
ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
};
+/* For ice_32b_rx_flex_desc.ts_low:
+ * [0]: Timestamp-low validity bit
+ * [1:7]: Timestamp-low value
+ */
+#define ICE_RX_FLEX_DESC_TS_L_VALID_S 0x01
+#define ICE_RX_FLEX_DESC_TS_L_VALID_M ICE_RX_FLEX_DESC_TS_L_VALID_S
+#define ICE_RX_FLEX_DESC_TS_L_M 0xFE
+
#define ICE_RXQ_CTX_SIZE_DWORDS 8
#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization function
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (4 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:36 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 07/28] net/ice/base: add accessors to get/set the time reference Qi Zhang
` (22 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
Before the device PTP hardware clock can be initialized, some steps must
be taken by the driver. This includes writing some registers and
initializing the PHY.
Some of these steps are distinct depending on the device type (E810 or
E822). Additionally, a future change will introduce more steps for E822
devices to program the Clock Generation Unit.
Introduce ice_ptp_init_phc as well as device-specific sub-functions for
e810 and e822 devices.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_cgu_regs.h | 117 +++++++++
drivers/net/ice/base/ice_ptp_consts.h | 74 ++++++
drivers/net/ice/base/ice_ptp_hw.c | 348 +++++++++++++++++++++++++-
drivers/net/ice/base/ice_ptp_hw.h | 24 ++
4 files changed, 562 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ice/base/ice_cgu_regs.h
diff --git a/drivers/net/ice/base/ice_cgu_regs.h b/drivers/net/ice/base/ice_cgu_regs.h
new file mode 100644
index 0000000000..6751481e83
--- /dev/null
+++ b/drivers/net/ice/base/ice_cgu_regs.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2021 Intel Corporation
+ */
+
+#ifndef _ICE_CGU_REGS_H_
+#define _ICE_CGU_REGS_H_
+
+#define NAC_CGU_DWORD9 0x24
+union nac_cgu_dword9 {
+ struct {
+ u32 time_ref_freq_sel : 3;
+ u32 clk_eref1_en : 1;
+ u32 clk_eref0_en : 1;
+ u32 time_ref_en : 1;
+ u32 time_sync_en : 1;
+ u32 one_pps_out_en : 1;
+ u32 clk_ref_synce_en : 1;
+ u32 clk_synce1_en : 1;
+ u32 clk_synce0_en : 1;
+ u32 net_clk_ref1_en : 1;
+ u32 net_clk_ref0_en : 1;
+ u32 clk_synce1_amp : 2;
+ u32 misc6 : 1;
+ u32 clk_synce0_amp : 2;
+ u32 one_pps_out_amp : 2;
+ u32 misc24 : 12;
+ } field;
+ u32 val;
+};
+
+#define NAC_CGU_DWORD19 0x4c
+union nac_cgu_dword19 {
+ struct {
+ u32 tspll_fbdiv_intgr : 8;
+ u32 fdpll_ulck_thr : 5;
+ u32 misc15 : 3;
+ u32 tspll_ndivratio : 4;
+ u32 tspll_iref_ndivratio : 3;
+ u32 misc19 : 1;
+ u32 japll_ndivratio : 4;
+ u32 japll_iref_ndivratio : 3;
+ u32 misc27 : 1;
+ } field;
+ u32 val;
+};
+
+#define NAC_CGU_DWORD22 0x58
+union nac_cgu_dword22 {
+ struct {
+ u32 fdpll_frac_div_out_nc : 2;
+ u32 fdpll_lock_int_for : 1;
+ u32 synce_hdov_int_for : 1;
+ u32 synce_lock_int_for : 1;
+ u32 fdpll_phlead_slip_nc : 1;
+ u32 fdpll_acc1_ovfl_nc : 1;
+ u32 fdpll_acc2_ovfl_nc : 1;
+ u32 synce_status_nc : 6;
+ u32 fdpll_acc1f_ovfl : 1;
+ u32 misc18 : 1;
+ u32 fdpllclk_div : 4;
+ u32 time1588clk_div : 4;
+ u32 synceclk_div : 4;
+ u32 synceclk_sel_div2 : 1;
+ u32 fdpllclk_sel_div2 : 1;
+ u32 time1588clk_sel_div2 : 1;
+ u32 misc3 : 1;
+ } field;
+ u32 val;
+};
+
+#define NAC_CGU_DWORD24 0x60
+union nac_cgu_dword24 {
+ struct {
+ u32 tspll_fbdiv_frac : 22;
+ u32 misc20 : 2;
+ u32 ts_pll_enable : 1;
+ u32 time_sync_tspll_align_sel : 1;
+ u32 ext_synce_sel : 1;
+ u32 ref1588_ck_div : 4;
+ u32 time_ref_sel : 1;
+ } field;
+ u32 val;
+};
+
+#define TSPLL_CNTR_BIST_SETTINGS 0x344
+union tspll_cntr_bist_settings {
+ struct {
+ u32 i_irefgen_settling_time_cntr_7_0 : 8;
+ u32 i_irefgen_settling_time_ro_standby_1_0 : 2;
+ u32 reserved195 : 5;
+ u32 i_plllock_sel_0 : 1;
+ u32 i_plllock_sel_1 : 1;
+ u32 i_plllock_cnt_6_0 : 7;
+ u32 i_plllock_cnt_10_7 : 4;
+ u32 reserved200 : 4;
+ } field;
+ u32 val;
+};
+
+#define TSPLL_RO_BWM_LF 0x370
+union tspll_ro_bwm_lf {
+ struct {
+ u32 bw_freqov_high_cri_7_0 : 8;
+ u32 bw_freqov_high_cri_9_8 : 2;
+ u32 biascaldone_cri : 1;
+ u32 plllock_gain_tran_cri : 1;
+ u32 plllock_true_lock_cri : 1;
+ u32 pllunlock_flag_cri : 1;
+ u32 afcerr_cri : 1;
+ u32 afcdone_cri : 1;
+ u32 feedfwrdgain_cal_cri_7_0 : 8;
+ u32 m2fbdivmod_cri_7_0 : 8;
+ } field;
+ u32 val;
+};
+
+#endif /* _ICE_CGU_REGS_H_ */
diff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h
index 2bd338c88c..4583dd42ff 100644
--- a/drivers/net/ice/base/ice_ptp_consts.h
+++ b/drivers/net/ice/base/ice_ptp_consts.h
@@ -83,4 +83,78 @@ const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {
},
};
+const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
+ /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ {
+ /* refclk_pre_div */
+ 1,
+ /* feedback_div */
+ 197,
+ /* frac_n_div */
+ 2621440,
+ /* post_pll_div */
+ 6,
+ },
+
+ /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 223,
+ /* frac_n_div */
+ 524288,
+ /* post_pll_div */
+ 7,
+ },
+
+ /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 223,
+ /* frac_n_div */
+ 524288,
+ /* post_pll_div */
+ 7,
+ },
+
+ /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 159,
+ /* frac_n_div */
+ 1572864,
+ /* post_pll_div */
+ 6,
+ },
+
+ /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 159,
+ /* frac_n_div */
+ 1572864,
+ /* post_pll_div */
+ 6,
+ },
+
+ /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ {
+ /* refclk_pre_div */
+ 10,
+ /* feedback_div */
+ 223,
+ /* frac_n_div */
+ 524288,
+ /* post_pll_div */
+ 7,
+ },
+};
+
#endif /* _ICE_PTP_CONSTS_H_ */
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 8aefcf93fd..cb32a4fb48 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -6,7 +6,7 @@
#include "ice_common.h"
#include "ice_ptp_hw.h"
#include "ice_ptp_consts.h"
-
+#include "ice_cgu_regs.h"
/* Low level functions for interacting with and managing the device clock used
* for the Precision Time Protocol.
@@ -699,6 +699,315 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
return ICE_SUCCESS;
}
+/**
+ * ice_read_cgu_reg_e822 - Read a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to read
+ * @val: storage for register value read
+ *
+ * Read the contents of a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static enum ice_status
+ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ enum ice_status status;
+
+ cgu_msg.opcode = ice_sbq_msg_rd;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+
+ status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, status %d\n",
+ addr, status);
+ return status;
+ }
+
+ *val = cgu_msg.data;
+
+ return status;
+}
+
+/**
+ * ice_write_cgu_reg_e822 - Write a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to write
+ * @val: value to write into the register
+ *
+ * Write the specified value to a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static enum ice_status
+ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ enum ice_status status;
+
+ cgu_msg.opcode = ice_sbq_msg_wr;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+ cgu_msg.data = val;
+
+ status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, status %d\n",
+ addr, status);
+ return status;
+ }
+
+ return status;
+}
+
+/**
+ * ice_clk_freq_str - Convert time_ref_freq to string
+ * @clk_freq: Clock frequency
+ *
+ * Convert the specified TIME_REF clock frequency to a string.
+ */
+static const char *ice_clk_freq_str(u8 clk_freq)
+{
+ switch ((enum ice_time_ref_freq)clk_freq) {
+ case ICE_TIME_REF_FREQ_25_000:
+ return "25 MHz";
+ case ICE_TIME_REF_FREQ_122_880:
+ return "122.88 MHz";
+ case ICE_TIME_REF_FREQ_125_000:
+ return "125 MHz";
+ case ICE_TIME_REF_FREQ_153_600:
+ return "153.6 MHz";
+ case ICE_TIME_REF_FREQ_156_250:
+ return "156.25 MHz";
+ case ICE_TIME_REF_FREQ_245_760:
+ return "245.76 MHz";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_clk_src_str - Convert time_ref_src to string
+ * @clk_src: Clock source
+ *
+ * Convert the specified clock source to its string name.
+ */
+static const char *ice_clk_src_str(u8 clk_src)
+{
+ switch ((enum ice_clk_src)clk_src) {
+ case ICE_CLK_SRC_TCX0:
+ return "TCX0";
+ case ICE_CLK_SRC_TIME_REF:
+ return "TIME_REF";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit
+ * @hw: pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCX0)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the PLL which drives the PTP hardware clock.
+ */
+enum ice_status
+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
+ enum ice_clk_src clk_src)
+{
+ union tspll_ro_bwm_lf bwm_lf;
+ union nac_cgu_dword19 dw19;
+ union nac_cgu_dword22 dw22;
+ union nac_cgu_dword24 dw24;
+ union nac_cgu_dword9 dw9;
+ enum ice_status status;
+
+ if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq);
+ return ICE_ERR_PARAM;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ ice_warn(hw, "Invalid clock source %u\n", clk_src);
+ return ICE_ERR_PARAM;
+ }
+
+ if (clk_src == ICE_CLK_SRC_TCX0 &&
+ clk_freq != ICE_TIME_REF_FREQ_25_000) {
+ ice_warn(hw, "TCX0 only supports 25 MHz frequency\n");
+ return ICE_ERR_PARAM;
+ }
+
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);
+ if (status)
+ return status;
+
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (status)
+ return status;
+
+ status = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ if (status)
+ return status;
+
+ /* Log the current clock configuration */
+ ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ dw24.field.ts_pll_enable ? "enabled" : "disabled",
+ ice_clk_src_str(dw24.field.time_ref_sel),
+ ice_clk_freq_str(dw9.field.time_ref_freq_sel),
+ bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
+
+ /* Disable the PLL before changing the clock source or frequency */
+ if (dw24.field.ts_pll_enable) {
+ dw24.field.ts_pll_enable = 0;
+
+ status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
+ if (status)
+ return status;
+ }
+
+ /* Set the frequency */
+ dw9.field.time_ref_freq_sel = clk_freq;
+ status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);
+ if (status)
+ return status;
+
+ /* Configure the TS PLL feedback divisor */
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);
+ if (status)
+ return status;
+
+ dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
+ dw19.field.tspll_ndivratio = 1;
+
+ status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);
+ if (status)
+ return status;
+
+ /* Configure the TS PLL post divisor */
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);
+ if (status)
+ return status;
+
+ dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
+ dw22.field.time1588clk_sel_div2 = 0;
+
+ status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);
+ if (status)
+ return status;
+
+ /* Configure the TS PLL pre divisor and clock source */
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (status)
+ return status;
+
+ dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
+ dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
+ dw24.field.time_ref_sel = clk_src;
+
+ status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
+ if (status)
+ return status;
+
+ /* Finally, enable the PLL */
+ dw24.field.ts_pll_enable = 1;
+
+ status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);
+ if (status)
+ return status;
+
+ /* Wait to verify if the PLL locks */
+ ice_msec_delay(1, true);
+
+ status = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ if (status)
+ return status;
+
+ if (!bwm_lf.field.plllock_true_lock_cri) {
+ ice_warn(hw, "CGU PLL failed to lock\n");
+ return ICE_ERR_NOT_READY;
+ }
+
+ /* Log the current clock configuration */
+ ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ dw24.field.ts_pll_enable ? "enabled" : "disabled",
+ ice_clk_src_str(dw24.field.time_ref_sel),
+ ice_clk_freq_str(dw9.field.time_ref_freq_sel),
+ bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
+
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_init_cgu_e822 - Initialize CGU with settings from firmware
+ * @hw: pointer to the HW structure
+ *
+ * Initialize the Clock Generation Unit of the E822 device.
+ */
+static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)
+{
+ struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
+ union tspll_cntr_bist_settings cntr_bist;
+ enum ice_status status;
+
+ status = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
+ &cntr_bist.val);
+ if (status)
+ return status;
+
+ /* Disable sticky lock detection so lock status reported is accurate */
+ cntr_bist.field.i_plllock_sel_0 = 0;
+ cntr_bist.field.i_plllock_sel_1 = 0;
+
+ status = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,
+ cntr_bist.val);
+ if (status)
+ return status;
+
+ /* Configure the CGU PLL using the parameters from the function
+ * capabilities.
+ */
+ status = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,
+ (enum ice_clk_src)ts_info->clk_src);
+ if (status)
+ return status;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization
+ * @hw: pointer to HW struct
+ *
+ * Perform PHC initialization steps specific to E822 devices.
+ */
+static enum ice_status ice_ptp_init_phc_e822(struct ice_hw *hw)
+{
+ enum ice_status status;
+ u32 regval;
+
+ /* Enable reading switch and PHY registers over the sideband queue */
+#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
+#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
+ regval = rd32(hw, PF_SB_REM_DEV_CTL);
+ regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
+ PF_SB_REM_DEV_CTL_PHY0);
+ wr32(hw, PF_SB_REM_DEV_CTL, regval);
+
+ /* Initialize the Clock Generation Unit */
+ status = ice_init_cgu_e822(hw);
+ if (status)
+ return status;
+
+ /* Set window length for all the ports */
+ return ice_ptp_set_vernier_wl(hw);
+}
+
/**
* ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time
* @hw: pointer to the HW struct
@@ -1445,6 +1754,21 @@ enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw)
return status;
}
+/**
+ * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
+ * @hw: pointer to HW struct
+ *
+ * Perform E810-specific PTP hardware clock initialization steps.
+ */
+static enum ice_status ice_ptp_init_phc_e810(struct ice_hw *hw)
+{
+ /* Ensure synchronization delay is zero */
+ wr32(hw, GLTSYN_SYNC_DLAY, 0);
+
+ /* Initialize the PHY */
+ return ice_ptp_init_phy_e810(hw);
+}
+
/**
* ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
* @hw: Board private structure
@@ -2021,3 +2345,25 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
else
return ice_clear_phy_tstamp_e822(hw, block, idx);
}
+
+/**
+ * ice_ptp_init_phc - Initialize PTP hardware clock
+ * @hw: pointer to the HW struct
+ *
+ * Perform the steps required to initialize the PTP hardware clock.
+ */
+enum ice_status ice_ptp_init_phc(struct ice_hw *hw)
+{
+ u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
+
+ /* Enable source clocks */
+ wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
+
+ /* Clear event status indications for auxiliary pins */
+ (void)rd32(hw, GLTSYN_STAT(src_idx));
+
+ if (ice_is_e810(hw))
+ return ice_ptp_init_phc_e810(hw);
+ else
+ return ice_ptp_init_phc_e822(hw);
+}
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index 8cbe81792d..eb0e410ed8 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -55,6 +55,26 @@ struct ice_time_ref_info_e822 {
u8 pps_delay;
};
+/**
+ * struct ice_cgu_pll_params_e822
+ * @refclk_pre_div: Reference clock pre-divisor
+ * @feedback_div: Feedback divisor
+ * @frac_n_div: Fractional divisor
+ * @post_pll_div: Post PLL divisor
+ *
+ * Clock Generation Unit parameters used to program the PLL based on the
+ * selected TIME_REF frequency.
+ */
+struct ice_cgu_pll_params_e822 {
+ u32 refclk_pre_div;
+ u32 feedback_div;
+ u32 frac_n_div;
+ u32 post_pll_div;
+};
+
+extern const struct
+ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
+
/* Table of constants related to possible TIME_REF sources */
extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
@@ -79,6 +99,7 @@ enum ice_status
ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
enum ice_status
ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
+enum ice_status ice_ptp_init_phc(struct ice_hw *hw);
/* E822 family functions */
enum ice_status
@@ -99,6 +120,9 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);
enum ice_status
ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
bool lock_sbq);
+enum ice_status
+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
+ enum ice_clk_src clk_src);
static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
{
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 07/28] net/ice/base: add accessors to get/set the time reference
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (5 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization function Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:37 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types Qi Zhang
` (21 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
The E822 device clock might come from a variety of different sources,
called TIME_REFs. The firmware reports the current TIME_REF as part of
its function capabilities, which the driver caches when it loads.
Add an accessor function to look up the current TIME_REF from the
capabilities. This reduces line length significantly and also avoids
a tight coupling to the capabilities structure.
In some cases, TIME_REF might change at run time. This can occur in the
event that the CGU registers are updated. When this happens, its
possible that the capabilities structure can be out of date until the
capabilities are re-read.
Add an setter function to update the TIME_REF when this occurs. The
driver can call this function after updating the CGU to ensure that the
TIME_REF in the capabilities structure is up to date, without needing to
re-read the entire capabilities from firmware.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index eb0e410ed8..ad2349f60a 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -124,6 +124,31 @@ enum ice_status
ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
enum ice_clk_src clk_src);
+/**
+ * ice_e822_time_ref - Get the current TIME_REF from capabilities
+ * @hw: pointer to the HW structure
+ *
+ * Returns the current TIME_REF from the capabilities structure.
+ */
+static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
+{
+ return hw->func_caps.ts_func_info.time_ref;
+}
+
+/**
+ * ice_set_e822_time_ref - Set new TIME_REF
+ * @hw: pointer to the HW structure
+ * @time_ref: new TIME_REF to set
+ *
+ * Update the TIME_REF in the capabilities structure in response to some
+ * change, such as an update to the CGU registers.
+ */
+static inline void
+ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
+{
+ hw->func_caps.ts_func_info.time_ref = time_ref;
+}
+
static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
{
return e822_time_ref[time_ref].pll_freq;
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (6 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 07/28] net/ice/base: add accessors to get/set the time reference Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:37 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 09/28] net/ice/base: implement Vernier calibration logic for E822 devices Qi Zhang
` (20 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Anirudh Venkataramanan
Add functions to print PHY types in human-friendly form
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 164 ++++++++++++++++++++++++++----
1 file changed, 146 insertions(+), 18 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index e8d66aad6b..2447d15b87 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -11,6 +11,120 @@
#define ICE_PF_RESET_WAIT_COUNT 300
+/**
+ * dump_phy_type - helper function that prints PHY type strings
+ * @hw: pointer to the HW structure
+ * @phy: 64 bit PHY type to decipher
+ * @i: bit index within phy
+ * @phy_string: string corresponding to bit i in phy
+ * @prefix: prefix string to differentiate multiple dumps
+ */
+static void
+dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string,
+ const char *prefix)
+{
+ if (phy & BIT_ULL(i))
+ ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i,
+ phy_string);
+}
+
+/**
+ * ice_dump_phy_type_low - helper function to dump phy_type_low
+ * @hw: pointer to the HW structure
+ * @low: 64 bit value for phy_type_low
+ * @prefix: prefix string to differentiate multiple dumps
+ */
+static void
+ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix)
+{
+ ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix,
+ (unsigned long long)low);
+
+ dump_phy_type(hw, low, 0, "100BASE_TX", prefix);
+ dump_phy_type(hw, low, 1, "100M_SGMII", prefix);
+ dump_phy_type(hw, low, 2, "1000BASE_T", prefix);
+ dump_phy_type(hw, low, 3, "1000BASE_SX", prefix);
+ dump_phy_type(hw, low, 4, "1000BASE_LX", prefix);
+ dump_phy_type(hw, low, 5, "1000BASE_KX", prefix);
+ dump_phy_type(hw, low, 6, "1G_SGMII", prefix);
+ dump_phy_type(hw, low, 7, "2500BASE_T", prefix);
+ dump_phy_type(hw, low, 8, "2500BASE_X", prefix);
+ dump_phy_type(hw, low, 9, "2500BASE_KX", prefix);
+ dump_phy_type(hw, low, 10, "5GBASE_T", prefix);
+ dump_phy_type(hw, low, 11, "5GBASE_KR", prefix);
+ dump_phy_type(hw, low, 12, "10GBASE_T", prefix);
+ dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix);
+ dump_phy_type(hw, low, 14, "10GBASE_SR", prefix);
+ dump_phy_type(hw, low, 15, "10GBASE_LR", prefix);
+ dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix);
+ dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix);
+ dump_phy_type(hw, low, 19, "25GBASE_T", prefix);
+ dump_phy_type(hw, low, 20, "25GBASE_CR", prefix);
+ dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix);
+ dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix);
+ dump_phy_type(hw, low, 23, "25GBASE_SR", prefix);
+ dump_phy_type(hw, low, 24, "25GBASE_LR", prefix);
+ dump_phy_type(hw, low, 25, "25GBASE_KR", prefix);
+ dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix);
+ dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix);
+ dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix);
+ dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix);
+ dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix);
+ dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix);
+ dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix);
+ dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 35, "40G_XLAUI", prefix);
+ dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix);
+ dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix);
+ dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix);
+ dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix);
+ dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 41, "50G_LAUI2", prefix);
+ dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 43, "50G_AUI2", prefix);
+ dump_phy_type(hw, low, 44, "50GBASE_CP", prefix);
+ dump_phy_type(hw, low, 45, "50GBASE_SR", prefix);
+ dump_phy_type(hw, low, 46, "50GBASE_FR", prefix);
+ dump_phy_type(hw, low, 47, "50GBASE_LR", prefix);
+ dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix);
+ dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 50, "50G_AUI1", prefix);
+ dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix);
+ dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix);
+ dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix);
+ dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix);
+ dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 56, "100G_CAUI4", prefix);
+ dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix);
+ dump_phy_type(hw, low, 58, "100G_AUI4", prefix);
+ dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix);
+ dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix);
+ dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix);
+ dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix);
+ dump_phy_type(hw, low, 63, "100GBASE_DR", prefix);
+}
+
+/**
+ * ice_dump_phy_type_high - helper function to dump phy_type_high
+ * @hw: pointer to the HW structure
+ * @high: 64 bit value for phy_type_high
+ * @prefix: prefix string to differentiate multiple dumps
+ */
+static void
+ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix)
+{
+ ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix,
+ (unsigned long long)high);
+
+ dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix);
+ dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix);
+ dump_phy_type(hw, high, 2, "100G_CAUI2", prefix);
+ dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix);
+ dump_phy_type(hw, high, 4, "100G_AUI2", prefix);
+}
+
/**
* ice_set_mac_type - Sets MAC type
* @hw: pointer to the HW structure
@@ -180,6 +294,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
u16 pcaps_size = sizeof(*pcaps);
struct ice_aq_desc desc;
enum ice_status status;
+ const char *prefix;
struct ice_hw *hw;
cmd = &desc.params.get_phy;
@@ -200,29 +315,42 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
cmd->param0 |= CPU_TO_LE16(report_mode);
status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
- ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
- report_mode);
- ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
- (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
- ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
- (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));
- ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
- ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
+ ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
+
+ if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA)
+ prefix = "phy_caps_media";
+ else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA)
+ prefix = "phy_caps_no_media";
+ else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG)
+ prefix = "phy_caps_active";
+ else if (report_mode == ICE_AQC_REPORT_DFLT_CFG)
+ prefix = "phy_caps_default";
+ else
+ prefix = "phy_caps_invalid";
+
+ ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix);
+ ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix);
+
+ ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
+ prefix, report_mode);
+ ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
+ ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
pcaps->low_power_ctrl_an);
- ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
- ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
+ ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
+ pcaps->eee_cap);
+ ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
pcaps->eeer_value);
- ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
+ ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
pcaps->link_fec_options);
- ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
- pcaps->module_compliance_enforcement);
- ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
- pcaps->extended_compliance_code);
- ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
+ ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
+ prefix, pcaps->module_compliance_enforcement);
+ ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
+ prefix, pcaps->extended_compliance_code);
+ ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
pcaps->module_type[0]);
- ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
+ ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
pcaps->module_type[1]);
- ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
+ ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
pcaps->module_type[2]);
if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 09/28] net/ice/base: implement Vernier calibration logic for E822 devices
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (7 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:38 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 10/28] net/ice/base: clarify comments on checking PFC mode Qi Zhang
` (19 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
Move the implementation of Vernier calibration from Linux core ice_ptp.c
into the shared ice_ptp_hw.c file.
This implementation was recently refactored in Linux, so the move should
be verbatim with the latest Linux code that we had implemented.
This includes a new constant table with pre-determined values based on
link speed, new functions to aide in reading the multi-register values
from the PHY, functions to program the PAR/PCS conversion ratios, and
the UIX conversion ratios, functions to program the total Tx and Rx
offset after vernier calibration in the hardware completes, and finally
a function to start and stop the PHY timestamping block.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_consts.h | 216 ++++++
drivers/net/ice/base/ice_ptp_hw.c | 999 ++++++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 47 ++
3 files changed, 1262 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h
index 4583dd42ff..32eb60ab48 100644
--- a/drivers/net/ice/base/ice_ptp_consts.h
+++ b/drivers/net/ice/base/ice_ptp_consts.h
@@ -157,4 +157,220 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
},
};
+/* struct ice_vernier_info_e822
+ *
+ * E822 hardware calibrates the delay of the timestamp indication from the
+ * actual packet transmission or reception during the initialization of the
+ * PHY. To do this, the hardware mechanism uses some conversions between the
+ * various clocks within the PHY block. This table defines constants used to
+ * calculate the correct conversion ratios in the PHY registers.
+ *
+ * Many of the values relate to the PAR/PCS clock conversion registers. For
+ * these registers, a value of 0 means that the associated register is not
+ * used by this link speed, and that the register should be cleared by writing
+ * 0. Other values specify the clock frequency in Hz.
+ */
+const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
+ /* ICE_PTP_LNK_SPD_1G */
+ {
+ /* tx_par_clk */
+ 31250000, /* 31.25 MHz */
+ /* rx_par_clk */
+ 31250000, /* 31.25 MHz */
+ /* tx_pcs_clk */
+ 125000000, /* 125 MHz */
+ /* rx_pcs_clk */
+ 125000000, /* 125 MHz */
+ /* tx_desk_rsgb_par */
+ 0, /* unused */
+ /* rx_desk_rsgb_par */
+ 0, /* unused */
+ /* tx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* rx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* tx_fixed_delay */
+ 25140,
+ /* pmd_adj_divisor */
+ 10000000,
+ /* rx_fixed_delay */
+ 17372,
+ },
+ /* ICE_PTP_LNK_SPD_10G */
+ {
+ /* tx_par_clk */
+ 257812500, /* 257.8125 MHz */
+ /* rx_par_clk */
+ 257812500, /* 257.8125 MHz */
+ /* tx_pcs_clk */
+ 156250000, /* 156.25 MHz */
+ /* rx_pcs_clk */
+ 156250000, /* 156.25 MHz */
+ /* tx_desk_rsgb_par */
+ 0, /* unused */
+ /* rx_desk_rsgb_par */
+ 0, /* unused */
+ /* tx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* rx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* tx_fixed_delay */
+ 6938,
+ /* pmd_adj_divisor */
+ 82500000,
+ /* rx_fixed_delay */
+ 6212,
+ },
+ /* ICE_PTP_LNK_SPD_25G */
+ {
+ /* tx_par_clk */
+ 644531250, /* 644.53125 MHZ */
+ /* rx_par_clk */
+ 644531250, /* 644.53125 MHz */
+ /* tx_pcs_clk */
+ 390625000, /* 390.625 MHz */
+ /* rx_pcs_clk */
+ 390625000, /* 390.625 MHz */
+ /* tx_desk_rsgb_par */
+ 0, /* unused */
+ /* rx_desk_rsgb_par */
+ 0, /* unused */
+ /* tx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* rx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* tx_fixed_delay */
+ 2778,
+ /* pmd_adj_divisor */
+ 206250000,
+ /* rx_fixed_delay */
+ 2491,
+ },
+ /* ICE_PTP_LNK_SPD_25G_RS */
+ {
+ /* tx_par_clk */
+ 0, /* unused */
+ /* rx_par_clk */
+ 0, /* unused */
+ /* tx_pcs_clk */
+ 0, /* unused */
+ /* rx_pcs_clk */
+ 0, /* unused */
+ /* tx_desk_rsgb_par */
+ 161132812, /* 162.1328125 MHz Reed Solomon gearbox */
+ /* rx_desk_rsgb_par */
+ 161132812, /* 162.1328125 MHz Reed Solomon gearbox */
+ /* tx_desk_rsgb_pcs */
+ 97656250, /* 97.62625 MHz Reed Solomon gearbox */
+ /* rx_desk_rsgb_pcs */
+ 97656250, /* 97.62625 MHz Reed Solomon gearbox */
+ /* tx_fixed_delay */
+ 3928,
+ /* pmd_adj_divisor */
+ 206250000,
+ /* rx_fixed_delay */
+ 29535,
+ },
+ /* ICE_PTP_LNK_SPD_40G */
+ {
+ /* tx_par_clk */
+ 257812500,
+ /* rx_par_clk */
+ 257812500,
+ /* tx_pcs_clk */
+ 156250000, /* 156.25 MHz */
+ /* rx_pcs_clk */
+ 156250000, /* 156.25 MHz */
+ /* tx_desk_rsgb_par */
+ 0, /* unused */
+ /* rx_desk_rsgb_par */
+ 156250000, /* 156.25 MHz deskew clock */
+ /* tx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* rx_desk_rsgb_pcs */
+ 156250000, /* 156.25 MHz deskew clock */
+ /* tx_fixed_delay */
+ 5666,
+ /* pmd_adj_divisor */
+ 82500000,
+ /* rx_fixed_delay */
+ 4244,
+ },
+ /* ICE_PTP_LNK_SPD_50G */
+ {
+ /* tx_par_clk */
+ 644531250, /* 644.53125 MHZ */
+ /* rx_par_clk */
+ 644531250, /* 644.53125 MHZ */
+ /* tx_pcs_clk */
+ 390625000, /* 390.625 MHz */
+ /* rx_pcs_clk */
+ 390625000, /* 390.625 MHz */
+ /* tx_desk_rsgb_par */
+ 0, /* unused */
+ /* rx_desk_rsgb_par */
+ 195312500, /* 193.3125 MHz deskew clock */
+ /* tx_desk_rsgb_pcs */
+ 0, /* unused */
+ /* rx_desk_rsgb_pcs */
+ 195312500, /* 193.3125 MHz deskew clock */
+ /* tx_fixed_delay */
+ 2778,
+ /* pmd_adj_divisor */
+ 206250000,
+ /* rx_fixed_delay */
+ 2868,
+ },
+ /* ICE_PTP_LNK_SPD_50G_RS */
+ {
+ /* tx_par_clk */
+ 0, /* unused */
+ /* rx_par_clk */
+ 644531250, /* 644.53125 MHz */
+ /* tx_pcs_clk */
+ 0, /* unused */
+ /* rx_pcs_clk */
+ 644531250, /* 644.53125 MHz */
+ /* tx_desk_rsgb_par */
+ 322265625, /* 322.265625 MHz Reed Solomon gearbox */
+ /* rx_desk_rsgb_par */
+ 322265625, /* 322.265625 MHz Reed Solomon gearbox */
+ /* tx_desk_rsgb_pcs */
+ 644531250, /* 644.53125 MHz Reed Solomon gearbox */
+ /* rx_desk_rsgb_pcs */
+ 644531250, /* 644.53125 MHz Reed Solomon gearbox */
+ /* tx_fixed_delay */
+ 2095,
+ /* pmd_adj_divisor */
+ 206250000,
+ /* rx_fixed_delay */
+ 14524,
+ },
+ /* ICE_PTP_LNK_SPD_100G_RS */
+ {
+ /* tx_par_clk */
+ 0, /* unused */
+ /* rx_par_clk */
+ 644531250, /* 644.53125 MHz */
+ /* tx_pcs_clk */
+ 0, /* unused */
+ /* rx_pcs_clk */
+ 644531250, /* 644.53125 MHz */
+ /* tx_desk_rsgb_par */
+ 644531250, /* 644.53125 MHz Reed Solomon gearbox */
+ /* rx_desk_rsgb_par */
+ 644531250, /* 644.53125 MHz Reed Solomon gearbox */
+ /* tx_desk_rsgb_pcs */
+ 644531250, /* 644.53125 MHz Reed Solomon gearbox */
+ /* rx_desk_rsgb_pcs */
+ 644531250, /* 644.53125 MHz Reed Solomon gearbox */
+ /* tx_fixed_delay */
+ 1620,
+ /* pmd_adj_divisor */
+ 206250000,
+ /* rx_fixed_delay */
+ 7775,
+ },
+};
+
#endif /* _ICE_PTP_CONSTS_H_ */
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index cb32a4fb48..bf6889029a 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1573,6 +1573,1005 @@ void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
}
}
+/**
+ * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822
+ * @hw: pointer to the HW structure
+ * @port: the port to configure
+ *
+ * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
+ * hardware clock time units (TUs). That is, determine the number of TUs per
+ * serdes unit interval, and program the UIX registers with this conversion.
+ *
+ * This conversion is used as part of the calibration process when determining
+ * the additional error of a timestamp vs the real time of transmission or
+ * receipt of the packet.
+ *
+ * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
+ * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
+ *
+ * To calculate the conversion ratio, we use the following facts:
+ *
+ * a) the clock frequency in Hz (cycles per second)
+ * b) the number of TUs per cycle (the increment value of the clock)
+ * c) 1 second per 1 billion nanoseconds
+ * d) the duration of 66 UIs in nanoseconds
+ *
+ * Given these facts, we can use the following table to work out what ratios
+ * to multiply in order to get the number of TUs per 66 UIs:
+ *
+ * cycles | 1 second | incval (TUs) | nanoseconds
+ * -------+--------------+--------------+-------------
+ * second | 1 billion ns | cycle | 66 UIs
+ *
+ * To perform the multiplication using integers without too much loss of
+ * precision, we can take use the following equation:
+ *
+ * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
+ *
+ * We scale up to using 6600 UI instead of 66 in order to avoid fractional
+ * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
+ *
+ * The increment value has a maximum expected range of about 34 bits, while
+ * the frequency value is about 29 bits. Multiplying these values shouldn't
+ * overflow the 64 bits. However, we must then further multiply them again by
+ * the Serdes unit interval duration. To avoid overflow here, we split the
+ * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
+ * a divide by 390,625,000. This does lose some precision, but avoids
+ * miscalculation due to arithmetic overflow.
+ */
+static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
+{
+ u64 cur_freq, clk_incval, tu_per_sec, uix;
+ enum ice_status status;
+
+ cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
+ clk_incval = ice_ptp_read_src_incval(hw);
+
+ /* Calculate TUs per second divided by 256 */
+ tu_per_sec = (cur_freq * clk_incval) >> 8;
+
+#define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
+#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
+
+ /* Program the 10Gb/40Gb conversion ratio */
+ uix = (tu_per_sec * LINE_UI_10G_40G) / 390625000;
+
+ status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
+ uix);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, status %d\n",
+ status);
+ return status;
+ }
+
+ /* Program the 25Gb/100Gb conversion ratio */
+ uix = (tu_per_sec * LINE_UI_25G_100G) / 390625000;
+
+ status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
+ uix);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, status %d\n",
+ status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle
+ * @hw: pointer to the HW struct
+ * @port: port to configure
+ *
+ * Configure the number of TUs for the PAR and PCS clocks used as part of the
+ * timestamp calibration process. This depends on the link speed, as the PHY
+ * uses different markers depending on the speed.
+ *
+ * 1Gb/10Gb/25Gb:
+ * - Tx/Rx PAR/PCS markers
+ *
+ * 25Gb RS:
+ * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
+ *
+ * 40Gb/50Gb:
+ * - Tx/Rx PAR/PCS markers
+ * - Rx Deskew PAR/PCS markers
+ *
+ * 50G RS and 100GB RS:
+ * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
+ * - Rx Deskew PAR/PCS markers
+ * - Tx PAR/PCS markers
+ *
+ * To calculate the conversion, we use the PHC clock frequency (cycles per
+ * second), the increment value (TUs per cycle), and the related PHY clock
+ * frequency to calculate the TUs per unit of the PHY link clock. The
+ * following table shows how the units convert:
+ *
+ * cycles | TUs | second
+ * -------+-------+--------
+ * second | cycle | cycles
+ *
+ * For each conversion register, look up the appropriate frequency from the
+ * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
+ * this to the appropriate register, preparing hardware to perform timestamp
+ * calibration to calculate the total Tx or Rx offset to adjust the timestamp
+ * in order to calibrate for the internal PHY delays.
+ *
+ * Note that the increment value ranges up to ~34 bits, and the clock
+ * frequency is ~29 bits, so multiplying them together should fit within the
+ * 64 bit arithmetic.
+ */
+static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
+{
+ u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ enum ice_status status;
+
+ status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (status)
+ return status;
+
+ cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
+ clk_incval = ice_ptp_read_src_incval(hw);
+
+ /* Calculate TUs per cycle of the PHC clock */
+ tu_per_sec = cur_freq * clk_incval;
+
+ /* For each PHY conversion register, look up the appropriate link
+ * speed frequency and determine the TUs per that clock's cycle time.
+ * Split this into a high and low value and then program the
+ * appropriate register. If that link speed does not use the
+ * associated register, write zeros to clear it instead.
+ */
+
+ /* P_REG_PAR_TX_TUS */
+ if (e822_vernier[link_spd].tx_par_clk)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].tx_par_clk;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_PAR_RX_TUS */
+ if (e822_vernier[link_spd].rx_par_clk)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].rx_par_clk;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_PCS_TX_TUS */
+ if (e822_vernier[link_spd].tx_pcs_clk)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].tx_pcs_clk;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_PCS_RX_TUS */
+ if (e822_vernier[link_spd].rx_pcs_clk)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].rx_pcs_clk;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_DESK_PAR_TX_TUS */
+ if (e822_vernier[link_spd].tx_desk_rsgb_par)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_par;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_DESK_PAR_RX_TUS */
+ if (e822_vernier[link_spd].rx_desk_rsgb_par)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_par;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_DESK_PCS_TX_TUS */
+ if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_pcs;
+ else
+ phy_tus = 0;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,
+ phy_tus);
+ if (status)
+ return status;
+
+ /* P_REG_DESK_PCS_RX_TUS */
+ if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
+ phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_pcs;
+ else
+ phy_tus = 0;
+
+ return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L,
+ phy_tus);
+}
+
+/**
+ * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port
+ * @hw: pointer to the HW struct
+ * @link_spd: the Link speed to calculate for
+ *
+ * Calculate the fixed offset due to known static latency data.
+ */
+static u64
+ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
+{
+ u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
+
+ cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
+ clk_incval = ice_ptp_read_src_incval(hw);
+
+ /* Calculate TUs per second */
+ tu_per_sec = cur_freq * clk_incval;
+
+ /* Calculate number of TUs to add for the fixed Tx latency. Since the
+ * latency measurement is in 1/100th of a nanosecond, we need to
+ * multiply by tu_per_sec and then divide by 1e11. This calculation
+ * overflows 64 bit integer arithmetic, so break it up into two
+ * divisions by 1e4 first then by 1e7.
+ */
+ fixed_offset = tu_per_sec / 10000;
+ fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
+ fixed_offset /= 10000000;
+
+ return fixed_offset;
+}
+
+/**
+ * ice_phy_cfg_tx_offset_e822 - Configure total Tx timestamp offset
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
+ * adjust Tx timestamps by. This is calculated by combining some known static
+ * latency along with the Vernier offset computations done by hardware.
+ *
+ * This function must be called only after the offset registers are valid,
+ * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
+ * has measured the offset.
+ *
+ * To avoid overflow, when calculating the offset based on the known static
+ * latency values, we use measurements in 1/100th of a nanosecond, and divide
+ * the TUs per second up front. This avoids overflow while allowing
+ * calculation of the adjustment using integer arithmetic.
+ */
+enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ enum ice_status status;
+ u64 total_offset, val;
+
+ status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (status)
+ return status;
+
+ total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
+
+ /* Read the first Vernier offset from the PHY register and add it to
+ * the total offset.
+ */
+ if (link_spd == ICE_PTP_LNK_SPD_1G ||
+ link_spd == ICE_PTP_LNK_SPD_10G ||
+ link_spd == ICE_PTP_LNK_SPD_25G ||
+ link_spd == ICE_PTP_LNK_SPD_25G_RS ||
+ link_spd == ICE_PTP_LNK_SPD_40G ||
+ link_spd == ICE_PTP_LNK_SPD_50G) {
+ status = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_PCS_TX_OFFSET_L,
+ &val);
+ if (status)
+ return status;
+
+ total_offset += val;
+ }
+
+ /* For Tx, we only need to use the second Vernier offset for
+ * multi-lane link speeds with RS-FEC. The lanes will always be
+ * aligned.
+ */
+ if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
+ link_spd == ICE_PTP_LNK_SPD_100G_RS) {
+ status = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_TX_TIME_L,
+ &val);
+ if (status)
+ return status;
+
+ total_offset += val;
+ }
+
+ /* Now that the total offset has been calculated, program it to the
+ * PHY and indicate that the Tx offset is ready. After this,
+ * timestamps will be enabled.
+ */
+ status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
+ total_offset);
+ if (status)
+ return status;
+
+ status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
+ if (status)
+ return status;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Calculate and program the fixed Tx offset, and indicate that the offset is
+ * ready. This can be used when operating in bypass mode.
+ */
+static enum ice_status
+ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ enum ice_status status;
+ u64 total_offset;
+
+ status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (status)
+ return status;
+
+ total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
+
+ /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
+ * register, then indicate that the Tx offset is ready. After this,
+ * timestamps will be enabled.
+ *
+ * Note that this skips including the more precise offsets generated
+ * by the Vernier calibration.
+ */
+ status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
+ total_offset);
+ if (status)
+ return status;
+
+ status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
+ if (status)
+ return status;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to adjust for
+ * @link_spd: the current link speed of the PHY
+ * @fec_mode: the current FEC mode of the PHY
+ * @pmd_adj: on return, the amount to adjust the Rx total offset by
+ *
+ * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
+ * This varies by link speed and FEC mode. The value calculated accounts for
+ * various delays caused when receiving a packet.
+ */
+static enum ice_status
+ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
+ enum ice_ptp_link_spd link_spd,
+ enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
+{
+ u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
+ enum ice_status status;
+ u8 pmd_align;
+ u32 val;
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, status %d\n",
+ status);
+ return status;
+ }
+
+ pmd_align = (u8)val;
+
+ cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
+ clk_incval = ice_ptp_read_src_incval(hw);
+
+ /* Calculate TUs per second */
+ tu_per_sec = cur_freq * clk_incval;
+
+ /* The PMD alignment adjustment measurement depends on the link speed,
+ * and whether FEC is enabled. For each link speed, the alignment
+ * adjustment is calculated by dividing a value by the length of
+ * a Time Unit in nanoseconds.
+ *
+ * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
+ * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
+ * 10G w/FEC: align * 0.1 * 32/33
+ * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
+ * 25G w/FEC: align * 0.4 * 32/33
+ * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
+ * 40G w/FEC: align * 0.1 * 32/33
+ * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
+ * 50G w/FEC: align * 0.8 * 32/33
+ *
+ * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
+ *
+ * To allow for calculating this value using integer arithmetic, we
+ * instead start with the number of TUs per second, (inverse of the
+ * length of a Time Unit in nanoseconds), multiply by a value based
+ * on the PMD alignment register, and then divide by the right value
+ * calculated based on the table above. To avoid integer overflow this
+ * division is broken up into a step of dividing by 125 first.
+ */
+ if (link_spd == ICE_PTP_LNK_SPD_1G) {
+ if (pmd_align == 4)
+ mult = 10;
+ else
+ mult = (pmd_align + 6) % 10;
+ } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
+ link_spd == ICE_PTP_LNK_SPD_25G ||
+ link_spd == ICE_PTP_LNK_SPD_40G ||
+ link_spd == ICE_PTP_LNK_SPD_50G) {
+ /* If Clause 74 FEC, always calculate PMD adjust */
+ if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
+ mult = pmd_align;
+ else
+ mult = 0;
+ } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
+ link_spd == ICE_PTP_LNK_SPD_50G_RS ||
+ link_spd == ICE_PTP_LNK_SPD_100G_RS) {
+ if (pmd_align < 17)
+ mult = pmd_align + 40;
+ else
+ mult = pmd_align;
+ } else {
+ ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
+ link_spd);
+ mult = 0;
+ }
+
+ /* In some cases, there's no need to adjust for the PMD alignment */
+ if (!mult) {
+ *pmd_adj = 0;
+ return ICE_SUCCESS;
+ }
+
+ /* Calculate the adjustment by multiplying TUs per second by the
+ * appropriate multiplier and divisor. To avoid overflow, we first
+ * divide by 125, and then handle remaining divisor based on the link
+ * speed pmd_adj_divisor value.
+ */
+ adj = tu_per_sec / 125;
+ adj *= mult;
+ adj /= e822_vernier[link_spd].pmd_adj_divisor;
+
+ /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
+ * cycle count is necessary.
+ */
+ if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
+ u64 cycle_adj;
+ u8 rx_cycle;
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,
+ &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, status %d\n",
+ status);
+ return status;
+ }
+
+ rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
+ if (rx_cycle) {
+ mult = (4 - rx_cycle) * 40;
+
+ cycle_adj = tu_per_sec / 125;
+ cycle_adj *= mult;
+ cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
+
+ adj += cycle_adj;
+ }
+ } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
+ u64 cycle_adj;
+ u8 rx_cycle;
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,
+ &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, status %d\n",
+ status);
+ return status;
+ }
+
+ rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
+ if (rx_cycle) {
+ mult = rx_cycle * 40;
+
+ cycle_adj = tu_per_sec / 125;
+ cycle_adj *= mult;
+ cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
+
+ adj += cycle_adj;
+ }
+ }
+
+ /* Return the calculated adjustment */
+ *pmd_adj = adj;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port
+ * @hw: pointer to HW struct
+ * @link_spd: The Link speed to calculate for
+ *
+ * Determine the fixed Rx latency for a given link speed.
+ */
+static u64
+ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
+{
+ u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
+
+ cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
+ clk_incval = ice_ptp_read_src_incval(hw);
+
+ /* Calculate TUs per second */
+ tu_per_sec = cur_freq * clk_incval;
+
+ /* Calculate number of TUs to add for the fixed Rx latency. Since the
+ * latency measurement is in 1/100th of a nanosecond, we need to
+ * multiply by tu_per_sec and then divide by 1e11. This calculation
+ * overflows 64 bit integer arithmetic, so break it up into two
+ * divisions by 1e4 first then by 1e7.
+ */
+ fixed_offset = tu_per_sec / 10000;
+ fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
+ fixed_offset /= 10000000;
+
+ return fixed_offset;
+}
+
+/**
+ * ice_phy_cfg_rx_offset_e822 - Configure total Rx timestamp offset
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
+ * adjust Rx timestamps by. This combines calculations from the Vernier offset
+ * measurements taken in hardware with some data about known fixed delay as
+ * well as adjusting for multi-lane alignment delay.
+ *
+ * This function must be called only after the offset registers are valid,
+ * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
+ * has measured the offset.
+ *
+ * To avoid overflow, when calculating the offset based on the known static
+ * latency values, we use measurements in 1/100th of a nanosecond, and divide
+ * the TUs per second up front. This avoids overflow while allowing
+ * calculation of the adjustment using integer arithmetic.
+ */
+enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ u64 total_offset, pmd, val;
+ enum ice_status status;
+
+ status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (status)
+ return status;
+
+ total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
+
+ /* Read the first Vernier offset from the PHY register and add it to
+ * the total offset.
+ */
+ status = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_PCS_RX_OFFSET_L,
+ &val);
+ if (status)
+ return status;
+
+ total_offset += val;
+
+ /* For Rx, all multi-lane link speeds include a second Vernier
+ * calibration, because the lanes might not be aligned.
+ */
+ if (link_spd == ICE_PTP_LNK_SPD_40G ||
+ link_spd == ICE_PTP_LNK_SPD_50G ||
+ link_spd == ICE_PTP_LNK_SPD_50G_RS ||
+ link_spd == ICE_PTP_LNK_SPD_100G_RS) {
+ status = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_RX_TIME_L,
+ &val);
+ if (status)
+ return status;
+
+ total_offset += val;
+ }
+
+ /* In addition, Rx must account for the PMD alignment */
+ status = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd);
+ if (status)
+ return status;
+
+ /* For RS-FEC, this adjustment adds delay, but for other modes, it
+ * subtracts delay.
+ */
+ if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
+ total_offset += pmd;
+ else
+ total_offset -= pmd;
+
+ /* Now that the total offset has been calculated, program it to the
+ * PHY and indicate that the Rx offset is ready. After this,
+ * timestamps will be enabled.
+ */
+ status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
+ total_offset);
+ if (status)
+ return status;
+
+ status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
+ if (status)
+ return status;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Calculate and program the fixed Rx offset, and indicate that the offset is
+ * ready. This can be used when operating in bypass mode.
+ */
+static enum ice_status
+ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ enum ice_status status;
+ u64 total_offset;
+
+ status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (status)
+ return status;
+
+ total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
+
+ /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
+ * register, then indicate that the Rx offset is ready. After this,
+ * timestamps will be enabled.
+ *
+ * Note that this skips including the more precise offsets generated
+ * by Vernier calibration.
+ */
+ status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
+ total_offset);
+ if (status)
+ return status;
+
+ status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
+ if (status)
+ return status;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to read
+ * @phy_time: on return, the 64bit PHY timer value
+ * @phc_time: on return, the lower 64bits of PHC time
+ *
+ * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC
+ * timer values.
+ */
+static enum ice_status
+ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
+ u64 *phc_time)
+{
+ enum ice_status status;
+ u64 tx_time, rx_time;
+ u32 zo, lo;
+ u8 tmr_idx;
+
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+
+ /* Prepare the PHC timer for a READ_TIME capture command */
+ ice_ptp_src_cmd(hw, READ_TIME);
+
+ /* Prepare the PHY timer for a READ_TIME capture command */
+ status = ice_ptp_one_port_cmd(hw, port, READ_TIME, true);
+ if (status)
+ return status;
+
+ /* Issue the sync to start the READ_TIME capture */
+ ice_ptp_exec_tmr_cmd(hw);
+
+ /* Read the captured PHC time from the shadow time registers */
+ zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
+ lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
+ *phc_time = (u64)lo << 32 | zo;
+
+ /* Read the captured PHY time from the PHY shadow registers */
+ status = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
+ if (status)
+ return status;
+
+ /* If the PHY Tx and Rx timers don't match, log a warning message.
+ * Note that this should not happen in normal circumstances since the
+ * driver always programs them together.
+ */
+ if (tx_time != rx_time)
+ ice_warn(hw, "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
+ port, (unsigned long long)tx_time,
+ (unsigned long long)rx_time);
+
+ *phy_time = tx_time;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to synchronize
+ *
+ * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
+ * This is done by issuing a READ_TIME command which triggers a simultaneous
+ * read of the PHY timer and PHC timer. Then we use the difference to
+ * calculate an appropriate 2s complement addition to add to the PHY timer in
+ * order to ensure it reads the same value as the primary PHC timer.
+ */
+static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
+{
+ u64 phc_time, phy_time, difference;
+ enum ice_status status;
+
+ if (!ice_ptp_lock(hw)) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
+ return ICE_ERR_NOT_READY;
+ }
+
+ status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
+ if (status)
+ goto err_unlock;
+
+ /* Calculate the amount required to add to the port time in order for
+ * it to match the PHC time.
+ *
+ * Note that the port adjustment is done using 2s complement
+ * arithmetic. This is convenient since it means that we can simply
+ * calculate the difference between the PHC time and the port time,
+ * and it will be interpreted correctly.
+ */
+ difference = phc_time - phy_time;
+
+ status = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference, true);
+ if (status)
+ goto err_unlock;
+
+ status = ice_ptp_one_port_cmd(hw, port, ADJ_TIME, true);
+ if (status)
+ goto err_unlock;
+
+ /* Issue the sync to activate the time adjustment */
+ ice_ptp_exec_tmr_cmd(hw);
+
+ /* Re-capture the timer values to flush the command registers and
+ * verify that the time was properly adjusted.
+ */
+ status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
+ if (status)
+ goto err_unlock;
+
+ ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
+ port, (unsigned long long)phy_time,
+ (unsigned long long)phc_time);
+
+ ice_ptp_unlock(hw);
+
+ return ICE_SUCCESS;
+
+err_unlock:
+ ice_ptp_unlock(hw);
+ return status;
+}
+
+/**
+ * ice_stop_phy_timer_e822 - Stop the PHY clock timer
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to stop
+ * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
+ *
+ * Stop the clock of a PHY port. This must be done as part of the flow to
+ * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
+ * initialized or when link speed changes.
+ */
+enum ice_status
+ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
+{
+ enum ice_status status;
+ u32 val;
+
+ status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
+ if (status)
+ return status;
+
+ status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
+ if (status)
+ return status;
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
+ if (status)
+ return status;
+
+ val &= ~P_REG_PS_START_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ val &= ~P_REG_PS_ENA_CLK_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ if (soft_reset) {
+ val |= P_REG_PS_SFT_RESET_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+ }
+
+ ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_start_phy_timer_e822 - Start the PHY clock timer
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to start
+ * @bypass: if true, start the PHY in bypass mode
+ *
+ * Start the clock of a PHY port. This must be done as part of the flow to
+ * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
+ * initialized or when link speed changes.
+ *
+ * Bypass mode enables timestamps immediately without waiting for Vernier
+ * calibration to complete. Hardware will still continue taking Vernier
+ * measurements on Tx or Rx of packets, but they will not be applied to
+ * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware
+ * has completed offset calculation.
+ */
+enum ice_status
+ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
+{
+ enum ice_status status;
+ u32 lo, hi, val;
+ u64 incval;
+ u8 tmr_idx;
+
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+
+ status = ice_stop_phy_timer_e822(hw, port, false);
+ if (status)
+ return status;
+
+ ice_phy_cfg_lane_e822(hw, port);
+
+ status = ice_phy_cfg_uix_e822(hw, port);
+ if (status)
+ return status;
+
+ status = ice_phy_cfg_parpcs_e822(hw, port);
+ if (status)
+ return status;
+
+ lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
+ hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
+ incval = (u64)hi << 32 | lo;
+
+ status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
+ if (status)
+ return status;
+
+ status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
+ if (status)
+ return status;
+
+ ice_ptp_exec_tmr_cmd(hw);
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
+ if (status)
+ return status;
+
+ val |= P_REG_PS_SFT_RESET_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ val |= P_REG_PS_START_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ val &= ~P_REG_PS_SFT_RESET_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
+ if (status)
+ return status;
+
+ ice_ptp_exec_tmr_cmd(hw);
+
+ val |= P_REG_PS_ENA_CLK_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ val |= P_REG_PS_LOAD_OFFSET_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ ice_ptp_exec_tmr_cmd(hw);
+
+ status = ice_sync_phy_timer_e822(hw, port);
+ if (status)
+ return status;
+
+ if (bypass) {
+ val |= P_REG_PS_BYPASS_MODE_M;
+ /* Enter BYPASS mode, enabling timestamps immediately. */
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status)
+ return status;
+
+ /* Program the fixed Tx offset */
+ status = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
+ if (status)
+ return status;
+
+ /* Program the fixed Rx offset */
+ status = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
+ if (status)
+ return status;
+ }
+
+ ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
+
+ return ICE_SUCCESS;
+}
+
/* E810 functions
*
* The following functions operate on the E810 series devices which use
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index ad2349f60a..f2d87ca1e6 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -55,6 +55,44 @@ struct ice_time_ref_info_e822 {
u8 pps_delay;
};
+/**
+ * struct ice_vernier_info_e822
+ * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
+ * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
+ * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
+ * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
+ * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
+ * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
+ * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
+ * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
+ * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
+ * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
+ * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
+ *
+ * Table of constants used during as part of the Vernier calibration of the Tx
+ * and Rx timestamps. This includes frequency values used to compute TUs per
+ * PAR/PCS clock cycle, and static delay values measured during hardware
+ * design.
+ *
+ * Note that some values are not used for all link speeds, and the
+ * P_REG_DESK_PAR* registers may represent different clock markers at
+ * different link speeds, either the deskew marker for multi-lane link speeds
+ * or the Reed Solomon gearbox marker for RS-FEC.
+ */
+struct ice_vernier_info_e822 {
+ u32 tx_par_clk;
+ u32 rx_par_clk;
+ u32 tx_pcs_clk;
+ u32 rx_pcs_clk;
+ u32 tx_desk_rsgb_par;
+ u32 rx_desk_rsgb_par;
+ u32 tx_desk_rsgb_pcs;
+ u32 rx_desk_rsgb_pcs;
+ u32 tx_fixed_delay;
+ u32 pmd_adj_divisor;
+ u32 rx_fixed_delay;
+};
+
/**
* struct ice_cgu_pll_params_e822
* @refclk_pre_div: Reference clock pre-divisor
@@ -78,6 +116,9 @@ ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
/* Table of constants related to possible TIME_REF sources */
extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
+/* Table of constants for Vernier calibration on E822 */
+extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
+
/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
*/
@@ -171,6 +212,12 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
enum ice_ptp_link_spd *link_out,
enum ice_ptp_fec_mode *fec_out);
void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
+enum ice_status
+ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
+enum ice_status
+ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
+enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
+enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
/* E810 family functions */
enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 10/28] net/ice/base: clarify comments on checking PFC mode
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (8 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 09/28] net/ice/base: implement Vernier calibration logic for E822 devices Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:39 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode Qi Zhang
` (18 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Tony Nguyen
Rework the comment around checking PFC mode to make it clear why we are
checking the mode after sending the command.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_dcb.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 9c9675f6ef..cb6c5ba182 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -764,11 +764,10 @@ ice_aq_set_pfc_mode(struct ice_hw *hw, u8 pfc_mode, struct ice_sq_cd *cd)
if (status)
return status;
- /* The spec isn't clear about whether the FW will return an error code
- * if the PFC mode requested by the driver was not set. The spec just
- * says that the FW will write the PFC mode set back into cmd->pfc_mode,
- * so after the AQ has been executed, check if cmd->pfc_mode is what was
- * requested.
+ /* FW will write the PFC mode set back into cmd->pfc_mode, but if DCB is
+ * disabled, FW will write back 0 to cmd->pfc_mode. After the AQ has
+ * been executed, check if cmd->pfc_mode is what was requested. If not,
+ * return an error.
*/
if (cmd->pfc_mode != pfc_mode)
return ICE_ERR_NOT_SUPPORTED;
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (9 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 10/28] net/ice/base: clarify comments on checking PFC mode Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:39 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 12/28] net/ice/base: add E810T check function Qi Zhang
` (17 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
After starting the timestamping block, hardware begins calculating
precise offsets through a process of vernier calibration. This process
measures the effective phase offset of the various internal clocks used
in the PHY.
Once hardware completes these measurements, the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers are updated to indicate that the hardware
offset measurements are done.
This process does not happen immediately, but requires that at least one
packet be sent or received in order for the offset in that direction to
be calculated.
This poses a problem in some setups, because software expects the first
packet sent to be timestamped. This most often occurs if the clock time
is set by an application during startup. This set time command triggers
a PHY restart. Because of this, the timestamping block is reset, and
timestamps are not enabled until vernier calibration is complete. Since
this process won't complete until at least one packet is sent through
the PHY, timestamps of the very first packet sent will not be obtained.
This can result in the application failing due to missing timestamps.
To avoid this, allow starting the PHY in bypass mode. This mode enables
timestamps immediately, and skips adding the precise offset measurement.
This reduces the accuracy of the timestamp slightly, but ensures that we
get a reasonable value for the first packet.
The driver can continue monitoring the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers and exit bypass mode once the total
calibration is completed. In this way, once calibration is complete, the
timestamps will have the precise offset, but we do not break
applications which expect to be able to timestamp immediately.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 84 +++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 1 +
2 files changed, 85 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index bf6889029a..8ea75538fa 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2572,6 +2572,90 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
return ICE_SUCCESS;
}
+/**
+ * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * After hardware finishes vernier calculations for the Tx and Rx offset, this
+ * function can be used to exit bypass mode by updating the total Tx and Rx
+ * offsets, and then disabling bypass. This will enable hardware to include
+ * the more precise offset calibrations, increasing precision of the generated
+ * timestamps.
+ *
+ * This cannot be done until hardware has measured the offsets, which requires
+ * waiting until at least one packet has been sent and received by the device.
+ */
+enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_status status;
+ u32 val;
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+
+ if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
+ ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port %u\n",
+ port);
+ return ICE_ERR_NOT_READY;
+ }
+
+ status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+
+ if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
+ ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port %u\n",
+ port);
+ return ICE_ERR_NOT_READY;
+ }
+
+ status = ice_phy_cfg_tx_offset_e822(hw, port);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+
+ status = ice_phy_cfg_rx_offset_e822(hw, port);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+
+ /* Exit bypass mode now that the offset has been updated */
+ status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+
+ if (!(val & P_REG_PS_BYPASS_MODE_M))
+ ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n",
+ port);
+
+ val &= ~P_REG_PS_BYPASS_MODE_M;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+
+ ice_info(hw, "Exiting bypass mode on PHY port %u\n", port);
+
+ return ICE_SUCCESS;
+}
+
/* E810 functions
*
* The following functions operate on the E810 series devices which use
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index f2d87ca1e6..c804085095 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -218,6 +218,7 @@ enum ice_status
ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
+enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);
/* E810 family functions */
enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 12/28] net/ice/base: add E810T check function
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (10 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:39 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump Qi Zhang
` (16 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Michal Michalik
Add function ice_is_e810t() to be able to distinguish if hardware is E810T
based or not.
Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 12 ++++++++++++
drivers/net/ice/base/ice_common.h | 1 +
drivers/net/ice/base/ice_devids.h | 1 +
3 files changed, 14 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 2447d15b87..9cfff8930e 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -200,6 +200,18 @@ bool ice_is_e810(struct ice_hw *hw)
return hw->mac_type == ICE_MAC_E810;
}
+/**
+ * ice_is_e810t
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E810T based, false if not.
+ */
+bool ice_is_e810t(struct ice_hw *hw)
+{
+ return (hw->device_id == ICE_DEV_ID_E810C_SFP &&
+ hw->subsystem_device_id == ICE_SUBDEV_ID_E810T);
+}
+
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index de7592ba13..a18cccd8cb 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -237,6 +237,7 @@ enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
void ice_print_rollback_msg(struct ice_hw *hw);
bool ice_is_generic_mac(struct ice_hw *hw);
bool ice_is_e810(struct ice_hw *hw);
+bool ice_is_e810t(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_txsched_elem_data *buf);
diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h
index b4cdddc8e7..18397f1925 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -22,6 +22,7 @@
#define ICE_DEV_ID_E810C_QSFP 0x1592
/* Intel(R) Ethernet Controller E810-C for SFP */
#define ICE_DEV_ID_E810C_SFP 0x1593
+#define ICE_SUBDEV_ID_E810T 0x000E
/* Intel(R) Ethernet Controller E810-XXV for backplane */
#define ICE_DEV_ID_E810_XXV_BACKPLANE 0x1599
/* Intel(R) Ethernet Controller E810-XXV for QSFP */
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (11 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 12/28] net/ice/base: add E810T check function Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:40 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 14/28] net/ice/base: add new AQ description Qi Zhang
` (15 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Marcin Domagala
Basic implementation of FW Debug Dump.
Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 25 ++++++++++++++
drivers/net/ice/base/ice_common.c | 50 +++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 6 ++++
3 files changed, 81 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 74c4e8f120..7205fc6fbe 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2720,6 +2720,27 @@ struct ice_aqc_event_lan_overflow {
u8 reserved[8];
};
+/* Debug Dump Internal Data (indirect 0xFF08) */
+struct ice_aqc_debug_dump_internals {
+ u8 cluster_id;
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL 1
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
+/* EMP_DRAM only dumpable in device debug mode */
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
+/* AUX_REGS only dumpable in device debug mode */
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
+ u8 reserved;
+ __le16 table_id; /* Used only for non-memory clusters */
+ __le32 idx; /* In table entries for tables, in bytes for memory */
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
/* Set Health Status (direct 0xFF20) */
struct ice_aqc_set_health_status_config {
u8 event_source;
@@ -2894,6 +2915,7 @@ struct ice_aq_desc {
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_get_pkg_info_list get_pkg_info_list;
struct ice_aqc_driver_shared_params drv_shared_params;
+ struct ice_aqc_debug_dump_internals debug_dump;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_get_res_alloc get_res;
@@ -3161,6 +3183,9 @@ enum ice_adminq_opc {
/* Standalone Commands/Events */
ice_aqc_opc_event_lan_overflow = 0x1001,
+ /* debug commands */
+ ice_aqc_opc_debug_dump_internals = 0xFF08,
+
/* SystemDiagnostic commands */
ice_aqc_opc_set_health_status_config = 0xFF20,
ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 9cfff8930e..e98145bf3f 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4517,6 +4517,56 @@ ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
return ICE_SUCCESS;
}
+/**
+ * ice_aq_get_internal_data
+ * @hw: pointer to the hardware structure
+ * @cluster_id: specific cluster to dump
+ * @table_id: table ID within cluster
+ * @start: index of line in the block to read
+ * @buf: dump buffer
+ * @buf_size: dump buffer size
+ * @ret_buf_size: return buffer size (returned by FW)
+ * @ret_next_table: next block to read (returned by FW)
+ * @ret_next_index: next index to read (returned by FW)
+ * @cd: pointer to command details structure
+ *
+ * Get internal FW/HW data (0xFF08) for debug purposes.
+ */
+enum ice_status
+ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
+ u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
+ u16 *ret_next_table, u32 *ret_next_index,
+ struct ice_sq_cd *cd)
+{
+ struct ice_aqc_debug_dump_internals *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ cmd = &desc.params.debug_dump;
+
+ if (buf_size == 0 || !buf)
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals);
+
+ cmd->cluster_id = cluster_id;
+ cmd->table_id = CPU_TO_LE16(table_id);
+ cmd->idx = CPU_TO_LE32(start);
+
+ status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+ if (!status) {
+ if (ret_buf_size)
+ *ret_buf_size = LE16_TO_CPU(desc.datalen);
+ if (ret_next_table)
+ *ret_next_table = LE16_TO_CPU(cmd->table_id);
+ if (ret_next_index)
+ *ret_next_index = LE32_TO_CPU(cmd->idx);
+ }
+
+ return status;
+}
+
/**
* ice_read_byte - read context byte into struct
* @src_ctx: the context structure to read from
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index a18cccd8cb..770db8f40c 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -64,6 +64,12 @@ enum ice_status ice_get_caps(struct ice_hw *hw);
void ice_set_safe_mode_caps(struct ice_hw *hw);
+enum ice_status
+ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
+ u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
+ u16 *ret_next_table, u32 *ret_next_index,
+ struct ice_sq_cd *cd);
+
/* Define a macro that will align a pointer to point to the next memory address
* that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
* example, given the variable pointer = 0x1006, then after the following call:
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 14/28] net/ice/base: add new AQ description
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (12 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:40 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 15/28] net/ice/base: refine MAC rule adding Qi Zhang
` (14 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Siddaraju DH
Add ice_aqc_sw_gpio struct to ice_aq_desc
This change allows us to do SW_GPIO AQ cmd transactions
over ice_aq_send_cmd() interface.
Signed-off-by: Siddaraju DH <siddaraju.dh@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 7205fc6fbe..e9d6fcc3ad 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2860,6 +2860,7 @@ struct ice_aq_desc {
struct ice_aqc_i2c read_write_i2c;
struct ice_aqc_read_i2c_resp read_i2c_resp;
struct ice_aqc_gpio read_write_gpio;
+ struct ice_aqc_sw_gpio sw_read_write_gpio;
struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_sw_cfg get_sw_conf;
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 15/28] net/ice/base: refine MAC rule adding
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (13 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 14/28] net/ice/base: add new AQ description Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:41 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 16/28] net/ice/base: support TC nodes PIR configuration Qi Zhang
` (13 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Marcin Domagala
Move replay_pre_init function to interface.
Add further MAC rules, despite unicast address is already on list.
Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 2 +-
drivers/net/ice/base/ice_common.h | 2 ++
drivers/net/ice/base/ice_switch.c | 2 +-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index e98145bf3f..a77bf32b1c 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -5069,7 +5069,7 @@ static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
*
* Initializes required config data for VSI, FD, ACL, and RSS before replay.
*/
-static enum ice_status
+enum ice_status
ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
{
enum ice_status status;
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 770db8f40c..ac6b487347 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -221,6 +221,8 @@ enum ice_status
ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
struct ice_sq_cd *cd);
+enum ice_status
+ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw);
enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
void ice_replay_post(struct ice_hw *hw);
struct ice_q_ctx *
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 0b2347ba3a..2d8904d2c3 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4730,7 +4730,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
if (ice_find_rule_entry(rule_head,
&m_list_itr->fltr_info)) {
ice_release_lock(rule_lock);
- return ICE_ERR_ALREADY_EXISTS;
+ continue;
}
ice_release_lock(rule_lock);
num_unicast++;
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 16/28] net/ice/base: support TC nodes PIR configuration
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (14 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 15/28] net/ice/base: refine MAC rule adding Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:41 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet Qi Zhang
` (12 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Ting Xu
TC nodes CIR configuration is not supported. In order to configure PIR,
the corresponding adminq command should not include the flag for CIR.
Since the TC node info has this flag by default, it is supposed to delete
this flag for TC nodes before sending the adminq command.
Signed-off-by: Ting Xu <ting.xu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 544648cb84..2620892c9e 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -2945,6 +2945,9 @@ ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node,
u16 num_elems = 1;
buf = *info;
+ /* For TC nodes, CIR config is not supported */
+ if (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_TC)
+ buf.data.valid_sections &= ~ICE_AQC_ELEM_VALID_CIR;
/* Parent TEID is reserved field in this aq call */
buf.parent_teid = 0;
/* Element type is reserved field in this aq call */
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (15 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 16/28] net/ice/base: support TC nodes PIR configuration Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:41 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS " Qi Zhang
` (11 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Wenjun Wu
Support IPV4_GRE and IPV6_GRE with inner IPV4/IPV6/UDP/TCP for
FDIR.
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_fdir.c | 361 ++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_fdir.h | 2 +
drivers/net/ice/base/ice_type.h | 14 ++
3 files changed, 377 insertions(+)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 2e4770061d..e5ad0f298b 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -537,6 +537,183 @@ static const u8 ice_fdir_ipv4_frag_pkt[] = {
0x00, 0x00
};
+/* IPV4 GRE INNER IPV4 */
+static const u8 ice_fdir_ipv4_gre4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x2e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x9e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x16, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
+ 0x7c, 0xe5, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gre4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x36, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x96, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x1e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xcc, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x01, 0xd8, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gre4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x8a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
+ 0x7c, 0xcb, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x91, 0xde, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE INNER IPV6 */
+static const u8 ice_fdir_ipv6_gre4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x8a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x3b, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gre4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x82, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x0a, 0x11, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x0a, 0xff, 0xd8, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gre4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x76, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x16, 0x06, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x8f, 0xdf,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE INNER IPV4 */
+static const u8 ice_fdir_ipv4_gre6_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x18, 0x2F, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x14, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x00, 0x7A, 0xEA, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gre6_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x20, 0x2F, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x1C, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7A, 0xD1, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0xFF, 0xDE, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gre6_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x2C, 0x2F, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x28, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x06, 0x7A, 0xD0, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x8F, 0xE3,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE INNER IPV6 */
+static const u8 ice_fdir_ipv6_gre6_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x2C, 0x2F, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x86, 0xDD, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x3B, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gre6_pkt[] = {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x34, 0x2F, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x86, 0xDD, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x08,
+ 0xFF, 0x72, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gre6_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x40, 0x2F, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x86, 0xDD, 0x60, 0x00, 0x00, 0x00, 0x00, 0x14,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8F, 0xE1, 0x00, 0x00, 0x00, 0x00,
+};
+
static const u8 ice_fdir_tcpv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
@@ -1055,6 +1232,94 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_ipv4_udp_ecpri_tp0_pkt),
ice_fdir_ipv4_udp_ecpri_tp0_pkt,
},
+ /* IPV4 GRE INNER IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4,
+ sizeof(ice_fdir_ipv4_gre4_pkt),
+ ice_fdir_ipv4_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gre4_pkt),
+ ice_fdir_ipv4_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gre4_pkt),
+ ice_fdir_udp4_gre4_pkt,
+ sizeof(ice_fdir_udp4_gre4_pkt),
+ ice_fdir_udp4_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gre4_pkt),
+ ice_fdir_tcp4_gre4_pkt,
+ sizeof(ice_fdir_tcp4_gre4_pkt),
+ ice_fdir_tcp4_gre4_pkt,
+ },
+ /* IPV4 GRE INNER IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6,
+ sizeof(ice_fdir_ipv6_gre4_pkt),
+ ice_fdir_ipv6_gre4_pkt,
+ sizeof(ice_fdir_ipv6_gre4_pkt),
+ ice_fdir_ipv6_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gre4_pkt),
+ ice_fdir_udp6_gre4_pkt,
+ sizeof(ice_fdir_udp6_gre4_pkt),
+ ice_fdir_udp6_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gre4_pkt),
+ ice_fdir_tcp6_gre4_pkt,
+ sizeof(ice_fdir_tcp6_gre4_pkt),
+ ice_fdir_tcp6_gre4_pkt,
+ },
+ /* IPV6 GRE INNER IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4,
+ sizeof(ice_fdir_ipv4_gre6_pkt),
+ ice_fdir_ipv4_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gre6_pkt),
+ ice_fdir_ipv4_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gre6_pkt),
+ ice_fdir_udp4_gre6_pkt,
+ sizeof(ice_fdir_udp4_gre6_pkt),
+ ice_fdir_udp4_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gre6_pkt),
+ ice_fdir_tcp4_gre6_pkt,
+ sizeof(ice_fdir_tcp4_gre6_pkt),
+ ice_fdir_tcp4_gre6_pkt,
+ },
+ /* IPV4 GRE INNER IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6,
+ sizeof(ice_fdir_ipv6_gre6_pkt),
+ ice_fdir_ipv6_gre6_pkt,
+ sizeof(ice_fdir_ipv6_gre6_pkt),
+ ice_fdir_ipv6_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gre6_pkt),
+ ice_fdir_udp6_gre6_pkt,
+ sizeof(ice_fdir_udp6_gre6_pkt),
+ ice_fdir_udp6_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gre6_pkt),
+ ice_fdir_tcp6_gre6_pkt,
+ sizeof(ice_fdir_tcp6_gre6_pkt),
+ ice_fdir_tcp6_gre6_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt,
@@ -1523,6 +1788,28 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ICE_NONDMA_TO_NONDMA);
loc = &pkt[ICE_FDIR_GTPU_EH_INNER_PKT_OFF];
break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_TCP:
+ ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+ ice_fdir_pkt[idx].tun_pkt_len,
+ ICE_NONDMA_TO_NONDMA);
+ loc = &pkt[ICE_FDIR_IPV4_GRE_INNER_PKT_OFF];
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP:
+ ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+ ice_fdir_pkt[idx].tun_pkt_len,
+ ICE_NONDMA_TO_NONDMA);
+ loc = &pkt[ICE_FDIR_IPV6_GRE_INNER_PKT_OFF];
+ break;
default:
if (ice_fdir_get_open_tunnel_port(hw, flow, &tnl_port))
return ICE_ERR_DOES_NOT_EXIST;
@@ -1894,6 +2181,80 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_ECPRI_TP0_PC_ID_OFFSET,
input->ecpri_data.pc_id);
break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4:
+ ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v4.src_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v4.dst_ip);
+ ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET,
+ input->ip.v4.tos);
+ ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_PROTO_OFFSET,
+ input->ip.v4.proto);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_TCP:
+ ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v4.src_ip);
+ ice_pkt_insert_u16(loc, ICE_TCP4_NO_MAC_DST_PORT_OFFSET,
+ input->ip.v4.src_port);
+ ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v4.dst_ip);
+ ice_pkt_insert_u16(loc, ICE_TCP4_NO_MAC_SRC_PORT_OFFSET,
+ input->ip.v4.dst_port);
+ ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET,
+ input->ip.v4.tos);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_UDP:
+ ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v4.src_ip);
+ ice_pkt_insert_u16(loc, ICE_UDP4_NO_MAC_DST_PORT_OFFSET,
+ input->ip.v4.src_port);
+ ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v4.dst_ip);
+ ice_pkt_insert_u16(loc, ICE_UDP4_NO_MAC_SRC_PORT_OFFSET,
+ input->ip.v4.dst_port);
+ ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET,
+ input->ip.v4.tos);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET,
+ input->ip.v6.tc);
+ ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_PROTO_OFFSET,
+ input->ip.v6.proto);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_DST_PORT_OFFSET,
+ input->ip.v6.src_port);
+ ice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_SRC_PORT_OFFSET,
+ input->ip.v6.dst_port);
+ ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET,
+ input->ip.v6.tc);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_DST_PORT_OFFSET,
+ input->ip.v6.src_port);
+ ice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_SRC_PORT_OFFSET,
+ input->ip.v6.dst_port);
+ ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET,
+ input->ip.v6.tc);
+ break;
case ICE_FLTR_PTYPE_NONF_IPV6_TCP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index 1ba1084f38..a1147b4569 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -16,6 +16,8 @@
#define ICE_FDIR_GTPU_IP_INNER_PKT_OFF 50
#define ICE_FDIR_GTPU_EH_INNER_PKT_OFF 58
+#define ICE_FDIR_IPV4_GRE_INNER_PKT_OFF 38
+#define ICE_FDIR_IPV6_GRE_INNER_PKT_OFF 58
#define ICE_FDIR_TUN_PKT_OFF 50
#define ICE_FDIR_MAX_RAW_PKT_SIZE (512 + ICE_FDIR_TUN_PKT_OFF)
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2bd2318b13..f7aa5f6139 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -350,6 +350,20 @@ enum ice_fltr_ptype {
ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
ICE_FLTR_PTYPE_FRAG_IPV4,
ICE_FLTR_PTYPE_FRAG_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS for GRE tunnel packet
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (16 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:42 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner IPv6 Qi Zhang
` (10 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Wenjun Wu
Support RSS of inner headers for GRE tunnel packet.
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index b336275d0c..5b26d6c8b2 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -257,7 +257,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = {
* includes IPV4 other PTYPEs
*/
static const u32 ice_ptypes_ipv4_ofos_all[] = {
- 0x1D800000, 0x24000800, 0x00000000, 0x00000000,
+ 0x1D800000, 0x27BF7800, 0x00000000, 0x00000000,
0x00000000, 0x00000155, 0x00000000, 0x00000000,
0x00000000, 0x000FC000, 0x83E0FAA0, 0x00000101,
0x03FFD500, 0x00000000, 0x00000000, 0x00000000,
@@ -297,7 +297,7 @@ static const u32 ice_ptypes_ipv6_ofos[] = {
* includes IPV6 other PTYPEs
*/
static const u32 ice_ptypes_ipv6_ofos_all[] = {
- 0x00000000, 0x00000000, 0x76000000, 0x10002000,
+ 0x00000000, 0x00000000, 0x76000000, 0x1EFDE000,
0x00000000, 0x000002AA, 0x00000000, 0x00000000,
0x00000000, 0x03F00000, 0x7C1F0540, 0x00000206,
0xFC002A00, 0x0000003F, 0x00000000, 0x00000000,
@@ -807,7 +807,7 @@ struct ice_flow_prof_params {
ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \
ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \
ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \
- ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP)
+ ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE)
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
@@ -1024,11 +1024,9 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
} else if (hdrs & ICE_FLOW_SEG_HDR_GRE) {
- if (!i) {
- src = (const ice_bitmap_t *)ice_ptypes_gre_of;
- ice_and_bitmap(params->ptypes, params->ptypes,
- src, ICE_FLOW_PTYPE_MAX);
- }
+ src = (const ice_bitmap_t *)ice_ptypes_gre_of;
+ ice_and_bitmap(params->ptypes, params->ptypes, src,
+ ICE_FLOW_PTYPE_MAX);
} else if (hdrs & ICE_FLOW_SEG_HDR_GTPC) {
src = (const ice_bitmap_t *)ice_ptypes_gtpc;
ice_and_bitmap(params->ptypes, params->ptypes,
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner IPv6
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (17 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS " Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:43 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 20/28] net/ice/base: support RSS for GTPoGRE Qi Zhang
` (9 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang
Supuport FDIR filtering for IPV4_GTPU_EH_IPV6 with inner
IPV6/UDP/TCP fields matching.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_fdir.c | 352 ++++++++++++++++++++++++++------
drivers/net/ice/base/ice_type.h | 23 ++-
2 files changed, 309 insertions(+), 66 deletions(-)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index e5ad0f298b..ae512e5695 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -97,6 +97,54 @@ static const u8 ice_fdir_tcp4_gtpu4_pkt[] = {
0x00, 0x00, 0x00, 0x00,
};
+static const u8 ice_fdir_ipv6_gtpu4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
+ 0x24, 0x42, 0x30, 0xff, 0x00, 0x28, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x54, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x40,
+ 0x4e, 0x3d, 0x30, 0xff, 0x00, 0x30, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0xff, 0xdc, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4e,
+ 0x59, 0x08, 0x30, 0xff, 0x00, 0x3e, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
static const u8 ice_fdir_ipv4_gtpu4_eh_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
@@ -140,6 +188,57 @@ static const u8 ice_fdir_tcp4_gtpu4_eh_pkt[] = {
0x00, 0x00, 0x00, 0x00,
};
+static const u8 ice_fdir_ipv6_gtpu4_eh_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x1e, 0x9d, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x8c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4a,
+ 0x48, 0x9a, 0x34, 0xff, 0x00, 0x3a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0xff, 0xd8, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x80, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x56,
+ 0x53, 0x6b, 0x34, 0xff, 0x00, 0x46, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0xdf, 0x00, 0x00, 0x00, 0x00,
+};
+
static const u8 ice_fdir_ipv4_gtpu4_eh_dw_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
@@ -183,6 +282,57 @@ static const u8 ice_fdir_tcp4_gtpu4_eh_dw_pkt[] = {
0x00, 0x00, 0x00, 0x00,
};
+static const u8 ice_fdir_ipv6_gtpu4_eh_dw_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x1e, 0x9d, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_dw_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x8c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4a,
+ 0x48, 0x9a, 0x34, 0xff, 0x00, 0x3a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0xff, 0xd8, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_dw_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x80, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x56,
+ 0x53, 0x6b, 0x34, 0xff, 0x00, 0x46, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0xdf, 0x00, 0x00, 0x00, 0x00,
+};
+
static const u8 ice_fdir_ipv4_gtpu4_eh_up_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
@@ -226,67 +376,70 @@ static const u8 ice_fdir_tcp4_gtpu4_eh_up_pkt[] = {
0x00, 0x00, 0x00, 0x00,
};
-static const u8 ice_fdir_icmp4_gtpu4_pkt[] = {
+static const u8 ice_fdir_ipv6_gtpu4_eh_up_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
- 0x00, 0x4c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00,
- 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
- 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x01,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x1e, 0x8d, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
};
-static const u8 ice_fdir_ipv6_gtpu4_pkt[] = {
+static const u8 ice_fdir_udp6_gtpu4_eh_up_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
- 0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
- 0x7c, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
- 0x24, 0x42, 0x30, 0xff, 0x00, 0x28, 0x00, 0x00,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x5e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x8c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4a,
+ 0x48, 0x8a, 0x34, 0xff, 0x00, 0x3a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0xff, 0xd8, 0x00, 0x00,
};
-static const u8 ice_fdir_udp6_gtpu4_pkt[] = {
+static const u8 ice_fdir_tcp6_gtpu4_eh_up_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
- 0x00, 0x54, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
- 0x7c, 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x40,
- 0x4e, 0x3d, 0x30, 0xff, 0x00, 0x30, 0x00, 0x00,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,
- 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x6a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x80, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x56,
+ 0x53, 0x5b, 0x34, 0xff, 0x00, 0x46, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
- 0xff, 0xdc, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0xdf, 0x00, 0x00, 0x00, 0x00,
};
-static const u8 ice_fdir_tcp6_gtpu4_pkt[] = {
+static const u8 ice_fdir_icmp4_gtpu4_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
- 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
- 0x7c, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4e,
- 0x59, 0x08, 0x30, 0xff, 0x00, 0x3e, 0x00, 0x00,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
- 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x4c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00,
+ 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x01,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
- 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00,
};
static const u8 ice_fdir_ipv6_gtpu6_pkt[] = {
@@ -971,6 +1124,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_tcp4_gtpu4_pkt),
ice_fdir_tcp4_gtpu4_pkt,
},
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_pkt),
+ ice_fdir_ipv6_gtpu4_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_pkt),
+ ice_fdir_ipv6_gtpu4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_pkt),
+ ice_fdir_udp6_gtpu4_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_pkt),
+ ice_fdir_udp6_gtpu4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_pkt),
+ ice_fdir_tcp6_gtpu4_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_pkt),
+ ice_fdir_tcp6_gtpu4_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
sizeof(ice_fdir_ipv4_gtpu4_eh_pkt),
@@ -992,6 +1166,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_tcp4_gtpu4_eh_pkt),
ice_fdir_tcp4_gtpu4_eh_pkt,
},
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_pkt),
+ ice_fdir_ipv6_gtpu4_eh_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_pkt),
+ ice_fdir_ipv6_gtpu4_eh_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_pkt),
+ ice_fdir_udp6_gtpu4_eh_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_pkt),
+ ice_fdir_udp6_gtpu4_eh_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_pkt),
+ ice_fdir_tcp6_gtpu4_eh_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_pkt),
+ ice_fdir_tcp6_gtpu4_eh_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4,
sizeof(ice_fdir_ipv4_gtpu4_eh_dw_pkt),
@@ -1013,6 +1208,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_tcp4_gtpu4_eh_dw_pkt),
ice_fdir_tcp4_gtpu4_eh_dw_pkt,
},
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_dw_pkt),
+ ice_fdir_ipv6_gtpu4_eh_dw_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_dw_pkt),
+ ice_fdir_ipv6_gtpu4_eh_dw_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_dw_pkt),
+ ice_fdir_udp6_gtpu4_eh_dw_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_dw_pkt),
+ ice_fdir_udp6_gtpu4_eh_dw_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_dw_pkt),
+ ice_fdir_tcp6_gtpu4_eh_dw_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_dw_pkt),
+ ice_fdir_tcp6_gtpu4_eh_dw_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4,
sizeof(ice_fdir_ipv4_gtpu4_eh_up_pkt),
@@ -1034,6 +1250,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_tcp4_gtpu4_eh_up_pkt),
ice_fdir_tcp4_gtpu4_eh_up_pkt,
},
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_up_pkt),
+ ice_fdir_ipv6_gtpu4_eh_up_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_up_pkt),
+ ice_fdir_ipv6_gtpu4_eh_up_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_up_pkt),
+ ice_fdir_udp6_gtpu4_eh_up_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_up_pkt),
+ ice_fdir_udp6_gtpu4_eh_up_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_up_pkt),
+ ice_fdir_tcp6_gtpu4_eh_up_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_up_pkt),
+ ice_fdir_tcp6_gtpu4_eh_up_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
sizeof(ice_fdir_icmp4_gtpu4_pkt),
@@ -1048,27 +1285,6 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_ipv4_gtpu4_pkt),
ice_fdir_ipv4_gtpu4_pkt,
},
- {
- ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
- sizeof(ice_fdir_ipv6_gtpu4_pkt),
- ice_fdir_ipv6_gtpu4_pkt,
- sizeof(ice_fdir_ipv6_gtpu4_pkt),
- ice_fdir_ipv6_gtpu4_pkt,
- },
- {
- ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
- sizeof(ice_fdir_udp6_gtpu4_pkt),
- ice_fdir_udp6_gtpu4_pkt,
- sizeof(ice_fdir_udp6_gtpu4_pkt),
- ice_fdir_udp6_gtpu4_pkt,
- },
- {
- ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
- sizeof(ice_fdir_tcp6_gtpu4_pkt),
- ice_fdir_tcp6_gtpu4_pkt,
- sizeof(ice_fdir_tcp6_gtpu4_pkt),
- ice_fdir_tcp6_gtpu4_pkt,
- },
{
ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
sizeof(ice_fdir_ipv6_gtpu6_pkt),
@@ -1777,12 +1993,21 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP:
ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
ice_fdir_pkt[idx].tun_pkt_len,
ICE_NONDMA_TO_NONDMA);
@@ -2055,6 +2280,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);
break;
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
@@ -2065,6 +2293,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
input->ip.v6.proto);
break;
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
@@ -2077,6 +2308,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
break;
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index f7aa5f6139..b76404f085 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -306,28 +306,37 @@ enum ice_fltr_ptype {
ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU,
- ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH,
- ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW,
- ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP,
- ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
- ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH,
- ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW,
- ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 20/28] net/ice/base: support RSS for GTPoGRE
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (18 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner IPv6 Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:43 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities Qi Zhang
` (8 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang
Support RSS for GTPoGRE inner fields hash.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 8 ++++++++
drivers/net/ice/base/ice_flow.h | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 5b26d6c8b2..e41082b6ba 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -3483,6 +3483,14 @@ ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u8 seg_cnt,
segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV6 |
ICE_FLOW_SEG_HDR_IPV_FRAG |
ICE_FLOW_SEG_HDR_IPV_OTHER;
+ else if (cfg->hdr_type == ICE_RSS_INNER_HEADERS_W_OUTER_IPV4_GRE)
+ segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV4 |
+ ICE_FLOW_SEG_HDR_GRE |
+ ICE_FLOW_SEG_HDR_IPV_OTHER;
+ else if (cfg->hdr_type == ICE_RSS_INNER_HEADERS_W_OUTER_IPV6_GRE)
+ segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV6 |
+ ICE_FLOW_SEG_HDR_GRE |
+ ICE_FLOW_SEG_HDR_IPV_OTHER;
if (seg->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS &
~ICE_FLOW_RSS_HDRS_INNER_MASK & ~ICE_FLOW_SEG_HDR_IPV_OTHER &
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 878c79d19e..39408c5634 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -348,6 +348,10 @@ enum ice_rss_cfg_hdr_type {
/* take inner headers as inputset for packet with outer ipv6. */
ICE_RSS_INNER_HEADERS_W_OUTER_IPV6,
/* take outer headers first then inner headers as inputset */
+ /* take inner as inputset for GTPoGRE with outer ipv4 + gre. */
+ ICE_RSS_INNER_HEADERS_W_OUTER_IPV4_GRE,
+ /* take inner as inputset for GTPoGRE with outer ipv6 + gre. */
+ ICE_RSS_INNER_HEADERS_W_OUTER_IPV6_GRE,
ICE_RSS_ANY_HEADERS
};
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (19 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 20/28] net/ice/base: support RSS for GTPoGRE Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:43 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE Qi Zhang
` (7 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
Add logic to parse capabilities relating to the firmware update reset
requirements. This includes both capability 0x76, which informs the
driver if the firmware can sometimes skip PCIe resets, and 0x77, which
informs the driver if the firmware might potentially restrict EMP
resets.
For capability 0x76, if the number is 1, the firmware will report the
required reset level for a given update as part of its response to the
last command sent to program the NVM bank. (Otherwise, if the firmware
does not support this capability then it will always send a 0 in the
field of the response).
For capability 0x77, if the number is 1, the firmware will report when
EMP reset is available as part of the response to the command for
switching flash banks. (Otherwise, if the firmware does not support this
capability, it will always send a 0 in the field of the response
message).
These capabilities are required to implement immediate firmware
activation. If the capabilities are set, software can read the response
data and determine what reset level is required to activate the firmware
image. If only an EMP reset is required, and if the EMP reset is not
restricted by firmware, then the driver can issue an EMP reset to
immediately activate the new firmware.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 12 ++++++++++++
drivers/net/ice/base/ice_type.h | 4 ++++
2 files changed, 16 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index a77bf32b1c..2744c3d119 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2281,6 +2281,18 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
prefix, caps->max_mtu);
break;
+ case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
+ caps->pcie_reset_avoidance = (number > 0);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: pcie_reset_avoidance = %d\n", prefix,
+ caps->pcie_reset_avoidance);
+ break;
+ case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
+ caps->reset_restrict_support = (number == 1);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: reset_restrict_support = %d\n", prefix,
+ caps->reset_restrict_support);
+ break;
case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0:
case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1:
case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index b76404f085..6ae39a345b 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -480,6 +480,10 @@ struct ice_hw_common_caps {
#define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
#define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
+ /* PCIe reset avoidance */
+ bool pcie_reset_avoidance; /* false: not supported, true: supported */
+ /* Post update reset restriction */
+ bool reset_restrict_support; /* false: not supported, true: supported */
/* External topology device images within the NVM */
#define ICE_EXT_TOPO_DEV_IMG_COUNT 4
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (20 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:44 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4 checksum Qi Zhang
` (6 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang
Enable Flow Director filtering for GTPoGRE inner/outer fields
matching.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_fdir.c | 1532 ++++++++++++++++++++++
drivers/net/ice/base/ice_fdir.h | 12 +
drivers/net/ice/base/ice_flex_pipe.c | 6 +
drivers/net/ice/base/ice_flex_type.h | 48 +
drivers/net/ice/base/ice_flow.c | 184 ++-
drivers/net/ice/base/ice_protocol_type.h | 2 +
drivers/net/ice/base/ice_type.h | 112 ++
7 files changed, 1888 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index ae512e5695..d50f54a979 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -867,6 +867,966 @@ static const u8 ice_fdir_tcp6_gre6_pkt[] = {
0x20, 0x00, 0x8F, 0xE1, 0x00, 0x00, 0x00, 0x00,
};
+/* IPV4 GRE IPV4 GTPU IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x52, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x7a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xb0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x26,
+ 0xbf, 0xba, 0x30, 0xff, 0x00, 0x16, 0x00, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x72, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+ 0xbd, 0xc0, 0x30, 0xff, 0x00, 0x1e, 0x00, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x66, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x66, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x9c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x3a,
+ 0xbd, 0x9d, 0x30, 0xff, 0x00, 0x2a, 0x00, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0x7a,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x66, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x66, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x9c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x3a,
+ 0x24, 0x3a, 0x30, 0xff, 0x00, 0x2a, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x4e, 0x37, 0x30, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x7a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x52, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x88, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4e,
+ 0x59, 0x08, 0x30, 0xff, 0x00, 0x3e, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x3e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x3a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xb0, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x26, 0xbf, 0xba, 0x30, 0xff,
+ 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x16, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
+ 0x7c, 0xe5, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x46, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x42, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa8, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x2e, 0xbd, 0xc0, 0x30, 0xff,
+ 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x1e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xcc, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x52, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x4e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x9c, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x3a, 0xbd, 0x9d, 0x30, 0xff,
+ 0x00, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
+ 0x7c, 0xcb, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x91, 0x7a, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x52, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x4e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x9c, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x3a, 0x24, 0x3a, 0x30, 0xff,
+ 0x00, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x3b, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0x4e, 0x37, 0x30, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x0a, 0x11, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x66, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x62, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x88, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x4e, 0x59, 0x08, 0x30, 0xff,
+ 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x16, 0x06, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x8f, 0x7b,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU EH IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_eh_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x72, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+ 0xba, 0x1d, 0x34, 0xff, 0x00, 0x1e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_eh_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x6a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x36,
+ 0xb8, 0x23, 0x34, 0xff, 0x00, 0x26, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_eh_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0xb8, 0x00, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0x7a,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU EH IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_eh_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x1e, 0x9d, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x76, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x56, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x8c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4a,
+ 0x48, 0x9a, 0x34, 0xff, 0x00, 0x3a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x82, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x4a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x80, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x56,
+ 0x53, 0x6b, 0x34, 0xff, 0x00, 0x46, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU EH IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_eh_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x46, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x42, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa8, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x2e, 0xba, 0x1d, 0x34, 0xff,
+ 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x16, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
+ 0x7c, 0xe5, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_eh_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x4e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x4a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa0, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x36, 0xb8, 0x23, 0x34, 0xff,
+ 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x1e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xcc, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_eh_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0xb8, 0x00, 0x34, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
+ 0x7c, 0xcb, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x91, 0x7a, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU EH IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_eh_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0x1e, 0x9d, 0x34, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x3b, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x62, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x5e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x8c, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x4a, 0x48, 0x9a, 0x34, 0xff,
+ 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x0a, 0x11, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x6e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x6a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x80, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x56, 0x53, 0x6b, 0x34, 0xff,
+ 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x16, 0x06, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x8f, 0x7b,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU DW IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x72, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+ 0xba, 0x1d, 0x34, 0xff, 0x00, 0x1e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_eh_dw_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x6a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x36,
+ 0xb8, 0x23, 0x34, 0xff, 0x00, 0x26, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_eh_dw_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0xb8, 0x00, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0x7a,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU DW IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_eh_dw_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x1e, 0x9d, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_dw_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x76, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x56, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x8c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4a,
+ 0x48, 0x9a, 0x34, 0xff, 0x00, 0x3a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_dw_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x82, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x4a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x80, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x56,
+ 0x53, 0x6b, 0x34, 0xff, 0x00, 0x46, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU DW IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x46, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x42, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa8, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x2e, 0xba, 0x1d, 0x34, 0xff,
+ 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x16, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
+ 0x7c, 0xe5, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_eh_dw_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x4e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x4a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa0, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x36, 0xb8, 0x23, 0x34, 0xff,
+ 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x1e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xcc, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_eh_dw_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0xb8, 0x00, 0x34, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
+ 0x7c, 0xcb, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x91, 0x7a, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU DW IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_eh_dw_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0x1e, 0x9d, 0x34, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x3b, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_dw_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x62, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x5e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x8c, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x4a, 0x48, 0x9a, 0x34, 0xff,
+ 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x0a, 0x11, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_dw_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x6e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x6a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x80, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x56, 0x53, 0x6b, 0x34, 0xff,
+ 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x16, 0x06, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x8f, 0x7b,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU UP IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x72, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+ 0xba, 0x0d, 0x34, 0xff, 0x00, 0x1e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_eh_up_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x6a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x36,
+ 0xb8, 0x13, 0x34, 0xff, 0x00, 0x26, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_eh_up_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0xb7, 0xf0, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0x7a,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 GRE IPV4 GTPU UP IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_eh_up_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x5e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+ 0x1e, 0x8d, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_up_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x76, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x56, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x8c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4a,
+ 0x48, 0x8a, 0x34, 0xff, 0x00, 0x3a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_up_gre4_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x82, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f,
+ 0x7c, 0x4a, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x6a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x80, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x56,
+ 0x53, 0x5b, 0x34, 0xff, 0x00, 0x46, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+ 0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU UP IPV4 */
+static const u8 ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x46, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x42, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa8, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x2e, 0xba, 0x0d, 0x34, 0xff,
+ 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x10, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x16, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
+ 0x7c, 0xe5, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp4_gtpu4_eh_up_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x4e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x4a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0xa0, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x36, 0xb8, 0x13, 0x34, 0xff,
+ 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x10, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x1e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xcc, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a,
+ 0x01, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp4_gtpu4_eh_up_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0xb7, 0xf0, 0x34, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x10, 0x00, 0x00, 0x45, 0x00,
+ 0x00, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
+ 0x7c, 0xcb, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+ 0x20, 0x00, 0x91, 0x7a, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV6 GRE IPV4 GTPU UP IPV6 */
+static const u8 ice_fdir_ipv6_gtpu4_eh_up_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x5a, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x56, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x94, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x42, 0x1e, 0x8d, 0x34, 0xff,
+ 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x10, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x3b, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_eh_up_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x62, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x5e, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x8c, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x4a, 0x48, 0x8a, 0x34, 0xff,
+ 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x10, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x0a, 0x11, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x35,
+ 0x00, 0x35, 0x00, 0x0a, 0xff, 0x6e, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_eh_up_gre6_pkt[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x6e, 0x2f, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x08, 0x00, 0x45, 0x00, 0x00, 0x6a, 0x00, 0x01,
+ 0x00, 0x00, 0x40, 0x11, 0x7c, 0x80, 0x7f, 0x00,
+ 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x08, 0x68,
+ 0x08, 0x68, 0x00, 0x56, 0x53, 0x5b, 0x34, 0xff,
+ 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x85, 0x01, 0x10, 0x00, 0x00, 0x60, 0x00,
+ 0x00, 0x00, 0x00, 0x16, 0x06, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x14,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x8f, 0x7b,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
static const u8 ice_fdir_tcpv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
@@ -1103,6 +2063,70 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_ipv4_gtpu4_eh_up_pkt),
ice_fdir_ipv4_gtpu4_eh_up_pkt,
},
+ /* IPV4 GRE IPV4 GTPU */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU,
+ sizeof(ice_fdir_ipv4_gtpu4_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU EH */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU DW */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU UP */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU,
+ sizeof(ice_fdir_ipv4_gtpu4_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU EH */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU DW */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU UP */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
sizeof(ice_fdir_ipv4_gtpu4_pkt),
@@ -1536,6 +2560,358 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
sizeof(ice_fdir_tcp6_gre6_pkt),
ice_fdir_tcp6_gre6_pkt,
},
+ /* IPV4 GRE IPV4 GTPU IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_gre4_pkt),
+ ice_fdir_udp4_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_gre4_pkt),
+ ice_fdir_udp4_gtpu4_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_gre4_pkt),
+ ice_fdir_udp6_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_gre4_pkt),
+ ice_fdir_udp6_gtpu4_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_gre4_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_gre4_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_gre6_pkt),
+ ice_fdir_udp4_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_gre6_pkt),
+ ice_fdir_udp4_gtpu4_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_gre6_pkt),
+ ice_fdir_udp6_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_gre6_pkt),
+ ice_fdir_udp6_gtpu4_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_gre6_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_gre6_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU EH IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_eh_gre4_pkt),
+ ice_fdir_udp4_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_eh_gre4_pkt),
+ ice_fdir_udp4_gtpu4_eh_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_eh_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU EH IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_eh_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_gre4_pkt),
+ ice_fdir_udp6_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_gre4_pkt),
+ ice_fdir_udp6_gtpu4_eh_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_eh_gre4_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_eh_gre4_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU EH IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_eh_gre6_pkt),
+ ice_fdir_udp4_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_eh_gre6_pkt),
+ ice_fdir_udp4_gtpu4_eh_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_eh_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU EH IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_eh_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_gre6_pkt),
+ ice_fdir_udp6_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_gre6_pkt),
+ ice_fdir_udp6_gtpu4_eh_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_eh_gre6_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_eh_gre6_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU DW IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_udp4_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_udp4_gtpu4_eh_dw_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_eh_dw_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU DW IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_eh_dw_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_udp6_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_udp6_gtpu4_eh_dw_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_eh_dw_gre4_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_dw_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_eh_dw_gre4_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU DW IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_dw_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_udp4_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_udp4_gtpu4_eh_dw_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_eh_dw_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU DW IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_eh_dw_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_udp6_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_udp6_gtpu4_eh_dw_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_eh_dw_gre6_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_dw_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_eh_dw_gre6_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU UP IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_udp4_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_udp4_gtpu4_eh_up_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_tcp4_gtpu4_eh_up_gre4_pkt,
+ },
+ /* IPV4 GRE IPV4 GTPU UP IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_ipv6_gtpu4_eh_up_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_udp6_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_udp6_gtpu4_eh_up_gre4_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_eh_up_gre4_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_up_gre4_pkt),
+ ice_fdir_tcp6_gtpu4_eh_up_gre4_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU UP IPV4 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_ipv4_gtpu4_eh_up_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
+ sizeof(ice_fdir_udp4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_udp4_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_udp4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_udp4_gtpu4_eh_up_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_tcp4_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_tcp4_gtpu4_eh_up_gre6_pkt,
+ },
+ /* IPV6 GRE IPV4 GTPU UP IPV6 */
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_ipv6_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_ipv6_gtpu4_eh_up_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
+ sizeof(ice_fdir_udp6_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_udp6_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_udp6_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_udp6_gtpu4_eh_up_gre6_pkt,
+ },
+ {
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_eh_up_gre6_pkt,
+ sizeof(ice_fdir_tcp6_gtpu4_eh_up_gre6_pkt),
+ ice_fdir_tcp6_gtpu4_eh_up_gre6_pkt,
+ },
{
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt,
@@ -2035,6 +3411,74 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ICE_NONDMA_TO_NONDMA);
loc = &pkt[ICE_FDIR_IPV6_GRE_INNER_PKT_OFF];
break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_TCP:
+ ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+ ice_fdir_pkt[idx].tun_pkt_len,
+ ICE_NONDMA_TO_NONDMA);
+ loc = &pkt[ICE_FDIR_V4_V4_GTPOGRE_PKT_OFF];
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_TCP:
+ ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+ ice_fdir_pkt[idx].tun_pkt_len,
+ ICE_NONDMA_TO_NONDMA);
+ loc = &pkt[ICE_FDIR_V6_V4_GTPOGRE_PKT_OFF];
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_TCP:
+ ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+ ice_fdir_pkt[idx].tun_pkt_len,
+ ICE_NONDMA_TO_NONDMA);
+ loc = &pkt[ICE_FDIR_V4_V4_GTPOGRE_EH_PKT_OFF];
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_TCP:
+ ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+ ice_fdir_pkt[idx].tun_pkt_len,
+ ICE_NONDMA_TO_NONDMA);
+ loc = &pkt[ICE_FDIR_V6_V4_GTPOGRE_EH_PKT_OFF];
+ break;
default:
if (ice_fdir_get_open_tunnel_port(hw, flow, &tnl_port))
return ICE_ERR_DOES_NOT_EXIST;
@@ -2228,6 +3672,14 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4:
ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
@@ -2249,10 +3701,38 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET,
input->gtpu_data.qfi);
break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU:
+ ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
+ input->ip.v4.src_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
+ input->ip.v4.dst_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_GTPOGRE_TEID_OFFSET,
+ input->gtpu_data.teid);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP:
+ ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
+ input->ip.v4.src_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
+ input->ip.v4.dst_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_GTPOGRE_TEID_OFFSET,
+ input->gtpu_data.teid);
+ ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPOGRE_QFI_OFFSET,
+ input->gtpu_data.qfi);
+ break;
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_UDP:
ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u16(loc, ICE_UDP4_NO_MAC_DST_PORT_OFFSET,
@@ -2268,6 +3748,14 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_TCP:
ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u16(loc, ICE_TCP4_NO_MAC_DST_PORT_OFFSET,
@@ -2283,6 +3771,14 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
@@ -2296,6 +3792,14 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_UDP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_UDP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
@@ -2311,6 +3815,14 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_TCP:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_TCP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
@@ -2344,6 +3856,26 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
ice_pkt_insert_u6_qfi(loc, ICE_IPV6_GTPU_QFI_OFFSET,
input->gtpu_data.qfi);
break;
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV6_GTPOGRE_TEID_OFFSET,
+ input->gtpu_data.teid);
+ break;
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW:
+ case ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP:
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
+ input->ip.v6.src_ip);
+ ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET,
+ input->ip.v6.dst_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV6_GTPOGRE_TEID_OFFSET,
+ input->gtpu_data.teid);
+ ice_pkt_insert_u6_qfi(loc, ICE_IPV6_GTPOGRE_QFI_OFFSET,
+ input->gtpu_data.qfi);
+ break;
case ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3:
ice_pkt_insert_u32(loc, ICE_IPV4_L2TPV3_SESS_ID_OFFSET,
input->l2tpv3_data.session_id);
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index a1147b4569..b6325a3b1b 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -18,6 +18,14 @@
#define ICE_FDIR_GTPU_EH_INNER_PKT_OFF 58
#define ICE_FDIR_IPV4_GRE_INNER_PKT_OFF 38
#define ICE_FDIR_IPV6_GRE_INNER_PKT_OFF 58
+#define ICE_FDIR_V4_V4_GTPOGRE_PKT_OFF 74
+#define ICE_FDIR_V4_V6_GTPOGRE_PKT_OFF 94
+#define ICE_FDIR_V6_V4_GTPOGRE_PKT_OFF 94
+#define ICE_FDIR_V6_V6_GTPOGRE_PKT_OFF 114
+#define ICE_FDIR_V4_V4_GTPOGRE_EH_PKT_OFF 82
+#define ICE_FDIR_V4_V6_GTPOGRE_EH_PKT_OFF 102
+#define ICE_FDIR_V6_V4_GTPOGRE_EH_PKT_OFF 102
+#define ICE_FDIR_V6_V6_GTPOGRE_EH_PKT_OFF 122
#define ICE_FDIR_TUN_PKT_OFF 50
#define ICE_FDIR_MAX_RAW_PKT_SIZE (512 + ICE_FDIR_TUN_PKT_OFF)
@@ -73,6 +81,10 @@
#define ICE_IPV4_GTPU_QFI_OFFSET 56
#define ICE_IPV6_GTPU_TEID_OFFSET 66
#define ICE_IPV6_GTPU_QFI_OFFSET 76
+#define ICE_IPV4_GTPOGRE_TEID_OFFSET 70
+#define ICE_IPV4_GTPOGRE_QFI_OFFSET 80
+#define ICE_IPV6_GTPOGRE_TEID_OFFSET 90
+#define ICE_IPV6_GTPOGRE_QFI_OFFSET 100
#define ICE_IPV4_L2TPV3_SESS_ID_OFFSET 34
#define ICE_IPV6_L2TPV3_SESS_ID_OFFSET 54
#define ICE_IPV4_ESP_SPI_OFFSET 34
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index b3cea731f3..fd98b3837d 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4712,12 +4712,18 @@ static const struct ice_fd_src_dst_pair ice_fd_pairs[] = {
{ ICE_PROT_IPV4_IL, 2, 12 },
{ ICE_PROT_IPV4_IL, 2, 16 },
+ { ICE_PROT_IPV4_IL_IL, 2, 12 },
+ { ICE_PROT_IPV4_IL_IL, 2, 16 },
+
{ ICE_PROT_IPV6_OF_OR_S, 8, 8 },
{ ICE_PROT_IPV6_OF_OR_S, 8, 24 },
{ ICE_PROT_IPV6_IL, 8, 8 },
{ ICE_PROT_IPV6_IL, 8, 24 },
+ { ICE_PROT_IPV6_IL_IL, 8, 8 },
+ { ICE_PROT_IPV6_IL_IL, 8, 24 },
+
{ ICE_PROT_TCP_IL, 1, 0 },
{ ICE_PROT_TCP_IL, 1, 2 },
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 8d2ba991e1..eb8290713b 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -446,6 +446,54 @@ enum ice_sect {
#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_TCP 419
#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_SCTP 420
#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_ICMPV6 421
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_FRAG 450
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_PAY 451
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_UDP_PAY 452
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_TCP 453
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_SCTP 454
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_ICMP 455
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV6_FRAG 456
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV6_PAY 457
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV6_UDP_PAY 458
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV6_TCP 459
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV6_SCTP 460
+#define MAC_IPV4_TUN_IPV4_GTPU_IPV6_ICMPV6 461
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV4_FRAG 462
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV4_PAY 463
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV4_UDP_PAY 464
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV4_TCP 465
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV4_SCTP 466
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV4_ICMP 467
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV6_FRAG 468
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV6_PAY 469
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV6_UDP_PAY 470
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV6_TCP 471
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV6_SCTP 472
+#define MAC_IPV4_TUN_IPV6_GTPU_IPV6_ICMPV6 473
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV4_FRAG 474
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV4_PAY 475
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV4_UDP_PAY 476
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV4_TCP 477
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV4_SCTP 478
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV4_ICMP 479
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV6_FRAG 480
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV6_PAY 481
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV6_UDP_PAY 482
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV6_TCP 483
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV6_SCTP 484
+#define MAC_IPV6_TUN_IPV4_GTPU_IPV6_ICMPV6 485
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV4_FRAG 486
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV4_PAY 487
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV4_UDP_PAY 488
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV4_TCP 489
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV4_SCTP 490
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV4_ICMP 491
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV6_FRAG 492
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV6_PAY 493
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV6_UDP_PAY 494
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV6_TCP 495
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV6_SCTP 496
+#define MAC_IPV6_TUN_IPV6_GTPU_IPV6_ICMPV6 497
/* Attributes that can modify PTYPE definitions.
*
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index e41082b6ba..0b7d087c83 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -260,7 +260,7 @@ static const u32 ice_ptypes_ipv4_ofos_all[] = {
0x1D800000, 0x27BF7800, 0x00000000, 0x00000000,
0x00000000, 0x00000155, 0x00000000, 0x00000000,
0x00000000, 0x000FC000, 0x83E0FAA0, 0x00000101,
- 0x03FFD500, 0x00000000, 0x00000000, 0x00000000,
+ 0x03FFD000, 0x00000000, 0x02FBEFBC, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -272,7 +272,7 @@ static const u32 ice_ptypes_ipv4_il[] = {
0xE0000000, 0xB807700E, 0x80000003, 0xE01DC03B,
0x0000000E, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x001FF800, 0x00100000,
- 0xFC0FC000, 0x00000000, 0x00000000, 0x00000000,
+ 0xFC0FC000, 0x00000000, 0xBC0BC0BC, 0x00000BC0,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -300,7 +300,7 @@ static const u32 ice_ptypes_ipv6_ofos_all[] = {
0x00000000, 0x00000000, 0x76000000, 0x1EFDE000,
0x00000000, 0x000002AA, 0x00000000, 0x00000000,
0x00000000, 0x03F00000, 0x7C1F0540, 0x00000206,
- 0xFC002A00, 0x0000003F, 0x00000000, 0x00000000,
+ 0xFC002000, 0x0000003F, 0xBC000000, 0x0002FBEF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -312,7 +312,7 @@ static const u32 ice_ptypes_ipv6_il[] = {
0x00000000, 0x03B80770, 0x000001DC, 0x0EE00000,
0x00000770, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x7FE00000, 0x00000000,
- 0x03F00000, 0x0000003F, 0x00000000, 0x00000000,
+ 0x03F00000, 0x0000003F, 0x02F02F00, 0x0002F02F,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -390,7 +390,7 @@ static const u32 ice_ptypes_udp_il[] = {
0x81000000, 0x20204040, 0x04000010, 0x80810102,
0x00000040, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00410000, 0x908427E0, 0x00100007,
- 0x10410000, 0x00000004, 0x00000000, 0x00000000,
+ 0x10410000, 0x00000004, 0x10410410, 0x00004104,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -402,7 +402,7 @@ static const u32 ice_ptypes_tcp_il[] = {
0x04000000, 0x80810102, 0x10000040, 0x02040408,
0x00000102, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00820000, 0x21084000, 0x00000000,
- 0x20820000, 0x00000008, 0x00000000, 0x00000000,
+ 0x20820000, 0x00000008, 0x20820820, 0x00008208,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -450,7 +450,7 @@ static const u32 ice_ptypes_gre_of[] = {
0x00000000, 0xBFBF7800, 0x000001DF, 0xFEFDE000,
0x0000017E, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xBEFBEFBC, 0x0002FBEF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -527,6 +527,46 @@ static const struct ice_ptype_attributes ice_attr_gtpu_session[] = {
{ ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
{ ICE_MAC_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_SESSION },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_SESSION },
};
static const struct ice_ptype_attributes ice_attr_gtpu_eh[] = {
@@ -550,6 +590,46 @@ static const struct ice_ptype_attributes ice_attr_gtpu_eh[] = {
{ ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
{ ICE_MAC_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH },
};
static const struct ice_ptype_attributes ice_attr_gtpu_down[] = {
@@ -573,6 +653,46 @@ static const struct ice_ptype_attributes ice_attr_gtpu_down[] = {
{ ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
{ ICE_MAC_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_DOWNLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_DOWNLINK },
};
static const struct ice_ptype_attributes ice_attr_gtpu_up[] = {
@@ -596,13 +716,53 @@ static const struct ice_ptype_attributes ice_attr_gtpu_up[] = {
{ ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
{ ICE_MAC_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
{ ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV4_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_UPLINK },
+ { MAC_IPV6_TUN_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_UPLINK },
};
static const u32 ice_ptypes_gtpu[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x7FFFFE00, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x0000003F, 0xBEFBEFBC, 0x0002FBEF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -1251,6 +1411,10 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_IPV4_SA:
case ICE_FLOW_FIELD_IDX_IPV4_DA:
prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL;
+ if (params->prof->segs[0].hdrs & ICE_FLOW_SEG_HDR_GRE &&
+ params->prof->segs[1].hdrs & ICE_FLOW_SEG_HDR_GTPU &&
+ seg == 1)
+ prot_id = ICE_PROT_IPV4_IL_IL;
break;
case ICE_FLOW_FIELD_IDX_IPV4_ID:
prot_id = ICE_PROT_IPV4_OF_OR_S;
@@ -1264,6 +1428,10 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_IPV6_PRE64_SA:
case ICE_FLOW_FIELD_IDX_IPV6_PRE64_DA:
prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL;
+ if (params->prof->segs[0].hdrs & ICE_FLOW_SEG_HDR_GRE &&
+ params->prof->segs[1].hdrs & ICE_FLOW_SEG_HDR_GTPU &&
+ seg == 1)
+ prot_id = ICE_PROT_IPV6_IL_IL;
break;
case ICE_FLOW_FIELD_IDX_IPV6_ID:
prot_id = ICE_PROT_IPV6_FRAG;
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index 220ff3b773..cef8354f77 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -159,8 +159,10 @@ enum ice_prot_id {
ICE_PROT_MPLS_IL = 29,
ICE_PROT_IPV4_OF_OR_S = 32,
ICE_PROT_IPV4_IL = 33,
+ ICE_PROT_IPV4_IL_IL = 34,
ICE_PROT_IPV6_OF_OR_S = 40,
ICE_PROT_IPV6_IL = 41,
+ ICE_PROT_IPV6_IL_IL = 42,
ICE_PROT_IPV6_FRAG = 47,
ICE_PROT_TCP_IL = 49,
ICE_PROT_UDP_OF = 52,
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 6ae39a345b..4e33d14c6d 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -373,6 +373,118 @@ enum ice_fltr_ptype {
ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6,
ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4 checksum
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (21 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:45 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 24/28] net/ice/base: enable jumbo frame support during HW init Qi Zhang
` (5 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Alvin Zhang
The IPv4/TCP/UDP/SCTP header checksum fields are defined in this
patch and can be used as RSS input sets.
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 17 +++++++++++++++++
drivers/net/ice/base/ice_flow.h | 4 ++++
2 files changed, 21 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 0b7d087c83..470548331b 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -15,6 +15,10 @@
#define ICE_FLOW_FLD_SZ_IPV6_PRE64_ADDR 8
#define ICE_FLOW_FLD_SZ_IPV4_ID 2
#define ICE_FLOW_FLD_SZ_IPV6_ID 4
+#define ICE_FLOW_FLD_SZ_IP_CHKSUM 2
+#define ICE_FLOW_FLD_SZ_TCP_CHKSUM 2
+#define ICE_FLOW_FLD_SZ_UDP_CHKSUM 2
+#define ICE_FLOW_FLD_SZ_SCTP_CHKSUM 4
#define ICE_FLOW_FLD_SZ_IP_DSCP 1
#define ICE_FLOW_FLD_SZ_IP_TTL 1
#define ICE_FLOW_FLD_SZ_IP_PROT 1
@@ -98,6 +102,8 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 8, ICE_FLOW_FLD_SZ_IPV6_ADDR),
/* ICE_FLOW_FIELD_IDX_IPV6_DA */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 24, ICE_FLOW_FLD_SZ_IPV6_ADDR),
+ /* ICE_FLOW_FIELD_IDX_IPV4_CHKSUM */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 10, ICE_FLOW_FLD_SZ_IP_CHKSUM),
/* ICE_FLOW_FIELD_IDX_IPV4_FRAG */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV_FRAG, 4,
ICE_FLOW_FLD_SZ_IPV4_ID),
@@ -137,6 +143,13 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 2, ICE_FLOW_FLD_SZ_PORT),
/* ICE_FLOW_FIELD_IDX_TCP_FLAGS */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_TCP, 13, ICE_FLOW_FLD_SZ_TCP_FLAGS),
+ /* ICE_FLOW_FIELD_IDX_TCP_CHKSUM */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_TCP, 16, ICE_FLOW_FLD_SZ_TCP_CHKSUM),
+ /* ICE_FLOW_FIELD_IDX_UDP_CHKSUM */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP, 6, ICE_FLOW_FLD_SZ_UDP_CHKSUM),
+ /* ICE_FLOW_FIELD_IDX_SCTP_CHKSUM */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 8,
+ ICE_FLOW_FLD_SZ_SCTP_CHKSUM),
/* ARP */
/* ICE_FLOW_FIELD_IDX_ARP_SIP */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ARP, 14, ICE_FLOW_FLD_SZ_IPV4_ADDR),
@@ -1410,6 +1423,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
break;
case ICE_FLOW_FIELD_IDX_IPV4_SA:
case ICE_FLOW_FIELD_IDX_IPV4_DA:
+ case ICE_FLOW_FIELD_IDX_IPV4_CHKSUM:
prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL;
if (params->prof->segs[0].hdrs & ICE_FLOW_SEG_HDR_GRE &&
params->prof->segs[1].hdrs & ICE_FLOW_SEG_HDR_GTPU &&
@@ -1439,14 +1453,17 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_TCP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_TCP_DST_PORT:
case ICE_FLOW_FIELD_IDX_TCP_FLAGS:
+ case ICE_FLOW_FIELD_IDX_TCP_CHKSUM:
prot_id = ICE_PROT_TCP_IL;
break;
case ICE_FLOW_FIELD_IDX_UDP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_UDP_DST_PORT:
+ case ICE_FLOW_FIELD_IDX_UDP_CHKSUM:
prot_id = ICE_PROT_UDP_IL_OR_S;
break;
case ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
+ case ICE_FLOW_FIELD_IDX_SCTP_CHKSUM:
prot_id = ICE_PROT_SCTP_IL;
break;
case ICE_FLOW_FIELD_IDX_VXLAN_VNI:
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 39408c5634..92beb75db8 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -228,6 +228,7 @@ enum ice_flow_field {
ICE_FLOW_FIELD_IDX_IPV4_DA,
ICE_FLOW_FIELD_IDX_IPV6_SA,
ICE_FLOW_FIELD_IDX_IPV6_DA,
+ ICE_FLOW_FIELD_IDX_IPV4_CHKSUM,
ICE_FLOW_FIELD_IDX_IPV4_ID,
ICE_FLOW_FIELD_IDX_IPV6_ID,
ICE_FLOW_FIELD_IDX_IPV6_PRE32_SA,
@@ -244,6 +245,9 @@ enum ice_flow_field {
ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT,
ICE_FLOW_FIELD_IDX_SCTP_DST_PORT,
ICE_FLOW_FIELD_IDX_TCP_FLAGS,
+ ICE_FLOW_FIELD_IDX_TCP_CHKSUM,
+ ICE_FLOW_FIELD_IDX_UDP_CHKSUM,
+ ICE_FLOW_FIELD_IDX_SCTP_CHKSUM,
/* ARP */
ICE_FLOW_FIELD_IDX_ARP_SIP,
ICE_FLOW_FIELD_IDX_ARP_DIP,
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 24/28] net/ice/base: enable jumbo frame support during HW init
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (22 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4 checksum Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:45 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields Qi Zhang
` (4 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Anirudh Venkataramanan
Call ice_aq_set_mac_cfg in ice_hw_init to enable jumbo frame support.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 2744c3d119..ad9df0d3a2 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -994,6 +994,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_fltr_mgmt_struct;
+
+ /* enable jumbo frame support at MAC level */
+ status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
+ if (status)
+ goto err_unroll_fltr_mgmt_struct;
+
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (23 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 24/28] net/ice/base: enable jumbo frame support during HW init Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 26/28] net/ice/base: rename and add a setter function Qi Zhang
` (3 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang
Enable Flow Director filtering for GTPU UL/DL QFI field matching.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 8 ++++++++
drivers/net/ice/base/ice_flow.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 470548331b..96d54b494d 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -185,9 +185,15 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
/* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12,
ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_UP_QFI */
+ ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_GTPU_UP, 22,
+ ICE_FLOW_FLD_SZ_GTP_QFI, 0x3f00),
/* ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_DWN, 12,
ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_DWN_QFI */
+ ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_GTPU_DWN, 22,
+ ICE_FLOW_FLD_SZ_GTP_QFI, 0x3f00),
/* PPPOE */
/* ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PPPOE, 2,
@@ -1473,6 +1479,8 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID:
case ICE_FLOW_FIELD_IDX_GTPU_EH_TEID:
case ICE_FLOW_FIELD_IDX_GTPU_EH_QFI:
+ case ICE_FLOW_FIELD_IDX_GTPU_UP_QFI:
+ case ICE_FLOW_FIELD_IDX_GTPU_DWN_QFI:
/* GTP is accessed through UDP OF protocol */
prot_id = ICE_PROT_UDP_OF;
break;
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 92beb75db8..371d960066 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -268,8 +268,10 @@ enum ice_flow_field {
ICE_FLOW_FIELD_IDX_GTPU_EH_QFI,
/* GTPU_UP */
ICE_FLOW_FIELD_IDX_GTPU_UP_TEID,
+ ICE_FLOW_FIELD_IDX_GTPU_UP_QFI,
/* GTPU_DWN */
ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID,
+ ICE_FLOW_FIELD_IDX_GTPU_DWN_QFI,
/* PPPOE */
ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID,
/* PFCP */
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 26/28] net/ice/base: rename and add a setter function
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (24 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data Qi Zhang
` (2 subsequent siblings)
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Anirudh Venkataramanan
Rename ucast_shared to umac_shared, as "umac" is a more widely
used shorthand for "unicast MAC".
Also add a helper function to set this flag. This helper is
expected to be called by core drivers.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 11 +++++++++++
drivers/net/ice/base/ice_common.h | 1 +
drivers/net/ice/base/ice_switch.c | 8 ++++----
drivers/net/ice/base/ice_type.h | 3 ++-
4 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index ad9df0d3a2..9c6649b6c5 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -864,6 +864,17 @@ void ice_print_rollback_msg(struct ice_hw *hw)
nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
}
+/**
+ * ice_set_umac_shared
+ * @hw: pointer to the hw struct
+ *
+ * Set boolean flag to allow unicast MAC sharing
+ */
+void ice_set_umac_shared(struct ice_hw *hw)
+{
+ hw->umac_shared = true;
+}
+
/**
* ice_init_hw - main hardware initialization routine
* @hw: pointer to the hardware structure
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index ac6b487347..e84308444d 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -23,6 +23,7 @@ enum ice_fw_modes {
enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw);
void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw);
+void ice_set_umac_shared(struct ice_hw *hw);
enum ice_status ice_init_hw(struct ice_hw *hw);
void ice_deinit_hw(struct ice_hw *hw);
enum ice_status ice_check_reset(struct ice_hw *hw);
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 2d8904d2c3..9179f66c20 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4681,7 +4681,7 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
* @sw: pointer to switch info struct for which function add rule
* @lport: logic port number on which function add rule
*
- * IMPORTANT: When the ucast_shared flag is set to false and m_list has
+ * IMPORTANT: When the umac_shared flag is set to false and m_list has
* multiple unicast addresses, the function assumes that all the
* addresses are unique in a given add_mac call. It doesn't
* check for duplicates in this case, removing duplicates from a given
@@ -4724,7 +4724,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
if (m_list_itr->fltr_info.lkup_type != ICE_SW_LKUP_MAC ||
IS_ZERO_ETHER_ADDR(add))
return ICE_ERR_PARAM;
- if (IS_UNICAST_ETHER_ADDR(add) && !hw->ucast_shared) {
+ if (IS_UNICAST_ETHER_ADDR(add) && !hw->umac_shared) {
/* Don't overwrite the unicast address */
ice_acquire_lock(rule_lock);
if (ice_find_rule_entry(rule_head,
@@ -4735,7 +4735,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
ice_release_lock(rule_lock);
num_unicast++;
} else if (IS_MULTICAST_ETHER_ADDR(add) ||
- (IS_UNICAST_ETHER_ADDR(add) && hw->ucast_shared)) {
+ (IS_UNICAST_ETHER_ADDR(add) && hw->umac_shared)) {
m_list_itr->status =
ice_add_rule_internal(hw, recp_list, lport,
m_list_itr);
@@ -5424,7 +5424,7 @@ ice_remove_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,
list_itr->fltr_info.fwd_id.hw_vsi_id =
ice_get_hw_vsi_num(hw, vsi_handle);
- if (IS_UNICAST_ETHER_ADDR(add) && !hw->ucast_shared) {
+ if (IS_UNICAST_ETHER_ADDR(add) && !hw->umac_shared) {
/* Don't remove the unicast address that belongs to
* another VSI on the switch, since it is not being
* shared...
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 4e33d14c6d..56ee628f10 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1194,7 +1194,8 @@ struct ice_hw {
/* INTRL granularity in 1 us */
u8 intrl_gran;
- u8 ucast_shared; /* true if VSIs can share unicast addr */
+ /* true if VSIs can share unicast MAC addr */
+ u8 umac_shared;
#define ICE_PHY_PER_NAC 1
#define ICE_MAX_QUAD 2
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (25 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 26/28] net/ice/base: rename and add a setter function Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
2021-08-13 16:50 ` Ferruh Yigit
2021-08-10 2:51 ` [dpdk-dev] [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile Qi Zhang
2021-08-11 2:25 ` [dpdk-dev] [PATCH 00/28] ice: base code update Zhang, Qi Z
28 siblings, 2 replies; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Kevin Scott
Correct spelling of word data instead of date.
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 9c6649b6c5..641859f752 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3528,7 +3528,7 @@ ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
/**
* ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
* @pi: port information structure
- * @caps: PHY ability structure to copy date from
+ * @caps: PHY ability structure to copy data from
* @cfg: PHY configuration structure to copy data to
*
* Helper function to copy AQC PHY get ability data to PHY set configuration
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* [dpdk-dev] [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (26 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data Qi Zhang
@ 2021-08-10 2:51 ` Qi Zhang
2021-08-10 4:47 ` Guo, Junfeng
2021-08-11 2:25 ` [dpdk-dev] [PATCH 00/28] ice: base code update Zhang, Qi Z
28 siblings, 1 reply; 60+ messages in thread
From: Qi Zhang @ 2021-08-10 2:51 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang
For GTPoGRE protocol in AVF FDIR/RSS, the number of associated PTGs
of one Profile may exceeds the defined ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE. In those cases, some PTGs may be missed,
and therefore, the related and received packets will not have hash
values. Thus, this patch updated the ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE to a larger number 64.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_type.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index eb8290713b..247b85a192 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -804,8 +804,8 @@ struct ice_ptg_ptype {
u8 ptg;
};
-#define ICE_MAX_TCAM_PER_PROFILE 32
-#define ICE_MAX_PTG_PER_PROFILE 32
+#define ICE_MAX_TCAM_PER_PROFILE 64
+#define ICE_MAX_PTG_PER_PROFILE 64
struct ice_prof_map {
struct LIST_ENTRY_TYPE list;
--
2.26.2
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe
2021-08-10 2:51 ` [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe Qi Zhang
@ 2021-08-10 4:31 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:31 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 01/28] net/ice/base: add 1588 capability probe
>
> Parse 1588 timesync capability during device capability probing.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_adminq_cmd.h | 1 +
> drivers/net/ice/base/ice_common.c | 111
> ++++++++++++++++++++++++++
> drivers/net/ice/base/ice_type.h | 72 +++++++++++++++++
> 3 files changed, 184 insertions(+)
>
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 02/28] net/ice/base: add low level functions for device clock control
2021-08-10 2:51 ` [dpdk-dev] [PATCH 02/28] net/ice/base: add low level functions for device clock control Qi Zhang
@ 2021-08-10 4:33 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:33 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 02/28] net/ice/base: add low level functions for device
> clock control
>
> The ice hardware supports exposing a hardware clock for high precision
> timestamping. This is primarily intended for accelerating the Precision
> Time Protocol.
>
> Add several low level functions intended to be used as the basis for
> enabling the device clock, and ensuring that the port timers are
> synchronized properly.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_adminq_cmd.h | 1 +
> drivers/net/ice/base/ice_common.c | 143 ++
> drivers/net/ice/base/ice_common.h | 11 +
> drivers/net/ice/base/ice_controlq.c | 52 +-
> drivers/net/ice/base/ice_controlq.h | 2 +
> drivers/net/ice/base/ice_ptp_consts.h | 86 ++
> drivers/net/ice/base/ice_ptp_hw.c | 2023
> +++++++++++++++++++++++++
> drivers/net/ice/base/ice_ptp_hw.h | 376 +++++
> drivers/net/ice/base/ice_type.h | 3 +
> drivers/net/ice/base/meson.build | 1 +
> 10 files changed, 2697 insertions(+), 1 deletion(-)
> create mode 100644 drivers/net/ice/base/ice_ptp_consts.h
> create mode 100644 drivers/net/ice/base/ice_ptp_hw.c
> create mode 100644 drivers/net/ice/base/ice_ptp_hw.h
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 03/28] net/ice/base: add ethertype IPv6 check for dummy packet
2021-08-10 2:51 ` [dpdk-dev] [PATCH 03/28] net/ice/base: add ethertype IPv6 check for dummy packet Qi Zhang
@ 2021-08-10 4:34 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:34 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Nitka, Grzegorz
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Nitka, Grzegorz <grzegorz.nitka@intel.com>
> Subject: [PATCH 03/28] net/ice/base: add ethertype IPv6 check for
> dummy packet
>
> In order to support switch rule for ethertype filter
> with ipv6 ethertype id, it has to check ethertype and
> then find a proper dummy packet. There was a silent
> assumption that packet is ipv4, unless src or dst ipv6
> address is specified in a flow.
>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_switch.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 04/28] net/ice/base: change dummy packets with VLAN
2021-08-10 2:51 ` [dpdk-dev] [PATCH 04/28] net/ice/base: change dummy packets with VLAN Qi Zhang
@ 2021-08-10 4:35 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:35 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Swiatkowski, Michal
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Swiatkowski, Michal
> <michal.swiatkowski@intel.com>
> Subject: [PATCH 04/28] net/ice/base: change dummy packets with VLAN
>
> Ethertype was traded as VLAN tpid in dummy packets with VLAN.
> This led to a problem when user wanted to add filter for VLAN and
> ethertype.
>
> Change ice_vlan_hdr to reflect correct order of VLAN fields in
> packets (VLAN tpid, VLAN id). Correct all dummy packets with VLAN.
> Move VLAN fields before ethertype and change offsets. Leave values
> from dummy packets unchanged as they fit to new VLAN layout.
>
> Order of offsets in ice_prot_ext_tbl_entry for VLAN protocol should
> reflect order of fields in ice_vlan_hdr. However, hardware doesn't
> support matching on all tpid. This should be done by matching on
> packet flags. There is no FV word with protocol for VLAN and offset
> 2. Because of that, adding vlan tpid with not zero mask will lead
> to error in creating recipe.
>
> Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_protocol_type.h | 2 +-
> drivers/net/ice/base/ice_switch.c | 148 +++++++++++------------
> 2 files changed, 73 insertions(+), 77 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks
2021-08-10 2:51 ` [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks Qi Zhang
@ 2021-08-10 4:35 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:35 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Sridhar, Vignesh
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Sridhar, Vignesh <vignesh.sridhar@intel.com>
> Subject: [PATCH 05/28] net/ice/base: add timestamp masks
>
> Adding macros for shift and masking of the lower timestamp work in the
> Rx flex descriptor. The LSB of the timestamp-low word indicates the
> validity of the timestamp while the rest 7 bits contain the timestamp.
>
> Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_lan_tx_rx.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization function
2021-08-10 2:51 ` [dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization function Qi Zhang
@ 2021-08-10 4:36 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:36 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 06/28] net/ice/base: add clock initialization function
>
> Before the device PTP hardware clock can be initialized, some steps must
> be taken by the driver. This includes writing some registers and
> initializing the PHY.
>
> Some of these steps are distinct depending on the device type (E810 or
> E822). Additionally, a future change will introduce more steps for E822
> devices to program the Clock Generation Unit.
>
> Introduce ice_ptp_init_phc as well as device-specific sub-functions for
> e810 and e822 devices.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_cgu_regs.h | 117 +++++++++
> drivers/net/ice/base/ice_ptp_consts.h | 74 ++++++
> drivers/net/ice/base/ice_ptp_hw.c | 348
> +++++++++++++++++++++++++-
> drivers/net/ice/base/ice_ptp_hw.h | 24 ++
> 4 files changed, 562 insertions(+), 1 deletion(-)
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 07/28] net/ice/base: add accessors to get/set the time reference
2021-08-10 2:51 ` [dpdk-dev] [PATCH 07/28] net/ice/base: add accessors to get/set the time reference Qi Zhang
@ 2021-08-10 4:37 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:37 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 07/28] net/ice/base: add accessors to get/set the time
> reference
>
> The E822 device clock might come from a variety of different sources,
> called TIME_REFs. The firmware reports the current TIME_REF as part of
> its function capabilities, which the driver caches when it loads.
>
> Add an accessor function to look up the current TIME_REF from the
> capabilities. This reduces line length significantly and also avoids
> a tight coupling to the capabilities structure.
>
> In some cases, TIME_REF might change at run time. This can occur in the
> event that the CGU registers are updated. When this happens, its
> possible that the capabilities structure can be out of date until the
> capabilities are re-read.
>
> Add an setter function to update the TIME_REF when this occurs. The
> driver can call this function after updating the CGU to ensure that the
> TIME_REF in the capabilities structure is up to date, without needing to
> re-read the entire capabilities from firmware.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_ptp_hw.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types
2021-08-10 2:51 ` [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types Qi Zhang
@ 2021-08-10 4:37 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:37 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Venkataramanan, Anirudh
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Venkataramanan, Anirudh
> <anirudh.venkataramanan@intel.com>
> Subject: [PATCH 08/28] net/ice/base: print human-friendly PHY types
>
> Add functions to print PHY types in human-friendly form
>
> Signed-off-by: Anirudh Venkataramanan
> <anirudh.venkataramanan@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 164
> ++++++++++++++++++++++++++----
> 1 file changed, 146 insertions(+), 18 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 09/28] net/ice/base: implement Vernier calibration logic for E822 devices
2021-08-10 2:51 ` [dpdk-dev] [PATCH 09/28] net/ice/base: implement Vernier calibration logic for E822 devices Qi Zhang
@ 2021-08-10 4:38 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:38 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 09/28] net/ice/base: implement Vernier calibration logic
> for E822 devices
>
> Move the implementation of Vernier calibration from Linux core ice_ptp.c
> into the shared ice_ptp_hw.c file.
>
> This implementation was recently refactored in Linux, so the move should
> be verbatim with the latest Linux code that we had implemented.
>
> This includes a new constant table with pre-determined values based on
> link speed, new functions to aide in reading the multi-register values
> from the PHY, functions to program the PAR/PCS conversion ratios, and
> the UIX conversion ratios, functions to program the total Tx and Rx
> offset after vernier calibration in the hardware completes, and finally
> a function to start and stop the PHY timestamping block.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_ptp_consts.h | 216 ++++++
> drivers/net/ice/base/ice_ptp_hw.c | 999
> ++++++++++++++++++++++++++
> drivers/net/ice/base/ice_ptp_hw.h | 47 ++
> 3 files changed, 1262 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 10/28] net/ice/base: clarify comments on checking PFC mode
2021-08-10 2:51 ` [dpdk-dev] [PATCH 10/28] net/ice/base: clarify comments on checking PFC mode Qi Zhang
@ 2021-08-10 4:39 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:39 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Nguyen, Anthony L
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>
> Subject: [PATCH 10/28] net/ice/base: clarify comments on checking PFC
> mode
>
> Rework the comment around checking PFC mode to make it clear why we
> are
> checking the mode after sending the command.
>
> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_dcb.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode
2021-08-10 2:51 ` [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode Qi Zhang
@ 2021-08-10 4:39 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:39 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 11/28] net/ice/base: add support for starting PHY in
> bypass mode
>
> After starting the timestamping block, hardware begins calculating
> precise offsets through a process of vernier calibration. This process
> measures the effective phase offset of the various internal clocks used
> in the PHY.
>
> Once hardware completes these measurements, the
> P_REG_TX_OV_STATUS and
> P_REG_RX_OV_STATUS registers are updated to indicate that the
> hardware
> offset measurements are done.
>
> This process does not happen immediately, but requires that at least one
> packet be sent or received in order for the offset in that direction to
> be calculated.
>
> This poses a problem in some setups, because software expects the first
> packet sent to be timestamped. This most often occurs if the clock time
> is set by an application during startup. This set time command triggers
> a PHY restart. Because of this, the timestamping block is reset, and
> timestamps are not enabled until vernier calibration is complete. Since
> this process won't complete until at least one packet is sent through
> the PHY, timestamps of the very first packet sent will not be obtained.
>
> This can result in the application failing due to missing timestamps.
>
> To avoid this, allow starting the PHY in bypass mode. This mode enables
> timestamps immediately, and skips adding the precise offset
> measurement.
> This reduces the accuracy of the timestamp slightly, but ensures that we
> get a reasonable value for the first packet.
>
> The driver can continue monitoring the P_REG_TX_OV_STATUS and
> P_REG_RX_OV_STATUS registers and exit bypass mode once the total
> calibration is completed. In this way, once calibration is complete, the
> timestamps will have the precise offset, but we do not break
> applications which expect to be able to timestamp immediately.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_ptp_hw.c | 84
> +++++++++++++++++++++++++++++++
> drivers/net/ice/base/ice_ptp_hw.h | 1 +
> 2 files changed, 85 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 12/28] net/ice/base: add E810T check function
2021-08-10 2:51 ` [dpdk-dev] [PATCH 12/28] net/ice/base: add E810T check function Qi Zhang
@ 2021-08-10 4:39 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:39 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Michalik, Michal
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Michalik, Michal <Michal.Michalik@intel.com>
> Subject: [PATCH 12/28] net/ice/base: add E810T check function
>
> Add function ice_is_e810t() to be able to distinguish if hardware is E810T
> based or not.
>
> Signed-off-by: Michal Michalik <michal.michalik@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 12 ++++++++++++
> drivers/net/ice/base/ice_common.h | 1 +
> drivers/net/ice/base/ice_devids.h | 1 +
> 3 files changed, 14 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump
2021-08-10 2:51 ` [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump Qi Zhang
@ 2021-08-10 4:40 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:40 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Domagala, MarcinX
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Domagala, MarcinX
> <marcinx.domagala@intel.com>
> Subject: [PATCH 13/28] net/ice/base: implement firmware debug dump
>
> Basic implementation of FW Debug Dump.
>
> Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_adminq_cmd.h | 25 ++++++++++++++
> drivers/net/ice/base/ice_common.c | 50
> +++++++++++++++++++++++++++
> drivers/net/ice/base/ice_common.h | 6 ++++
> 3 files changed, 81 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 14/28] net/ice/base: add new AQ description
2021-08-10 2:51 ` [dpdk-dev] [PATCH 14/28] net/ice/base: add new AQ description Qi Zhang
@ 2021-08-10 4:40 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:40 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, D H, Siddaraju
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; D H, Siddaraju <siddaraju.dh@intel.com>
> Subject: [PATCH 14/28] net/ice/base: add new AQ description
>
> Add ice_aqc_sw_gpio struct to ice_aq_desc
> This change allows us to do SW_GPIO AQ cmd transactions
> over ice_aq_send_cmd() interface.
>
> Signed-off-by: Siddaraju DH <siddaraju.dh@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_adminq_cmd.h | 1 +
> 1 file changed, 1 insertion(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 15/28] net/ice/base: refine MAC rule adding
2021-08-10 2:51 ` [dpdk-dev] [PATCH 15/28] net/ice/base: refine MAC rule adding Qi Zhang
@ 2021-08-10 4:41 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:41 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Domagala, MarcinX
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Domagala, MarcinX
> <marcinx.domagala@intel.com>
> Subject: [PATCH 15/28] net/ice/base: refine MAC rule adding
>
> Move replay_pre_init function to interface.
> Add further MAC rules, despite unicast address is already on list.
>
> Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 2 +-
> drivers/net/ice/base/ice_common.h | 2 ++
> drivers/net/ice/base/ice_switch.c | 2 +-
> 3 files changed, 4 insertions(+), 2 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 16/28] net/ice/base: support TC nodes PIR configuration
2021-08-10 2:51 ` [dpdk-dev] [PATCH 16/28] net/ice/base: support TC nodes PIR configuration Qi Zhang
@ 2021-08-10 4:41 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:41 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Xu, Ting
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Xu, Ting <Ting.Xu@intel.com>
> Subject: [PATCH 16/28] net/ice/base: support TC nodes PIR configuration
>
> TC nodes CIR configuration is not supported. In order to configure PIR,
> the corresponding adminq command should not include the flag for CIR.
> Since the TC node info has this flag by default, it is supposed to delete
> this flag for TC nodes before sending the adminq command.
>
> Signed-off-by: Ting Xu <ting.xu@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_sched.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet
2021-08-10 2:51 ` [dpdk-dev] [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet Qi Zhang
@ 2021-08-10 4:41 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:41 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Wu, Wenjun1
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Wu, Wenjun1 <Wenjun1.Wu@intel.com>
> Subject: [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet
>
> Support IPV4_GRE and IPV6_GRE with inner IPV4/IPV6/UDP/TCP for
> FDIR.
>
> Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_fdir.c | 361
> ++++++++++++++++++++++++++++++++
> drivers/net/ice/base/ice_fdir.h | 2 +
> drivers/net/ice/base/ice_type.h | 14 ++
> 3 files changed, 377 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS for GRE tunnel packet
2021-08-10 2:51 ` [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS " Qi Zhang
@ 2021-08-10 4:42 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:42 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Wu, Wenjun1
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Wu, Wenjun1 <Wenjun1.Wu@intel.com>
> Subject: [PATCH 18/28] net/ice/base: support RSS for GRE tunnel packet
>
> Support RSS of inner headers for GRE tunnel packet.
>
> Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_flow.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner IPv6
2021-08-10 2:51 ` [dpdk-dev] [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner IPv6 Qi Zhang
@ 2021-08-10 4:43 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:43 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner
> IPv6
>
> Supuport FDIR filtering for IPV4_GTPU_EH_IPV6 with inner
> IPV6/UDP/TCP fields matching.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_fdir.c | 352 ++++++++++++++++++++++++++-----
> -
> drivers/net/ice/base/ice_type.h | 23 ++-
> 2 files changed, 309 insertions(+), 66 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 20/28] net/ice/base: support RSS for GTPoGRE
2021-08-10 2:51 ` [dpdk-dev] [PATCH 20/28] net/ice/base: support RSS for GTPoGRE Qi Zhang
@ 2021-08-10 4:43 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:43 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 20/28] net/ice/base: support RSS for GTPoGRE
>
> Support RSS for GTPoGRE inner fields hash.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_flow.c | 8 ++++++++
> drivers/net/ice/base/ice_flow.h | 4 ++++
> 2 files changed, 12 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities
2021-08-10 2:51 ` [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities Qi Zhang
@ 2021-08-10 4:43 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:43 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Keller, Jacob E
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [PATCH 21/28] net/ice/base: enable NVM update reset
> capabilities
>
> Add logic to parse capabilities relating to the firmware update reset
> requirements. This includes both capability 0x76, which informs the
> driver if the firmware can sometimes skip PCIe resets, and 0x77, which
> informs the driver if the firmware might potentially restrict EMP
> resets.
>
> For capability 0x76, if the number is 1, the firmware will report the
> required reset level for a given update as part of its response to the
> last command sent to program the NVM bank. (Otherwise, if the firmware
> does not support this capability then it will always send a 0 in the
> field of the response).
>
> For capability 0x77, if the number is 1, the firmware will report when
> EMP reset is available as part of the response to the command for
> switching flash banks. (Otherwise, if the firmware does not support this
> capability, it will always send a 0 in the field of the response
> message).
>
> These capabilities are required to implement immediate firmware
> activation. If the capabilities are set, software can read the response
> data and determine what reset level is required to activate the firmware
> image. If only an EMP reset is required, and if the EMP reset is not
> restricted by firmware, then the driver can issue an EMP reset to
> immediately activate the new firmware.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 12 ++++++++++++
> drivers/net/ice/base/ice_type.h | 4 ++++
> 2 files changed, 16 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE
2021-08-10 2:51 ` [dpdk-dev] [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE Qi Zhang
@ 2021-08-10 4:44 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:44 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE
>
> Enable Flow Director filtering for GTPoGRE inner/outer fields
> matching.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_fdir.c | 1532 ++++++++++++++++++++++
> drivers/net/ice/base/ice_fdir.h | 12 +
> drivers/net/ice/base/ice_flex_pipe.c | 6 +
> drivers/net/ice/base/ice_flex_type.h | 48 +
> drivers/net/ice/base/ice_flow.c | 184 ++-
> drivers/net/ice/base/ice_protocol_type.h | 2 +
> drivers/net/ice/base/ice_type.h | 112 ++
> 7 files changed, 1888 insertions(+), 8 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4 checksum
2021-08-10 2:51 ` [dpdk-dev] [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4 checksum Qi Zhang
@ 2021-08-10 4:45 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:45 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Zhang, AlvinX
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Zhang, AlvinX <AlvinX.Zhang@intel.com>
> Subject: [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4
> checksum
>
> The IPv4/TCP/UDP/SCTP header checksum fields are defined in this
> patch and can be used as RSS input sets.
>
> Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_flow.c | 17 +++++++++++++++++
> drivers/net/ice/base/ice_flow.h | 4 ++++
> 2 files changed, 21 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 24/28] net/ice/base: enable jumbo frame support during HW init
2021-08-10 2:51 ` [dpdk-dev] [PATCH 24/28] net/ice/base: enable jumbo frame support during HW init Qi Zhang
@ 2021-08-10 4:45 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:45 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Venkataramanan, Anirudh
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Venkataramanan, Anirudh
> <anirudh.venkataramanan@intel.com>
> Subject: [PATCH 24/28] net/ice/base: enable jumbo frame support during
> HW init
>
> Call ice_aq_set_mac_cfg in ice_hw_init to enable jumbo frame support.
>
> Signed-off-by: Anirudh Venkataramanan
> <anirudh.venkataramanan@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields
2021-08-10 2:51 ` [dpdk-dev] [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields Qi Zhang
@ 2021-08-10 4:46 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:46 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with
> QFI fields
>
> Enable Flow Director filtering for GTPU UL/DL QFI field matching.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_flow.c | 8 ++++++++
> drivers/net/ice/base/ice_flow.h | 2 ++
> 2 files changed, 10 insertions(+)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 26/28] net/ice/base: rename and add a setter function
2021-08-10 2:51 ` [dpdk-dev] [PATCH 26/28] net/ice/base: rename and add a setter function Qi Zhang
@ 2021-08-10 4:46 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:46 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Venkataramanan, Anirudh
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Venkataramanan, Anirudh
> <anirudh.venkataramanan@intel.com>
> Subject: [PATCH 26/28] net/ice/base: rename and add a setter function
>
> Rename ucast_shared to umac_shared, as "umac" is a more widely
> used shorthand for "unicast MAC".
>
> Also add a helper function to set this flag. This helper is
> expected to be called by core drivers.
>
> Signed-off-by: Anirudh Venkataramanan
> <anirudh.venkataramanan@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 11 +++++++++++
> drivers/net/ice/base/ice_common.h | 1 +
> drivers/net/ice/base/ice_switch.c | 8 ++++----
> drivers/net/ice/base/ice_type.h | 3 ++-
> 4 files changed, 18 insertions(+), 5 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data
2021-08-10 2:51 ` [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data Qi Zhang
@ 2021-08-10 4:46 ` Guo, Junfeng
2021-08-13 16:50 ` Ferruh Yigit
1 sibling, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:46 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev, Scott, Kevin C
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Scott, Kevin C <kevin.c.scott@intel.com>
> Subject: [PATCH 27/28] net/ice/base: correct spellling of word data
>
> Correct spelling of word data instead of date.
>
> Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile
2021-08-10 2:51 ` [dpdk-dev] [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile Qi Zhang
@ 2021-08-10 4:47 ` Guo, Junfeng
0 siblings, 0 replies; 60+ messages in thread
From: Guo, Junfeng @ 2021-08-10 4:47 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile
>
> For GTPoGRE protocol in AVF FDIR/RSS, the number of associated PTGs
> of one Profile may exceeds the defined ICE_MAX_PTG_PER_PROFILE and
> ICE_MAX_TCAM_PER_PROFILE. In those cases, some PTGs may be missed,
> and therefore, the related and received packets will not have hash
> values. Thus, this patch updated the ICE_MAX_PTG_PER_PROFILE and
> ICE_MAX_TCAM_PER_PROFILE to a larger number 64.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_flex_type.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 00/28] ice: base code update
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
` (27 preceding siblings ...)
2021-08-10 2:51 ` [dpdk-dev] [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile Qi Zhang
@ 2021-08-11 2:25 ` Zhang, Qi Z
28 siblings, 0 replies; 60+ messages in thread
From: Zhang, Qi Z @ 2021-08-11 2:25 UTC (permalink / raw)
To: Yang, Qiming; +Cc: Guo, Junfeng, dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51 AM
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 00/28] ice: base code update
>
> Summary:
>
> 1. Add new module to support 1588 timesync / PTP.
> 2. Couple FDIR / RSS enhancement to support GRE tunnel and GTPU 3. Support
> l3/ l4 checksum RSS
>
> Qi Zhang (28):
> net/ice/base: add 1588 capability probe
> net/ice/base: add low level functions for device clock control
> net/ice/base: add ethertype IPv6 check for dummy packet
> net/ice/base: change dummy packets with VLAN
> net/ice/base: add timestamp masks
> net/ice/base: add clock initialization function
> net/ice/base: add accessors to get/set the time reference
> net/ice/base: print human-friendly PHY types
> net/ice/base: implement Vernier calibration logic for E822 devices
> net/ice/base: clarify comments on checking PFC mode
> net/ice/base: add support for starting PHY in bypass mode
> net/ice/base: add E810T check function
> net/ice/base: implement firmware debug dump
> net/ice/base: add new AQ description
> net/ice/base: refine MAC rule adding
> net/ice/base: support TC nodes PIR configuration
> net/ice/base: support FDIR for GRE tunnel packet
> net/ice/base: support RSS for GRE tunnel packet
> net/ice/base: support FDIR for GTPU EH inner IPv6
> net/ice/base: support RSS for GTPoGRE
> net/ice/base: enable NVM update reset capabilities
> net/ice/base: support FDIR for GTPoGRE
> net/ice/base: add RSS support for IPv4/L4 checksum
> net/ice/base: enable jumbo frame support during HW init
> net/ice/base: support FDIR for GTPU UL/DL with QFI fields
> net/ice/base: rename and add a setter function
> net/ice/base: correct spellling of word data
> net/ice/base: update Max TCAM/PTG Per Profile
>
> drivers/net/ice/base/ice_adminq_cmd.h | 28 +
> drivers/net/ice/base/ice_cgu_regs.h | 117 +
> drivers/net/ice/base/ice_common.c | 513 +++-
> drivers/net/ice/base/ice_common.h | 21 +
> drivers/net/ice/base/ice_controlq.c | 52 +-
> drivers/net/ice/base/ice_controlq.h | 2 +
> drivers/net/ice/base/ice_dcb.c | 9 +-
> drivers/net/ice/base/ice_devids.h | 1 +
> drivers/net/ice/base/ice_fdir.c | 2387 ++++++++++++++-
> drivers/net/ice/base/ice_fdir.h | 14 +
> drivers/net/ice/base/ice_flex_pipe.c | 6 +
> drivers/net/ice/base/ice_flex_type.h | 52 +-
> drivers/net/ice/base/ice_flow.c | 231 +-
> drivers/net/ice/base/ice_flow.h | 10 +
> drivers/net/ice/base/ice_lan_tx_rx.h | 8 +
> drivers/net/ice/base/ice_protocol_type.h | 4 +-
> drivers/net/ice/base/ice_ptp_consts.h | 376 +++
> drivers/net/ice/base/ice_ptp_hw.c | 3452 ++++++++++++++++++++++
> drivers/net/ice/base/ice_ptp_hw.h | 473 +++
> drivers/net/ice/base/ice_sched.c | 3 +
> drivers/net/ice/base/ice_switch.c | 172 +-
> drivers/net/ice/base/ice_type.h | 231 +-
> drivers/net/ice/base/meson.build | 1 +
> 23 files changed, 7892 insertions(+), 271 deletions(-) create mode 100644
> drivers/net/ice/base/ice_cgu_regs.h
> create mode 100644 drivers/net/ice/base/ice_ptp_consts.h
> create mode 100644 drivers/net/ice/base/ice_ptp_hw.c create mode
> 100644 drivers/net/ice/base/ice_ptp_hw.h
>
> --
> 2.26.2
Applied to dpdk-next-net-intel.
Thanks
Qi
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data
2021-08-10 2:51 ` [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
@ 2021-08-13 16:50 ` Ferruh Yigit
2021-08-13 16:53 ` Ferruh Yigit
1 sibling, 1 reply; 60+ messages in thread
From: Ferruh Yigit @ 2021-08-13 16:50 UTC (permalink / raw)
To: Qi Zhang, qiming.yang; +Cc: junfeng.guo, dev, Kevin Scott
On 8/10/2021 3:51 AM, Qi Zhang wrote:
> Correct spelling of word data instead of date.
Spelling of 'spellling' needs to be corrected in patch title.
>
> Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
> index 9c6649b6c5..641859f752 100644
> --- a/drivers/net/ice/base/ice_common.c
> +++ b/drivers/net/ice/base/ice_common.c
> @@ -3528,7 +3528,7 @@ ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
> /**
> * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
> * @pi: port information structure
> - * @caps: PHY ability structure to copy date from
> + * @caps: PHY ability structure to copy data from
> * @cfg: PHY configuration structure to copy data to
> *
> * Helper function to copy AQC PHY get ability data to PHY set configuration
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data
2021-08-13 16:50 ` Ferruh Yigit
@ 2021-08-13 16:53 ` Ferruh Yigit
0 siblings, 0 replies; 60+ messages in thread
From: Ferruh Yigit @ 2021-08-13 16:53 UTC (permalink / raw)
To: Qi Zhang, qiming.yang; +Cc: junfeng.guo, dev, Kevin Scott
On 8/13/2021 5:50 PM, Ferruh Yigit wrote:
> On 8/10/2021 3:51 AM, Qi Zhang wrote:
>> Correct spelling of word data instead of date.
>
> Spelling of 'spellling' needs to be corrected in patch title.
>
Fixes: 453d087ccaff ("net/ice/base: add common functions")
Cc: stable@dpdk.org
>>
>> Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
>> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
>> ---
>> drivers/net/ice/base/ice_common.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
>> index 9c6649b6c5..641859f752 100644
>> --- a/drivers/net/ice/base/ice_common.c
>> +++ b/drivers/net/ice/base/ice_common.c
>> @@ -3528,7 +3528,7 @@ ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
>> /**
>> * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
>> * @pi: port information structure
>> - * @caps: PHY ability structure to copy date from
>> + * @caps: PHY ability structure to copy data from
>> * @cfg: PHY configuration structure to copy data to
>> *
>> * Helper function to copy AQC PHY get ability data to PHY set configuration
>>
>
^ permalink raw reply [flat|nested] 60+ messages in thread
end of thread, other threads:[~2021-08-13 16:53 UTC | newest]
Thread overview: 60+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-10 2:51 [dpdk-dev] [PATCH 00/28] ice: base code update Qi Zhang
2021-08-10 2:51 ` [dpdk-dev] [PATCH 01/28] net/ice/base: add 1588 capability probe Qi Zhang
2021-08-10 4:31 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 02/28] net/ice/base: add low level functions for device clock control Qi Zhang
2021-08-10 4:33 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 03/28] net/ice/base: add ethertype IPv6 check for dummy packet Qi Zhang
2021-08-10 4:34 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 04/28] net/ice/base: change dummy packets with VLAN Qi Zhang
2021-08-10 4:35 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks Qi Zhang
2021-08-10 4:35 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 06/28] net/ice/base: add clock initialization function Qi Zhang
2021-08-10 4:36 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 07/28] net/ice/base: add accessors to get/set the time reference Qi Zhang
2021-08-10 4:37 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types Qi Zhang
2021-08-10 4:37 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 09/28] net/ice/base: implement Vernier calibration logic for E822 devices Qi Zhang
2021-08-10 4:38 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 10/28] net/ice/base: clarify comments on checking PFC mode Qi Zhang
2021-08-10 4:39 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode Qi Zhang
2021-08-10 4:39 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 12/28] net/ice/base: add E810T check function Qi Zhang
2021-08-10 4:39 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump Qi Zhang
2021-08-10 4:40 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 14/28] net/ice/base: add new AQ description Qi Zhang
2021-08-10 4:40 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 15/28] net/ice/base: refine MAC rule adding Qi Zhang
2021-08-10 4:41 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 16/28] net/ice/base: support TC nodes PIR configuration Qi Zhang
2021-08-10 4:41 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 17/28] net/ice/base: support FDIR for GRE tunnel packet Qi Zhang
2021-08-10 4:41 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS " Qi Zhang
2021-08-10 4:42 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 19/28] net/ice/base: support FDIR for GTPU EH inner IPv6 Qi Zhang
2021-08-10 4:43 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 20/28] net/ice/base: support RSS for GTPoGRE Qi Zhang
2021-08-10 4:43 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities Qi Zhang
2021-08-10 4:43 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 22/28] net/ice/base: support FDIR for GTPoGRE Qi Zhang
2021-08-10 4:44 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 23/28] net/ice/base: add RSS support for IPv4/L4 checksum Qi Zhang
2021-08-10 4:45 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 24/28] net/ice/base: enable jumbo frame support during HW init Qi Zhang
2021-08-10 4:45 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 26/28] net/ice/base: rename and add a setter function Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
2021-08-10 2:51 ` [dpdk-dev] [PATCH 27/28] net/ice/base: correct spellling of word data Qi Zhang
2021-08-10 4:46 ` Guo, Junfeng
2021-08-13 16:50 ` Ferruh Yigit
2021-08-13 16:53 ` Ferruh Yigit
2021-08-10 2:51 ` [dpdk-dev] [PATCH 28/28] net/ice/base: update Max TCAM/PTG Per Profile Qi Zhang
2021-08-10 4:47 ` Guo, Junfeng
2021-08-11 2:25 ` [dpdk-dev] [PATCH 00/28] ice: base code update Zhang, Qi Z
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