From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8922241D47; Thu, 23 Feb 2023 06:33:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4EB7F40689; Thu, 23 Feb 2023 06:33:09 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 975604021F for ; Thu, 23 Feb 2023 06:33:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677130387; x=1708666387; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=fyhztYBdOjCvfWAR1vZZtj0+HdSy2elYteglyWcCmns=; b=BGYGcwoUoKbiQBlDKR3x4Cyc89k3hpl/nAF0kmZgKlbK9LNgg5vHXk3W cO1dzn9gm6ET9/WBXjobaVfwAaix/hqklkWhkT1+A+HwRrMa1VOb7aUIN mUypyUMY3u2wtP/jw8B8ZVleSlU7d5dWeHNltMoZ2C9xFqWTe34OSCs+c Vo/SgXLWep6GsAX6ghUILxqitRMKBtyogriIz9NKBW6ZJ5z39ank7AVm9 rQ+eoL8DpuohsZ+gfb4R5tHxwPXi0Dn9gKBsWsvCQUpOts7sev7QjQocG WjnEi6KJrex9ETFGMW8MFKFDUoBCv8rnhf5ds4g0jZvZffNugcU41YugG w==; X-IronPort-AV: E=McAfee;i="6500,9779,10629"; a="316847248" X-IronPort-AV: E=Sophos;i="5.97,320,1669104000"; d="scan'208";a="316847248" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2023 21:33:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10629"; a="761235554" X-IronPort-AV: E=Sophos;i="5.97,320,1669104000"; d="scan'208";a="761235554" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by FMSMGA003.fm.intel.com with ESMTP; 22 Feb 2023 21:32:58 -0800 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Wed, 22 Feb 2023 21:32:58 -0800 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Wed, 22 Feb 2023 21:32:58 -0800 Received: from fmsedg602.ED.cps.intel.com (10.1.192.136) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16 via Frontend Transport; Wed, 22 Feb 2023 21:32:58 -0800 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.108) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.16; Wed, 22 Feb 2023 21:32:57 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WvZiQoMbv66OGdDB0ClxZjeeKEFxMeZgmuZ6oB4WB7GNlcWI5kOsdDlcTgetMiNnMsRO4l9QznNdiEEQGUAD3amXrCTbNobRnfHSE2ryBJKEH3mVTxQaXjaLH8dWYEc6Fsa9vkpjHWBe/nwvRhqezGuCmgSghfvgjsgv7djqYrnQj+jQQsK8b4hWFAVdSLt9AL/SvrgNmMWQknILTQ9f71H54A784kTnH/wQ8guXB+hXUzO0UXogEpplpz/rzPctzwli3AoXDX1MJD1RI/RfJpyk6gM8aq2oBE0CsNP8rWk5EJNrmvIIZvluKt/bdP0B0+CMrg4p6nKpInGXvv7hOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Y/Jn1Gb+TEdE+lQQYDZSeQ5IT2o/2oT8QJQlQVT3EBQ=; b=LD/1F4kmFGm1aSStZlumJWqUcinrFx3eEEztLBKtQxNb2vc/8yu3jbPwZF63EL33xyjClNnpLixVdrS9SaK9pAFhS83sKBatxp2MJysSw8gqUFuQZAK5c7UqOA+k+j1gOvx/c9khDA4gp/IsB5NChiokIoiEAah8SWSwZ2+QjGQmgUJoyGGCsDLCS6XOCFOTOJJeGVyx3bYd5BTCcVJt+smSSFfTm2u0YGJ6uPHZ3zbOsd56IGzJ69osKRDIGgf5phTQ0BRNVHu+YeOdml8z2YJygvr6htcHVp7empjs2gP4oXKmmqivtB/V481uP1nVvSlG+p30XhCb8dPLA+tNZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from DM6PR11MB3723.namprd11.prod.outlook.com (2603:10b6:5:13f::25) by SJ0PR11MB5213.namprd11.prod.outlook.com (2603:10b6:a03:2da::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.19; Thu, 23 Feb 2023 05:32:56 +0000 Received: from DM6PR11MB3723.namprd11.prod.outlook.com ([fe80::b060:3d57:bbe5:baa8]) by DM6PR11MB3723.namprd11.prod.outlook.com ([fe80::b060:3d57:bbe5:baa8%4]) with mapi id 15.20.6111.021; Thu, 23 Feb 2023 05:32:55 +0000 From: "Guo, Junfeng" To: Honnappa Nagarahalli , "Zhang, Qi Z" , "Wu, Jingjing" , "ferruh.yigit@amd.com" , "Xing, Beilei" CC: "dev@dpdk.org" , "Li, Xiaoyun" , "Zhang, Helin" , Rushil Gupta , Jordan Kimbrough , Jeroen de Borst , nd , nd Subject: RE: [RFC v3 06/10] net/gve: support basic Rx data path for DQO Thread-Topic: [RFC v3 06/10] net/gve: support basic Rx data path for DQO Thread-Index: AQHZQqL2YeabsrzULE6fOygv5GYO6K7TQKUAgAjJluA= Date: Thu, 23 Feb 2023 05:32:55 +0000 Message-ID: References: <20230130062642.3337239-1-junfeng.guo@intel.com> <20230217073228.340815-1-junfeng.guo@intel.com> <20230217073228.340815-7-junfeng.guo@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DM6PR11MB3723:EE_|SJ0PR11MB5213:EE_ x-ms-office365-filtering-correlation-id: 9f2f5d92-e1ad-4809-25ca-08db155f6a71 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ksK//y8lP/h+zoXF780/DJyKJWofy6mOR69haTT7n02dk/caK6yfMcxCA2jPVXDI3uU4kxsy6qRF6HKs8EprrD2Yi+X+vwHRzG8gtVbhjyRZJ7PjDKCtsCZI16OaVFkSeOWtyVQUR714r8r4nCraQ7GoEVc7l8+m1bYbrtv2MIIMbWvOoDKPdGlKvVkYX++v+6Y6RvBgv19R3kzPWtLyZYgib3Ox3EC0kcKSynJNrDDSNIU7fAMecXt8iv2ABuZCw0fT8dmGviSU8Uod/PNQK1m6pq9FlZTxTxZ5h1FsGD1VbQAultcdkVi5NF7c+/DS5HDtc5DK2v8WFAWsLLoP689voxNlvukDvdg9N7bASceTEK9T7WLxj/3rXb9mSpyjxK1CGx/4BKL9ZQlTbdW2flQeRekMawJvakOzmAetIdOs/pMb33TQ5okYskrVX/ub3ibdp12snanthwNsOs5VNdnAJnDvXDMcb+iHy5s9njkRN/mT+oB5O3vBNbS86i2I1l77AvS5wZRukZkXrgViLj1TsAGvTnp+Zny4RikrxiIZeUdhTFeOfeqpZv/v1h09RHaXpgN7U2fdEEwjJBcD2oy1hchXkmVRIsBuyMcy66NbOhkSALoVKuxhmJ6JYNq4BDqgMKqE52rxWDkXBDjh6ESBpIwMGM13ZWh6KGCJibb+c24zvFgv8x91odBbiMZPsGyJkyh9khwrvWi5xXGNng== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR11MB3723.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(396003)(346002)(376002)(366004)(39860400002)(136003)(451199018)(5660300002)(8936002)(41300700001)(52536014)(55016003)(38070700005)(33656002)(86362001)(2906002)(38100700002)(9686003)(122000001)(478600001)(7696005)(71200400001)(53546011)(186003)(26005)(82960400001)(6506007)(66946007)(66556008)(66476007)(64756008)(66446008)(76116006)(6636002)(83380400001)(316002)(54906003)(110136005)(8676002)(4326008); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?JshwyImpT0tx/WszozSa6sWJYO1v4HYal60EP0HE7LsOlmZIlePFFNeDsY0h?= =?us-ascii?Q?7xATKi47eSBi46ScL3GBSH5Bpq59NcZRQgeE9W7cIR3aE57ClWjOjy2N0VDM?= =?us-ascii?Q?qZCU9bXvQqhar/0qkwJqrmaNUSF+9ACskDB+UDwak94MS4fiQirKtuwxzpDr?= =?us-ascii?Q?ExjFMHuGTE//mqLpXizY65y2tDfiwCHWBXyTO7h8Hv+QBB4EphlrQLfh3kiP?= =?us-ascii?Q?/WL8q4LEGqtQ4q1VM6zmxhG/WrTdDaJiy/MnA1qLBrHM4B+K2yu7wIYiB0U8?= =?us-ascii?Q?A4ZPgb1zwNviEyBc++Wy4BnL9p4rz+QE33JRF9L3/fZ9RUmQ1ke18e2dxQWP?= =?us-ascii?Q?GSW9oJIXUoHJ9B/DLBEwNoWsgeuwURiWCzeRSf5KcHZnrGfMPIfYpMzuY3lj?= =?us-ascii?Q?Ptln7cXooGKW3hrk8zeQJr5qYV1el4sOs34EybhbDvEJzSLATL2ZmN/LVdXK?= =?us-ascii?Q?f/YN5XCT+Q1Uwj/OSGbNf3I8O/n015njHQ0aBSoeDQjm3qwnGj9eMI3BnC8Z?= =?us-ascii?Q?4zQylqqJVzncgvZvHUvLhxIDpHuyCZXZ3vZ4SVbw1S5oT7Mw1OmniXMkdXKV?= =?us-ascii?Q?HXn1pcyZljZqJvJ94QyuSzg7mYMt4cp9CoTwP4sth6eviQwocBxe2ZcVpj6Q?= =?us-ascii?Q?H6tYuQzySQbw6Hl63+SjqeQ0zbXe5re5BxSZyGg8gkmn3NeweLt/e3YvDUPu?= =?us-ascii?Q?XsZTNXfGKGxr3d0no2GZWyoe7G9u4r7fWqVNaH/8cYfnV1cPxTSr/C6bXDWD?= =?us-ascii?Q?NbwLeTOG8p8mKTT/bHR+KUQrcy7u2wYMgypiWPvpEjrMNWQpbQ8nVcvOuTE0?= =?us-ascii?Q?YFUusWVtWCnjYAC9xVXxh5HWJ60InQwrKE5MG081kCazRyw7Kx5F5m4dHveK?= =?us-ascii?Q?2MvwYnpnUXAR7iKSZ54HKw7gamGEW3YhjtsjfeCubszRRGz64BtMBOLmpOqv?= =?us-ascii?Q?goqE2PKGB/WrVEY9NtbVW2bINJ5bwkVOugtzqKYelj2GkY80i2qKWzIIqnhf?= =?us-ascii?Q?cD7Wmfije9QaFfHctJC6+jSyq6u/2B+fz28nzwtisCpWaKnlqHRZtAvVNbmL?= =?us-ascii?Q?2LXjUY1unze4Gjm1oKfD406qKaAdAvG0xa3ewUa4qpIyEe1RZ3wCjkk6eFDf?= =?us-ascii?Q?il9drNqW82Yca4vDGkSJHiOtvjkc5NEAXbC3tgWCpCCS3vp0EVkxAWpb+uw5?= =?us-ascii?Q?vBH1J4eYAGxLuzomJp2wx5HYZg5Rw9fvvIWix19MxOXcyCJ6KZf0bn55ryPu?= =?us-ascii?Q?UixYKxojzy8/uyKKJyGssfZRUtP6muEoABF6BG1xe34wwlRbRjybtk2V6DCW?= =?us-ascii?Q?n4MERcNaF4O5Lfbtfz/OfNIGyVWA7zmLnPoqsCsHf23dWK/z/546aAVjDRF6?= =?us-ascii?Q?+1ITEJOG/xbXrwZKLX+xPElitrPrTJuR2J66RPC2Fxe9CMD3ZkUITcp1GuB/?= =?us-ascii?Q?lRKArrnjrs0HAz6QssXxAcLFgDQyzqFwg2gjv0heGCKox8a3tJWabOw58Mss?= =?us-ascii?Q?eUSePGni8sPAZNPEzy2JNvsV7dig/fCBe/OcM9ye4hkSwrJ+mTEPALCVKSOm?= =?us-ascii?Q?z+xUrte5EPNGhheNx0FL/AVyEYQZ+4zj1u+FKHq5?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3723.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f2f5d92-e1ad-4809-25ca-08db155f6a71 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Feb 2023 05:32:55.4777 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hlGmUnFzfMkvJ5L+yrQBXJggYvFYhrExuPFJpsIZGo6XI/opyqV1+qP8nM4+SEXywmRLbf+/XZARBfW1qW0EgA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5213 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Friday, February 17, 2023 23:18 > To: Guo, Junfeng ; Zhang, Qi Z > ; Wu, Jingjing ; > ferruh.yigit@amd.com; Xing, Beilei > Cc: dev@dpdk.org; Li, Xiaoyun ; Zhang, Helin > ; Rushil Gupta ; Jordan > Kimbrough ; Jeroen de Borst > ; nd ; Honnappa Nagarahalli > ; nd > Subject: RE: [RFC v3 06/10] net/gve: support basic Rx data path for DQO >=20 >=20 >=20 > > -----Original Message----- > > From: Junfeng Guo > > Sent: Friday, February 17, 2023 1:32 AM > > To: qi.z.zhang@intel.com; jingjing.wu@intel.com; > ferruh.yigit@amd.com; > > beilei.xing@intel.com > > Cc: dev@dpdk.org; xiaoyun.li@intel.com; helin.zhang@intel.com; > Junfeng > > Guo ; Rushil Gupta ; > Jordan > > Kimbrough ; Jeroen de Borst > > > Subject: [RFC v3 06/10] net/gve: support basic Rx data path for DQO > > > > Add basic Rx data path support for DQO. > > > > Signed-off-by: Junfeng Guo > > Signed-off-by: Rushil Gupta > > Signed-off-by: Jordan Kimbrough > > Signed-off-by: Jeroen de Borst > > --- > > drivers/net/gve/gve_ethdev.c | 1 + > > drivers/net/gve/gve_ethdev.h | 3 + > > drivers/net/gve/gve_rx_dqo.c | 128 > > +++++++++++++++++++++++++++++++++++ > > 3 files changed, 132 insertions(+) > > > > diff --git a/drivers/net/gve/gve_ethdev.c > b/drivers/net/gve/gve_ethdev.c > > index 1197194e41..1c9d272c2b 100644 > > --- a/drivers/net/gve/gve_ethdev.c > > +++ b/drivers/net/gve/gve_ethdev.c > > @@ -766,6 +766,7 @@ gve_dev_init(struct rte_eth_dev *eth_dev) > > eth_dev->tx_pkt_burst =3D gve_tx_burst; > > } else { > > eth_dev->dev_ops =3D &gve_eth_dev_ops_dqo; > > + eth_dev->rx_pkt_burst =3D gve_rx_burst_dqo; > > eth_dev->tx_pkt_burst =3D gve_tx_burst_dqo; > > } > > > > diff --git a/drivers/net/gve/gve_ethdev.h > b/drivers/net/gve/gve_ethdev.h > > index f39a0884f2..a8e0dd5f3d 100644 > > --- a/drivers/net/gve/gve_ethdev.h > > +++ b/drivers/net/gve/gve_ethdev.h > > @@ -377,6 +377,9 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev > *dev); > > void gve_stop_rx_queues_dqo(struct rte_eth_dev *dev); > > > > +uint16_t > > +gve_rx_burst_dqo(void *rxq, struct rte_mbuf **rx_pkts, uint16_t > > +nb_pkts); > > + > > uint16_t > > gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t > nb_pkts); > > > > diff --git a/drivers/net/gve/gve_rx_dqo.c > b/drivers/net/gve/gve_rx_dqo.c > > index 8236cd7b50..a281b237a4 100644 > > --- a/drivers/net/gve/gve_rx_dqo.c > > +++ b/drivers/net/gve/gve_rx_dqo.c > > @@ -5,6 +5,134 @@ > > #include "gve_ethdev.h" > > #include "base/gve_adminq.h" > > > > +static inline void > > +gve_rx_refill_dqo(struct gve_rx_queue *rxq) { > > + volatile struct gve_rx_desc_dqo *rx_buf_ring; > > + volatile struct gve_rx_desc_dqo *rx_buf_desc; > > + struct rte_mbuf *nmb[rxq->free_thresh]; > > + uint16_t nb_refill =3D rxq->free_thresh; > > + uint16_t nb_desc =3D rxq->nb_rx_desc; > > + uint16_t next_avail =3D rxq->bufq_tail; > > + struct rte_eth_dev *dev; > > + uint64_t dma_addr; > > + uint16_t delta; > > + int i; > > + > > + if (rxq->nb_rx_hold < rxq->free_thresh) > > + return; > > + > > + rx_buf_ring =3D rxq->rx_ring; > > + delta =3D nb_desc - next_avail; > > + if (unlikely(delta < nb_refill)) { > > + if (likely(rte_pktmbuf_alloc_bulk(rxq->mpool, nmb, delta) > =3D=3D > > 0)) { > > + for (i =3D 0; i < delta; i++) { > > + rx_buf_desc =3D &rx_buf_ring[next_avail + > i]; > > + rxq->sw_ring[next_avail + i] =3D nmb[i]; > > + dma_addr =3D > > rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i])); > > + rx_buf_desc->header_buf_addr =3D 0; > > + rx_buf_desc->buf_addr =3D dma_addr; > > + } > > + nb_refill -=3D delta; > > + next_avail =3D 0; > > + rxq->nb_rx_hold -=3D delta; > > + } else { > > + dev =3D &rte_eth_devices[rxq->port_id]; > > + dev->data->rx_mbuf_alloc_failed +=3D nb_desc - > > next_avail; > > + PMD_DRV_LOG(DEBUG, "RX mbuf alloc failed > > port_id=3D%u queue_id=3D%u", > > + rxq->port_id, rxq->queue_id); > > + return; > > + } > > + } > > + > > + if (nb_desc - next_avail >=3D nb_refill) { > > + if (likely(rte_pktmbuf_alloc_bulk(rxq->mpool, nmb, > nb_refill) > > =3D=3D 0)) { > > + for (i =3D 0; i < nb_refill; i++) { > > + rx_buf_desc =3D &rx_buf_ring[next_avail + > i]; > > + rxq->sw_ring[next_avail + i] =3D nmb[i]; > > + dma_addr =3D > > rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i])); > > + rx_buf_desc->header_buf_addr =3D 0; > > + rx_buf_desc->buf_addr =3D dma_addr; > > + } > > + next_avail +=3D nb_refill; > > + rxq->nb_rx_hold -=3D nb_refill; > > + } else { > > + dev =3D &rte_eth_devices[rxq->port_id]; > > + dev->data->rx_mbuf_alloc_failed +=3D nb_desc - > > next_avail; > > + PMD_DRV_LOG(DEBUG, "RX mbuf alloc failed > > port_id=3D%u queue_id=3D%u", > > + rxq->port_id, rxq->queue_id); > > + } > > + } > > + > > + rte_write32(next_avail, rxq->qrx_tail); > > + > > + rxq->bufq_tail =3D next_avail; > > +} > > + > > +uint16_t > > +gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t > > +nb_pkts) { > > + volatile struct gve_rx_compl_desc_dqo *rx_compl_ring; > > + volatile struct gve_rx_compl_desc_dqo *rx_desc; > > + struct gve_rx_queue *rxq; > > + struct rte_mbuf *rxm; > > + uint16_t rx_id_bufq; > > + uint16_t pkt_len; > > + uint16_t rx_id; > > + uint16_t nb_rx; > > + > > + nb_rx =3D 0; > > + rxq =3D rx_queue; > > + rx_id =3D rxq->rx_tail; > > + rx_id_bufq =3D rxq->next_avail; > > + rx_compl_ring =3D rxq->compl_ring; > > + > > + while (nb_rx < nb_pkts) { > > + rx_desc =3D &rx_compl_ring[rx_id]; > > + > > + /* check status */ > > + if (rx_desc->generation !=3D rxq->cur_gen_bit) > > + break; > From my experience with other PMDs, I think an IO read barrier is needed > here to ensure other parts of descriptors are not loaded before loading > rx_desc->generation. Yes, the memory barrier should be added here to prevent the code lines=20 being reordered by the compiler for some optimizations. We will refine this in the coming versions. Thanks a lot! >=20 > > + > > + if (unlikely(rx_desc->rx_error)) > > + continue; > > + > > + pkt_len =3D rx_desc->packet_len; > > + > > + rx_id++; > > + if (rx_id =3D=3D rxq->nb_rx_desc) { > > + rx_id =3D 0; > > + rxq->cur_gen_bit ^=3D 1; > > + } > > + > > + rxm =3D rxq->sw_ring[rx_id_bufq]; > > + rx_id_bufq++; > > + if (rx_id_bufq =3D=3D rxq->nb_rx_desc) > > + rx_id_bufq =3D 0; > > + rxq->nb_rx_hold++; > > + > > + rxm->pkt_len =3D pkt_len; > > + rxm->data_len =3D pkt_len; > > + rxm->port =3D rxq->port_id; > > + rxm->ol_flags =3D 0; > > + > > + rxm->ol_flags |=3D RTE_MBUF_F_RX_RSS_HASH; > > + rxm->hash.rss =3D rte_be_to_cpu_32(rx_desc->hash); > > + > > + rx_pkts[nb_rx++] =3D rxm; > > + } > > + > > + if (nb_rx > 0) { > > + rxq->rx_tail =3D rx_id; > > + if (rx_id_bufq !=3D rxq->next_avail) > > + rxq->next_avail =3D rx_id_bufq; > > + > > + gve_rx_refill_dqo(rxq); > > + } > > + > > + return nb_rx; > > +} > > + > > static inline void > > gve_release_rxq_mbufs_dqo(struct gve_rx_queue *rxq) { > > -- > > 2.34.1