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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3723.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6935ac9-f009-4495-70d6-08d95bb8d585 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Aug 2021 04:39:26.2738 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: //YM8BkgR2FS8/G7xBQlZSobQHXUCSnAb5sQVKIxGn1Dq3WITvWl6av8aoL4eCsighM5j0Z03zTlcIkzxj7hRA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3322 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 11/28] net/ice/base: add support for starting PHY in bypass mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Qi Z > Sent: Tuesday, August 10, 2021 10:51 > To: Yang, Qiming > Cc: Guo, Junfeng ; dev@dpdk.org; Zhang, Qi Z > ; Keller, Jacob E > Subject: [PATCH 11/28] net/ice/base: add support for starting PHY in > bypass mode >=20 > After starting the timestamping block, hardware begins calculating > precise offsets through a process of vernier calibration. This process > measures the effective phase offset of the various internal clocks used > in the PHY. >=20 > Once hardware completes these measurements, the > P_REG_TX_OV_STATUS and > P_REG_RX_OV_STATUS registers are updated to indicate that the > hardware > offset measurements are done. >=20 > This process does not happen immediately, but requires that at least one > packet be sent or received in order for the offset in that direction to > be calculated. >=20 > This poses a problem in some setups, because software expects the first > packet sent to be timestamped. This most often occurs if the clock time > is set by an application during startup. This set time command triggers > a PHY restart. Because of this, the timestamping block is reset, and > timestamps are not enabled until vernier calibration is complete. Since > this process won't complete until at least one packet is sent through > the PHY, timestamps of the very first packet sent will not be obtained. >=20 > This can result in the application failing due to missing timestamps. >=20 > To avoid this, allow starting the PHY in bypass mode. This mode enables > timestamps immediately, and skips adding the precise offset > measurement. > This reduces the accuracy of the timestamp slightly, but ensures that we > get a reasonable value for the first packet. >=20 > The driver can continue monitoring the P_REG_TX_OV_STATUS and > P_REG_RX_OV_STATUS registers and exit bypass mode once the total > calibration is completed. In this way, once calibration is complete, the > timestamps will have the precise offset, but we do not break > applications which expect to be able to timestamp immediately. >=20 > Signed-off-by: Jacob Keller > Signed-off-by: Qi Zhang > --- > drivers/net/ice/base/ice_ptp_hw.c | 84 > +++++++++++++++++++++++++++++++ > drivers/net/ice/base/ice_ptp_hw.h | 1 + > 2 files changed, 85 insertions(+) >=20 > -- > 2.26.2 Acked-by: Junfeng Guo Regards, Junfeng Guo