From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3750BA0C45; Wed, 6 Oct 2021 06:06:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1799D40685; Wed, 6 Oct 2021 06:06:27 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 3E4FA40140 for ; Wed, 6 Oct 2021 06:06:24 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10128"; a="213034502" X-IronPort-AV: E=Sophos;i="5.85,350,1624345200"; d="scan'208";a="213034502" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2021 21:06:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,350,1624345200"; d="scan'208";a="545117653" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by fmsmga004.fm.intel.com with ESMTP; 05 Oct 2021 21:06:22 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 5 Oct 2021 21:06:22 -0700 Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12 via Frontend Transport; Tue, 5 Oct 2021 21:06:22 -0700 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (104.47.73.42) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2242.12; Tue, 5 Oct 2021 21:06:22 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=C6GCaOH/VTxB4xbgNaeLSXTmC8UfOb7S5MtXIhCCtXmaXEQTCiMIWqfocbK1qilVn2BGPvHnqflPvWNF3FdGNAPw0T/dRzD1s2r09W/6C9AdK0EeBjJhQxUjZD4Xnt3gPtltgKrlvB+8jI8A3Lm4GSwozUeD4wiUhsS7WgeDZA7kIvqktc/DIg5SsoFg/8JBmIwbm6hQ6mGlPwNejlSSJjXA5tguP6jhLEV1LuHjzSkNb7dRkx5vu9gVs0SQtjZlVNIHYiZ+KPp6QBspvdUgnCfFoB/E3A7G7gdUVgMIU6LXjTb13gkqx7S6TkgUVyBoFyC1qbt3Ys7s759Aklc2zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zCJZCCVnsCvEYPHaM7WVqIHpDAEkghuEeX4trXhtG4E=; b=F3b7OpUMSVA/lz9eiryhBJPFp9+eJ3PW4ynXMTqMWQJwj+u9ZKWVDdxqOtnZ/4gTmp49f/x94FOSzI4A9DWWJLya6tkWbxvQR11fuuGfAhvuydeFPYWQ7ZI9Qxmbr9qpug8Sj0iJNI2gNmbEshBy1euDRLFMBPAwm9HJVRGfpBWpsvnevnNUKNMRVhv8q1uLsaFaKPKDWoPkBXSPXyDU85KpwRoKjLCRtYyjkltk+cYuZnL6QN9Xkd3PXHvFBUgdUdfDfN9IPYhzvb52rKoAVRjBqlropqKmqOxrFnVevjPepHEEMc74l1OoXTeEGQtqPFt9kXfXgJMd9oyZSADLSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zCJZCCVnsCvEYPHaM7WVqIHpDAEkghuEeX4trXhtG4E=; b=frxtaTR5a+eqTQ9ahGYbpSoW/Qk9M18metMoSLqpRaqNY4T3rmlRWyD2O9h1Ew44Dvy6oXuVfrTw6RnxcOzoNTMWX+DKlEfmq3WcrnWCpbi7UJXU0qC5kXkE3blG5bP62KQPOugh/zifEkQ5O8Ud8Dj1dIxHdb1kwyQgw52SB7A= Received: from DM6PR11MB3868.namprd11.prod.outlook.com (2603:10b6:5:19f::13) by DM5PR11MB1308.namprd11.prod.outlook.com (2603:10b6:3:e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.15; Wed, 6 Oct 2021 04:06:20 +0000 Received: from DM6PR11MB3868.namprd11.prod.outlook.com ([fe80::89fd:9564:349a:c59e]) by DM6PR11MB3868.namprd11.prod.outlook.com ([fe80::89fd:9564:349a:c59e%4]) with mapi id 15.20.4566.022; Wed, 6 Oct 2021 04:06:20 +0000 From: "Naga Harish K, S V" To: "Jayatheerthan, Jay" , "jerinj@marvell.com" CC: "dev@dpdk.org" Thread-Topic: [PATCH v5 4/5] eventdev/rx_adapter: implement per queue event buffer Thread-Index: AQHXuOJ8tV8IB94qOEeT3tF2kyQIE6vEBpbggAB25lCAAAKucIAA3K3g Date: Wed, 6 Oct 2021 04:06:20 +0000 Message-ID: References: <20210930082901.293541-1-s.v.naga.harish.k@intel.com> <20211004054108.3890018-1-s.v.naga.harish.k@intel.com> <20211004054108.3890018-4-s.v.naga.harish.k@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ccc27298-319c-409d-7b9a-08d9887ea74c x-ms-traffictypediagnostic: DM5PR11MB1308: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:792; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: pD5Zn2nb9QHesfyMKHzt69r8STaQq4LLvWHJNYNbXKO/bibnlOwAnhO8Rmp8jFqaioR/GzVcfvC1gpSDEGczyNl+moNHBhTKlXAG4TwyN6ch6bS+JQ3RoIUPuUYIpv+sRiab9+tjU5hDoQ67+dgVqxAOBQ5zIu7awWJ9ZYtZl696WUloW0PsybLzO7XjIAS7IW8TfC/MP7UhpHSF1D0Scn+P7cW3rDLyoZIaNp9hRuxSxaIgkjS0ou7wMAPZcwkIG5Q/kCGN95W2URe2APwGpMs+kU9XtjXnP3o9tJMArH7K1Ec5o40UEGCRZaek+WHssIfmHaRClPW/DQ6+0g1gwmvEf/FDJMhKvpuYGhs/KeZU7We5kCQNhC20g4bKDVvP/XLtSO3UihYIuhDsCIQEgp94ko3Aizl2IMXR5emDkErWAZuqDBFV81OUCPPWKNPxvB50x1Afa4xvJVWGtp30U7G1ZDpm9DumptIVA5H2FKbyE5B0zwr8wuRYM65ieyZ8L+ECHOI6ekiAYKpxdVmGqEsJOzNlKw9EBZXdkP4JOwbu4ki1YFOADPy6JdET65/LkJhgITjTwhQvJq2w2xp8MKC7i8h3Zo43eYGmjdNH24jv64G4yUV/VnS+f2AiQSJSTOdVyWkBN43xpTn6nopb4Xu0C0YwWWs0ugs+jlVZtDQUx5Na5soUdkCTBf1Z/67N2fzz3q/AVBC0bYbMINSiPA== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR11MB3868.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(6506007)(38100700002)(83380400001)(53546011)(186003)(7696005)(55236004)(38070700005)(76116006)(26005)(86362001)(64756008)(66446008)(66556008)(66476007)(66946007)(122000001)(8936002)(4326008)(5660300002)(8676002)(33656002)(52536014)(316002)(110136005)(30864003)(9686003)(55016002)(2906002)(508600001)(71200400001)(579004); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?MFVuoTC2ya/DMGm1COQR5V1qgh700KHJ2VnhYlSmO4i6ukyxrhh3vZrfz8hV?= =?us-ascii?Q?Eo4JRp+q9ZBd3Of/9/m0FmWY0d03dL2gb7rUO4Ta8RWMO76P958kEFEJYsgW?= =?us-ascii?Q?7QmH7doB1XNUl65FlTNljvpxZaARyK8oKWS39ExsHPETmOTWwp/dwDOjE3rM?= =?us-ascii?Q?tuu+2uenQWABFHXWyx/GJ6oUw19D5RH5LetwVbFtBEi02kvGmzvcZ3kJIctF?= =?us-ascii?Q?mXhnexQIDta8KEfnQTVYFmw2XWm9TMO+Ymbi3N73gnii7/HnmUCrebH8Oq+/?= =?us-ascii?Q?RzylIzmViNDQgoDaf9L6PpMaqOdJmfbkoeW4F+/VojTM9/DGm8Awqs++DpyM?= =?us-ascii?Q?vm8hUUe0ErAAGi2wT0vuT8QGyTh83H5XXm1bE8pSihgl/hth9ht+WNyDUP9Q?= =?us-ascii?Q?6PS24mgN4HvJczR06BJDhNTrK6MLWUAFpuMrXshwVETzXG3TjTpZw+8xvrYU?= =?us-ascii?Q?kenYjQWk3Es6o1MikgNQ3ibDg+VJ/80830o1R08kHhasEdatw8fT7lw5vQ0c?= =?us-ascii?Q?7Jy8hXaYqZYfX2YU4kxnJ9Ob1FShO2AlOFxob76LII3MUnYaNO3Ky9/dRSfl?= =?us-ascii?Q?ufn4epAdmCIC/4p/SELhahAFV14fXKaum/h9tHuaaqapOIyuAiw/S0yqOmRX?= =?us-ascii?Q?aTMDDdgejnQHY/0zr/wNIH+uZMKq52eMJbgyjzrWF1RwuOJerO2Nl1ecroF7?= =?us-ascii?Q?YW00R8UXZqbjAfZCCQpftMyVAO/OK3h1w0AhHBszgm7yUsT8NzhY7jzgluyX?= =?us-ascii?Q?OkEvhKJykI8b0spbBYOmaWo4qGVSZZK81sIQLnWBGtVaY8NH28krkqnNZzc9?= =?us-ascii?Q?6xqhAL3h8NB4VhvV1h0ciqa+Recw7lnsc/ApUVjYhOiLVmBmTy0FBlToD1SV?= =?us-ascii?Q?hl1pAXSMhVAQYWhqjjkMSbptNpmoI6g3+whsd2VmsxEapJyqHCkcKjowiP8X?= =?us-ascii?Q?7H47QqMeUDGozDTeaJb1FiwuOmBpE+KkcUhbBIPXHPcbf8RsK0nGIxsCxN2x?= =?us-ascii?Q?pWIY4miNNxq3SRV4I+PK108sY25d9g/GKEBMQzp8ANkat3QPRdeWAuUC664H?= =?us-ascii?Q?axqbcB2w/sLG0RmkvBJKbM99L1Mgdeet2VEoKM/jLDWgxfO6akj0iR/Yt237?= =?us-ascii?Q?ctmV8kDLTHT5islBFTMFZuvbeQOXibKAGU96UNiUek/4z0Ux88lznITZKuV8?= =?us-ascii?Q?eNuQwZSGbRl8A5CBLJYC2WylClcZraGZ9UkY2eXw3N6rjbwgeAior9oVdlme?= =?us-ascii?Q?NVr/GjtfNDouW/ID8GCWE0caK5tfiTX4hqOvt9GILlg7oj4d76OdbAHnk1VQ?= =?us-ascii?Q?MutuPdI+2YT8/2fMxg5n6dOu?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3868.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ccc27298-319c-409d-7b9a-08d9887ea74c X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Oct 2021 04:06:20.2210 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Sn/SB86xvhRlomurhYNuYfReG0qKVOq+fAXtp7cmO181ItVs0zr22BXHjjjxX5QfxoNeC2QRT93qeSCny08Y3prJe09j+NrTsmdg3BQdd60= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1308 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5 4/5] eventdev/rx_adapter: implement per queue event buffer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jay, > -----Original Message----- > From: Jayatheerthan, Jay > Sent: Tuesday, October 5, 2021 8:31 PM > To: Naga Harish K, S V ; jerinj@marvell.com > Cc: dev@dpdk.org > Subject: RE: [PATCH v5 4/5] eventdev/rx_adapter: implement per queue > event buffer >=20 > > -----Original Message----- > > From: Naga Harish K, S V > > Sent: Tuesday, October 5, 2021 8:18 PM > > To: Jayatheerthan, Jay ; > > jerinj@marvell.com > > Cc: dev@dpdk.org > > Subject: RE: [PATCH v5 4/5] eventdev/rx_adapter: implement per queue > > event buffer > > > > Hi Jay, > > > > > -----Original Message----- > > > From: Jayatheerthan, Jay > > > Sent: Tuesday, October 5, 2021 1:26 PM > > > To: Naga Harish K, S V ; > > > jerinj@marvell.com > > > Cc: dev@dpdk.org > > > Subject: RE: [PATCH v5 4/5] eventdev/rx_adapter: implement per queue > > > event buffer > > > > > > > -----Original Message----- > > > > From: Naga Harish K, S V > > > > Sent: Monday, October 4, 2021 11:11 AM > > > > To: jerinj@marvell.com; Jayatheerthan, Jay > > > > > > > > Cc: dev@dpdk.org > > > > Subject: [PATCH v5 4/5] eventdev/rx_adapter: implement per queue > > > event > > > > buffer > > > > > > > > this patch implement the per queue event buffer with required > > > > validations. > > > > > > > > Signed-off-by: Naga Harish K S V > > > > --- > > > > lib/eventdev/rte_event_eth_rx_adapter.c | 187 > > > > +++++++++++++++++------- > > > > 1 file changed, 138 insertions(+), 49 deletions(-) > > > > > > > > diff --git a/lib/eventdev/rte_event_eth_rx_adapter.c > > > > b/lib/eventdev/rte_event_eth_rx_adapter.c > > > > index 606db241b8..b61af0e75e 100644 > > > > --- a/lib/eventdev/rte_event_eth_rx_adapter.c > > > > +++ b/lib/eventdev/rte_event_eth_rx_adapter.c > > > > @@ -102,10 +102,12 @@ struct rte_event_eth_rx_adapter { > > > > uint8_t rss_key_be[RSS_KEY_SIZE]; > > > > /* Event device identifier */ > > > > uint8_t eventdev_id; > > > > - /* Per ethernet device structure */ > > > > - struct eth_device_info *eth_devices; > > > > /* Event port identifier */ > > > > uint8_t event_port_id; > > > > + /* Flag indicating per rxq event buffer */ > > > > + bool use_queue_event_buf; > > > > + /* Per ethernet device structure */ > > > > + struct eth_device_info *eth_devices; > > > > /* Lock to serialize config updates with service function */ > > > > rte_spinlock_t rx_lock; > > > > /* Max mbufs processed in any service function invocation */ @@ > > > > -241,6 +243,7 @@ struct eth_rx_queue_info { > > > > uint32_t flow_id_mask; /* Set to ~0 if app provides flow id > > > else 0 */ > > > > uint64_t event; > > > > struct eth_rx_vector_data vector_data; > > > > + struct rte_eth_event_enqueue_buffer *event_buf; > > > > }; > > > > > > > > static struct rte_event_eth_rx_adapter **event_eth_rx_adapter; @@ > > > > -767,10 +770,9 @@ rxa_enq_block_end_ts(struct > > > rte_event_eth_rx_adapter > > > > *rx_adapter, > > > > > > > > /* Enqueue buffered events to event device */ static inline > > > > uint16_t -rxa_flush_event_buffer(struct rte_event_eth_rx_adapter > > > > *rx_adapter) > > > > +rxa_flush_event_buffer(struct rte_event_eth_rx_adapter > *rx_adapter, > > > > + struct rte_eth_event_enqueue_buffer *buf) > > > > { > > > > - struct rte_eth_event_enqueue_buffer *buf =3D > > > > - &rx_adapter->event_enqueue_buffer; > > > > struct rte_event_eth_rx_adapter_stats *stats =3D &rx_adapter->sta= ts; > > > > uint16_t count =3D buf->last ? buf->last - buf->head : buf->count= ; > > > > > > > > @@ -888,15 +890,14 @@ rxa_buffer_mbufs(struct > > > rte_event_eth_rx_adapter *rx_adapter, > > > > uint16_t eth_dev_id, > > > > uint16_t rx_queue_id, > > > > struct rte_mbuf **mbufs, > > > > - uint16_t num) > > > > + uint16_t num, > > > > + struct rte_eth_event_enqueue_buffer *buf) > > > > { > > > > uint32_t i; > > > > struct eth_device_info *dev_info =3D > > > > &rx_adapter- > > > >eth_devices[eth_dev_id]; > > > > struct eth_rx_queue_info *eth_rx_queue_info =3D > > > > &dev_info- > > > >rx_queue[rx_queue_id]; > > > > - struct rte_eth_event_enqueue_buffer *buf =3D > > > > - &rx_adapter- > > > >event_enqueue_buffer; > > > > uint16_t new_tail =3D buf->tail; > > > > uint64_t event =3D eth_rx_queue_info->event; > > > > uint32_t flow_id_mask =3D eth_rx_queue_info->flow_id_mask; @@ - > > > 995,11 > > > > +996,10 @@ rxa_eth_rx(struct rte_event_eth_rx_adapter > *rx_adapter, > > > > uint16_t queue_id, > > > > uint32_t rx_count, > > > > uint32_t max_rx, > > > > - int *rxq_empty) > > > > + int *rxq_empty, > > > > + struct rte_eth_event_enqueue_buffer *buf) > > > > { > > > > struct rte_mbuf *mbufs[BATCH_SIZE]; > > > > - struct rte_eth_event_enqueue_buffer *buf =3D > > > > - &rx_adapter- > > > >event_enqueue_buffer; > > > > struct rte_event_eth_rx_adapter_stats *stats =3D > > > > &rx_adapter->stats; > > > > uint16_t n; > > > > @@ -1012,7 +1012,7 @@ rxa_eth_rx(struct rte_event_eth_rx_adapter > > > *rx_adapter, > > > > */ > > > > while (rxa_pkt_buf_available(buf)) { > > > > if (buf->count >=3D BATCH_SIZE) > > > > - rxa_flush_event_buffer(rx_adapter); > > > > + rxa_flush_event_buffer(rx_adapter, buf); > > > > > > > > stats->rx_poll_count++; > > > > n =3D rte_eth_rx_burst(port_id, queue_id, mbufs, > > > BATCH_SIZE); @@ > > > > -1021,14 +1021,14 @@ rxa_eth_rx(struct rte_event_eth_rx_adapter > > > *rx_adapter, > > > > *rxq_empty =3D 1; > > > > break; > > > > } > > > > - rxa_buffer_mbufs(rx_adapter, port_id, queue_id, mbufs, n); > > > > + rxa_buffer_mbufs(rx_adapter, port_id, queue_id, mbufs, n, > > > buf); > > > > nb_rx +=3D n; > > > > if (rx_count + nb_rx > max_rx) > > > > break; > > > > } > > > > > > > > if (buf->count > 0) > > > > - rxa_flush_event_buffer(rx_adapter); > > > > + rxa_flush_event_buffer(rx_adapter, buf); > > > > > > > > return nb_rx; > > > > } > > > > @@ -1169,7 +1169,7 @@ rxa_intr_ring_dequeue(struct > > > rte_event_eth_rx_adapter *rx_adapter) > > > > ring_lock =3D &rx_adapter->intr_ring_lock; > > > > > > > > if (buf->count >=3D BATCH_SIZE) > > > > - rxa_flush_event_buffer(rx_adapter); > > > > + rxa_flush_event_buffer(rx_adapter, buf); > > > > > > > > while (rxa_pkt_buf_available(buf)) { > > > > struct eth_device_info *dev_info; @@ -1221,7 +1221,7 @@ > > > > rxa_intr_ring_dequeue(struct > > > rte_event_eth_rx_adapter *rx_adapter) > > > > continue; > > > > n =3D rxa_eth_rx(rx_adapter, port, i, nb_rx, > > > > rx_adapter->max_nb_rx, > > > > - &rxq_empty); > > > > + &rxq_empty, buf); > > > > nb_rx +=3D n; > > > > > > > > enq_buffer_full =3D !rxq_empty && n =3D=3D 0; > > > @@ -1242,7 +1242,7 @@ > > > > rxa_intr_ring_dequeue(struct rte_event_eth_rx_adapter *rx_adapter) > > > > } else { > > > > n =3D rxa_eth_rx(rx_adapter, port, queue, nb_rx, > > > > rx_adapter->max_nb_rx, > > > > - &rxq_empty); > > > > + &rxq_empty, buf); > > > > rx_adapter->qd_valid =3D !rxq_empty; > > > > nb_rx +=3D n; > > > > if (nb_rx > rx_adapter->max_nb_rx) @@ -1273,13 > > > +1273,12 @@ > > > > rxa_poll(struct rte_event_eth_rx_adapter *rx_adapter) { > > > > uint32_t num_queue; > > > > uint32_t nb_rx =3D 0; > > > > - struct rte_eth_event_enqueue_buffer *buf; > > > > + struct rte_eth_event_enqueue_buffer *buf =3D NULL; > > > > uint32_t wrr_pos; > > > > uint32_t max_nb_rx; > > > > > > > > wrr_pos =3D rx_adapter->wrr_pos; > > > > max_nb_rx =3D rx_adapter->max_nb_rx; > > > > - buf =3D &rx_adapter->event_enqueue_buffer; > > > > > > > > /* Iterate through a WRR sequence */ > > > > for (num_queue =3D 0; num_queue < rx_adapter->wrr_len; > > > num_queue++) { > > > > @@ -1287,24 +1286,36 @@ rxa_poll(struct rte_event_eth_rx_adapter > > > *rx_adapter) > > > > uint16_t qid =3D rx_adapter->eth_rx_poll[poll_idx].eth_rx_qid; > > > > uint16_t d =3D rx_adapter->eth_rx_poll[poll_idx].eth_dev_id; > > > > > > > > + if (rx_adapter->use_queue_event_buf) { > > > > + struct eth_device_info *dev_info =3D > > > > + &rx_adapter->eth_devices[d]; > > > > + buf =3D dev_info->rx_queue[qid].event_buf; > > > > + } else > > > > + buf =3D &rx_adapter->event_enqueue_buffer; > > > > + > > > > /* Don't do a batch dequeue from the rx queue if there isn't > > > > * enough space in the enqueue buffer. > > > > */ > > > > if (buf->count >=3D BATCH_SIZE) > > > > - rxa_flush_event_buffer(rx_adapter); > > > > + rxa_flush_event_buffer(rx_adapter, buf); > > > > if (!rxa_pkt_buf_available(buf)) { > > > > - rx_adapter->wrr_pos =3D wrr_pos; > > > > - return nb_rx; > > > > + if (rx_adapter->use_queue_event_buf) > > > > + goto poll_next_entry; > > > > + else { > > > > + rx_adapter->wrr_pos =3D wrr_pos; > > > > + return nb_rx; > > > > + } > > > > } > > > > > > > > nb_rx +=3D rxa_eth_rx(rx_adapter, d, qid, nb_rx, max_nb_rx, > > > > - NULL); > > > > + NULL, buf); > > > > if (nb_rx > max_nb_rx) { > > > > rx_adapter->wrr_pos =3D > > > > (wrr_pos + 1) % rx_adapter->wrr_len; > > > > break; > > > > } > > > > > > > > +poll_next_entry: > > > > if (++wrr_pos =3D=3D rx_adapter->wrr_len) > > > > wrr_pos =3D 0; > > > > } > > > > @@ -1315,12 +1326,18 @@ static void rxa_vector_expire(struct > > > > eth_rx_vector_data *vec, void *arg) { > > > > struct rte_event_eth_rx_adapter *rx_adapter =3D arg; > > > > - struct rte_eth_event_enqueue_buffer *buf =3D > > > > - &rx_adapter->event_enqueue_buffer; > > > > + struct rte_eth_event_enqueue_buffer *buf =3D NULL; > > > > struct rte_event *ev; > > > > > > > > + if (rx_adapter->use_queue_event_buf) { > > > > + struct eth_device_info *dev_info =3D > > > > + &rx_adapter->eth_devices[vec->port]; > > > > + buf =3D dev_info->rx_queue[vec->queue].event_buf; > > > > + } else > > > > + buf =3D &rx_adapter->event_enqueue_buffer; > > > > + > > > > > > The above code to get the buffer can be made an inline function > > > since it is needed in more than one place. > > > > Added new inline function to get event buffer pointer in v6 patch set. > > > > > > > > > if (buf->count) > > > > - rxa_flush_event_buffer(rx_adapter); > > > > + rxa_flush_event_buffer(rx_adapter, buf); > > > > > > > > if (vec->vector_ev->nb_elem =3D=3D 0) > > > > return; > > > > @@ -1947,9 +1964,16 @@ rxa_sw_del(struct > rte_event_eth_rx_adapter > > > *rx_adapter, > > > > rx_adapter->num_rx_intr -=3D intrq; > > > > dev_info->nb_rx_intr -=3D intrq; > > > > dev_info->nb_shared_intr -=3D intrq && sintrq; > > > > + if (rx_adapter->use_queue_event_buf) { > > > > + struct rte_eth_event_enqueue_buffer *event_buf =3D > > > > + dev_info->rx_queue[rx_queue_id].event_buf; > > > > + rte_free(event_buf->events); > > > > + rte_free(event_buf); > > > > + dev_info->rx_queue[rx_queue_id].event_buf =3D NULL; > > > > + } > > > > } > > > > > > > > -static void > > > > +static int > > > > rxa_add_queue(struct rte_event_eth_rx_adapter *rx_adapter, > > > > struct eth_device_info *dev_info, > > > > int32_t rx_queue_id, > > > > @@ -1961,15 +1985,21 @@ rxa_add_queue(struct > > > rte_event_eth_rx_adapter *rx_adapter, > > > > int intrq; > > > > int sintrq; > > > > struct rte_event *qi_ev; > > > > + struct rte_eth_event_enqueue_buffer *new_rx_buf =3D NULL; > > > > + uint16_t eth_dev_id =3D dev_info->dev->data->port_id; > > > > + int ret; > > > > > > > > if (rx_queue_id =3D=3D -1) { > > > > uint16_t nb_rx_queues; > > > > uint16_t i; > > > > > > > > nb_rx_queues =3D dev_info->dev->data->nb_rx_queues; > > > > - for (i =3D 0; i < nb_rx_queues; i++) > > > > - rxa_add_queue(rx_adapter, dev_info, i, conf); > > > > - return; > > > > + for (i =3D 0; i < nb_rx_queues; i++) { > > > > + ret =3D rxa_add_queue(rx_adapter, dev_info, i, conf); > > > > + if (ret) > > > > + return ret; > > > > + } > > > > + return 0; > > > > } > > > > > > > > pollq =3D rxa_polled_queue(dev_info, rx_queue_id); @@ -2032,6 > > > +2062,37 > > > > @@ rxa_add_queue(struct rte_event_eth_rx_adapter *rx_adapter, > > > > dev_info->next_q_idx =3D 0; > > > > } > > > > } > > > > + > > > > + if (!rx_adapter->use_queue_event_buf) > > > > + return 0; > > > > + > > > > + new_rx_buf =3D rte_zmalloc_socket("rx_buffer_meta", > > > > + sizeof(*new_rx_buf), 0, > > > > + rte_eth_dev_socket_id(eth_dev_id)); > > > > + if (new_rx_buf =3D=3D NULL) { > > > > + RTE_EDEV_LOG_ERR("Failed to allocate event buffer meta > > > for " > > > > + "dev_id: %d queue_id: %d", > > > > + eth_dev_id, rx_queue_id); > > > > + return -ENOMEM; > > > > + } > > > > + > > > > + new_rx_buf->events_size =3D RTE_ALIGN(conf->event_buf_size, > > > BATCH_SIZE); > > > > + new_rx_buf->events_size +=3D (2 * BATCH_SIZE); > > > > + new_rx_buf->events =3D rte_zmalloc_socket("rx_buffer", > > > > + sizeof(struct rte_event) * > > > > + new_rx_buf->events_size, 0, > > > > + rte_eth_dev_socket_id(eth_dev_id)); > > > > + if (new_rx_buf->events =3D=3D NULL) { > > > > + rte_free(new_rx_buf); > > > > + RTE_EDEV_LOG_ERR("Failed to allocate event buffer for " > > > > + "dev_id: %d queue_id: %d", > > > > + eth_dev_id, rx_queue_id); > > > > + return -ENOMEM; > > > > + } > > > > + > > > > + queue_info->event_buf =3D new_rx_buf; > > > > + > > > > + return 0; > > > > } > > > > > > > > static int rxa_sw_add(struct rte_event_eth_rx_adapter > > > > *rx_adapter, @@ > > > > -2060,6 +2121,16 @@ static int rxa_sw_add(struct > > > rte_event_eth_rx_adapter *rx_adapter, > > > > temp_conf.servicing_weight =3D 1; > > > > } > > > > queue_conf =3D &temp_conf; > > > > + > > > > + if (queue_conf->servicing_weight =3D=3D 0 && > > > > + rx_adapter->use_queue_event_buf) { > > > > + > > > > + RTE_EDEV_LOG_ERR("Use of queue level event > > > buffer " > > > > + "not supported for interrupt queues > > > " > > > > + "dev_id: %d queue_id: %d", > > > > + eth_dev_id, rx_queue_id); > > > > + return -EINVAL; > > > > + } > > > > } > > > > > > > > nb_rx_queues =3D dev_info->dev->data->nb_rx_queues; > > > > @@ -2139,7 +2210,9 @@ static int rxa_sw_add(struct > > > > rte_event_eth_rx_adapter *rx_adapter, > > > > > > > > > > > > > > > > - rxa_add_queue(rx_adapter, dev_info, rx_queue_id, queue_conf); > > > > + ret =3D rxa_add_queue(rx_adapter, dev_info, rx_queue_id, > > > queue_conf); > > > > + if (ret) > > > > + goto err_free_rxqueue; > > > > rxa_calc_wrr_sequence(rx_adapter, rx_poll, rx_wrr); > > > > > > > > rte_free(rx_adapter->eth_rx_poll); > > > > @@ -2160,7 +2233,7 @@ static int rxa_sw_add(struct > > > rte_event_eth_rx_adapter *rx_adapter, > > > > rte_free(rx_poll); > > > > rte_free(rx_wrr); > > > > > > > > - return 0; > > > > + return ret; > > > > } > > > > > > > > static int > > > > @@ -2286,20 +2359,26 @@ rxa_create(uint8_t id, uint8_t dev_id, > > > > rx_adapter->eth_devices[i].dev =3D &rte_eth_devices[i]; > > > > > > > > /* Rx adapter event buffer allocation */ > > > > - buf =3D &rx_adapter->event_enqueue_buffer; > > > > - buf->events_size =3D RTE_ALIGN(rxa_params->event_buf_size, > > > BATCH_SIZE); > > > > - > > > > - events =3D rte_zmalloc_socket(rx_adapter->mem_name, > > > > - buf->events_size * sizeof(*events), > > > > - 0, socket_id); > > > > - if (events =3D=3D NULL) { > > > > - RTE_EDEV_LOG_ERR("Failed to allocate mem for event > > > buffer\n"); > > > > - rte_free(rx_adapter->eth_devices); > > > > - rte_free(rx_adapter); > > > > - return -ENOMEM; > > > > - } > > > > + rx_adapter->use_queue_event_buf =3D rxa_params- > > > >use_queue_event_buf; > > > > + > > > > + if (!rx_adapter->use_queue_event_buf) { > > > > + buf =3D &rx_adapter->event_enqueue_buffer; > > > > + buf->events_size =3D RTE_ALIGN(rxa_params- > > > >event_buf_size, > > > > + BATCH_SIZE); > > > > + > > > > + events =3D rte_zmalloc_socket(rx_adapter->mem_name, > > > > + buf->events_size * > > > sizeof(*events), > > > > + 0, socket_id); > > > > + if (events =3D=3D NULL) { > > > > + RTE_EDEV_LOG_ERR("Failed to allocate memory " > > > > + "for adapter event buffer"); > > > > + rte_free(rx_adapter->eth_devices); > > > > + rte_free(rx_adapter); > > > > + return -ENOMEM; > > > > + } > > > > > > > > - rx_adapter->event_enqueue_buffer.events =3D events; > > > > + rx_adapter->event_enqueue_buffer.events =3D events; > > > > + } > > > > > > > > event_eth_rx_adapter[id] =3D rx_adapter; > > > > > > > > @@ -2327,6 +2406,7 @@ > rte_event_eth_rx_adapter_create_ext(uint8_t > > > id, > > > > uint8_t dev_id, > > > > > > > > /* use default values for adapter params */ > > > > rxa_params.event_buf_size =3D ETH_EVENT_BUFFER_SIZE; > > > > + rxa_params.use_queue_event_buf =3D false; > > > > > > > > return rxa_create(id, dev_id, &rxa_params, conf_cb, conf_arg); > > > > } > > > @@ > > > > -2347,9 +2427,9 @@ > > > rte_event_eth_rx_adapter_create_with_params(uint8_t id, uint8_t > > > dev_id, > > > > if (rxa_params =3D=3D NULL) { > > > > rxa_params =3D &temp_params; > > > > rxa_params->event_buf_size =3D ETH_EVENT_BUFFER_SIZE; > > > > - } > > > > - > > > > - if (rxa_params->event_buf_size =3D=3D 0) > > > > + rxa_params->use_queue_event_buf =3D false; > > > > + } else if ((!rxa_params->use_queue_event_buf && > > > > + rxa_params->event_buf_size =3D=3D 0)) >=20 > My earlier comment applies here. > Another error case is configuring both - rxa_params->use_queue_event_buf > =3D=3D true and rxa_params->event_buf_size !=3D 0. >=20 Added this additional validation in V7 patch set > > > > return -EINVAL; > > > > > > > > pc =3D rte_malloc(NULL, sizeof(*pc), 0); @@ -2418,7 +2498,8 @@ > > > > rte_event_eth_rx_adapter_free(uint8_t id) > > > > if (rx_adapter->default_cb_arg) > > > > rte_free(rx_adapter->conf_arg); > > > > rte_free(rx_adapter->eth_devices); > > > > - rte_free(rx_adapter->event_enqueue_buffer.events); > > > > + if (!rx_adapter->use_queue_event_buf) > > > > + rte_free(rx_adapter->event_enqueue_buffer.events); > > > > rte_free(rx_adapter); > > > > event_eth_rx_adapter[id] =3D NULL; > > > > > > > > @@ -2522,6 +2603,14 @@ > rte_event_eth_rx_adapter_queue_add(uint8_t > > > id, > > > > return -EINVAL; > > > > } > > > > > > > > + if ((rx_adapter->use_queue_event_buf && > > > > + queue_conf->event_buf_size =3D=3D 0) || > > > > + (!rx_adapter->use_queue_event_buf && > > > > + queue_conf->event_buf_size !=3D 0)) { > > > > + RTE_EDEV_LOG_ERR("Invalid Event buffer size for the > > > queue"); > > > > + return -EINVAL; > > > > + } > > > > + > > > > > > Another error case is configuring both - > > > rx_adapter->use_queue_event_buf =3D true and queue_conf- > >event_buf_size !=3D 0. > > > > This is valid case. >=20 > My bad, wrong place. See above. >=20 > > > > > > > > > dev_info =3D &rx_adapter->eth_devices[eth_dev_id]; > > > > > > > > if (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT) { > > > > -- > > > > 2.25.1