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x-forefront-prvs: 03449D5DD1 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(376002)(366004)(39860400002)(346002)(396003)(136003)(199004)(316002)(71200400001)(8936002)(81166006)(8676002)(2906002)(55016002)(110136005)(26005)(81156014)(478600001)(9686003)(186003)(6506007)(5660300002)(76116006)(66556008)(52536014)(86362001)(7696005)(33656002)(66476007)(66446008)(64756008)(66946007); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR12MB3721; H:DM6PR12MB2987.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: cOB8fnpoX5GWWFn4KD6rvIxVDJAE7/zA0yHlK7zcu7eBbTgYzaEOfoDab295gNafwLP2ClC6htFDOXZnn15umJ50dt+BA33pBQg031g+9BEBCMpIO1coWhIfO+trRnlCm9IjeoEjb3m6jhX/TO5eBGgBqD9sabxYJNQJnPP0n8AKEeL/F3kWM/Vx9usjRH62FbEv89B9EFr/tpfCIzSKadOOLgHs3xXwcp+bncSANNsH7q0I9ZciWq8WUKhWy9khDM5AvSEHwIKcPMrfLK507TBE2BKYGldHv4r7rQQzt2j7i8aD0G2CrLOydFf40R3LfY2igbEW8m0gZngG5EtIpZ3d9XjGtR8TRRG5gPEw64XMEtQW3L1WVewlQaUugXNM/UqAcH89R4Lk/P4PO0HJFpAcP7xxXaWO+Tg9ML1+Ggw72APIoEANImCQjtMcJ1Fj x-ms-exchange-antispam-messagedata: wEuJzCRsYrn4tBDeN7Izmu7vvu1bcgaECZaLQKkMFf1/0Du8bG1+/k1vRcdrdxfZa3LeVkIJdc6lULaF4dGJKf94HQYjRBgUEMZ71Au71pbWcJOg2GqdgsHq5hE8L4FWbo9rXkQpkAbJW+A2EKSlrQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ab3695fd-a6a6-40f9-4091-08d7c95d8e84 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Mar 2020 03:53:15.5158 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 76JIL7fiLmWodRuO8NtyRn4qA/NwddjvZ0v7TPuUBQFEiagFGcF1RfYT/oOhP1zzE5V3FrbphJIZwwaEaPIj9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3721 Subject: Re: [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" [AMD Public Use] For series, Acked-by: Ravi Kumar =20 >From: Amaranath Somalapuram > >Adding api for flow_ctrl_get and flow_ctrl_set. >By default axgbe driver flow control is disabled. >Adding dpdk flow control to set water high and low. > >Signed-off-by: Amaranath Somalapuram >--- > drivers/net/axgbe/axgbe_ethdev.c | 84 ++++++++++++++++++++++++++++++++ d= rivers/net/axgbe/axgbe_ethdev.h | 11 +++++ > 2 files changed, 95 insertions(+) > >diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_et= hdev.c >index 00974e737..867c4744f 100644 >--- a/drivers/net/axgbe/axgbe_ethdev.c >+++ b/drivers/net/axgbe/axgbe_ethdev.c >@@ -47,6 +47,10 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *de= v, static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); static int= axgbe_dev_info_get(struct rte_eth_dev *dev, > struct rte_eth_dev_info *dev_info); >+static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, >+ struct rte_eth_fc_conf *fc_conf); >+static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, >+ struct rte_eth_fc_conf *fc_conf); >=20 > struct axgbe_xstats { > char name[RTE_ETH_XSTATS_NAME_SIZE]; >@@ -174,6 +178,8 @@ static const struct eth_dev_ops axgbe_eth_dev_ops =3D = { > .rx_queue_release =3D axgbe_dev_rx_queue_release, > .tx_queue_setup =3D axgbe_dev_tx_queue_setup, > .tx_queue_release =3D axgbe_dev_tx_queue_release, >+ .flow_ctrl_get =3D axgbe_flow_ctrl_get, >+ .flow_ctrl_set =3D axgbe_flow_ctrl_set, > }; >=20 > static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -843,6 +849,84 @@= axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_i= nfo) > return 0; > } >=20 >+static int >+axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf=20 >+*fc_conf) { >+ struct axgbe_port *pdata =3D dev->data->dev_private; >+ struct xgbe_fc_info fc =3D pdata->fc; >+ unsigned int reg, reg_val =3D 0; >+ >+ reg =3D MAC_Q0TFCR; >+ reg_val =3D AXGMAC_IOREAD(pdata, reg); >+ fc.low_water[0] =3D AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); >+ fc.high_water[0] =3D AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD)= ; >+ fc.pause_time[0] =3D AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); >+ fc.autoneg =3D pdata->pause_autoneg; >+ >+ if (pdata->rx_pause && pdata->tx_pause) >+ fc.mode =3D RTE_FC_FULL; >+ else if (pdata->rx_pause) >+ fc.mode =3D RTE_FC_RX_PAUSE; >+ else if (pdata->tx_pause) >+ fc.mode =3D RTE_FC_TX_PAUSE; >+ else >+ fc.mode =3D RTE_FC_NONE; >+ >+ fc_conf->high_water =3D (1024 + (fc.low_water[0] << 9)) / 1024; >+ fc_conf->low_water =3D (1024 + (fc.high_water[0] << 9)) / 1024; >+ fc_conf->pause_time =3D fc.pause_time[0]; >+ fc_conf->send_xon =3D fc.send_xon; >+ fc_conf->mode =3D fc.mode; >+ >+ return 0; >+} >+ >+static int >+axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf=20 >+*fc_conf) { >+ struct axgbe_port *pdata =3D dev->data->dev_private; >+ struct xgbe_fc_info fc =3D pdata->fc; >+ unsigned int reg, reg_val =3D 0; >+ reg =3D MAC_Q0TFCR; >+ >+ pdata->pause_autoneg =3D fc_conf->autoneg; >+ pdata->phy.pause_autoneg =3D pdata->pause_autoneg; >+ fc.send_xon =3D fc_conf->send_xon; >+ AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, >+ AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); >+ AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, >+ AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); >+ AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); >+ AXGMAC_IOWRITE(pdata, reg, reg_val); >+ fc.mode =3D fc_conf->mode; >+ >+ if (fc.mode =3D=3D RTE_FC_FULL) { >+ pdata->tx_pause =3D 1; >+ pdata->rx_pause =3D 1; >+ } else if (fc.mode =3D=3D RTE_FC_RX_PAUSE) { >+ pdata->tx_pause =3D 0; >+ pdata->rx_pause =3D 1; >+ } else if (fc.mode =3D=3D RTE_FC_TX_PAUSE) { >+ pdata->tx_pause =3D 1; >+ pdata->rx_pause =3D 0; >+ } else { >+ pdata->tx_pause =3D 0; >+ pdata->rx_pause =3D 0; >+ } >+ >+ if (pdata->tx_pause !=3D (unsigned int)pdata->phy.tx_pause) >+ pdata->hw_if.config_tx_flow_control(pdata); >+ >+ if (pdata->rx_pause !=3D (unsigned int)pdata->phy.rx_pause) >+ pdata->hw_if.config_rx_flow_control(pdata); >+ >+ pdata->hw_if.config_flow_control(pdata); >+ pdata->phy.tx_pause =3D pdata->tx_pause; >+ pdata->phy.rx_pause =3D pdata->rx_pause; >+ >+ return 0; >+} >+ > static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { > unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgb= e/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h >index a1083b17b..436d780c9 100644 >--- a/drivers/net/axgbe/axgbe_ethdev.h >+++ b/drivers/net/axgbe/axgbe_ethdev.h >@@ -485,6 +485,16 @@ struct axgbe_mmc_stats { > uint64_t rxwatchdogerror; > }; >=20 >+/* Flow control parameters */ >+struct xgbe_fc_info { >+ uint32_t high_water[AXGBE_PRIORITY_QUEUES]; >+ uint32_t low_water[AXGBE_PRIORITY_QUEUES]; >+ uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; >+ uint16_t send_xon; >+ enum rte_eth_fc_mode mode; >+ uint8_t autoneg; >+}; >+ > /* > * Structure to store private data for each port. > */ >@@ -625,6 +635,7 @@ struct axgbe_port { > uint32_t rx_csum_enable; >=20 > struct axgbe_mmc_stats mmc_stats; >+ struct xgbe_fc_info fc; > }; >=20 > void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); >-- >2.17.1 >