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From: Slava Ovsiienko <viacheslavo@nvidia.com>
To: fengchengwen <fengchengwen@huawei.com>,
	NBU-Contact-Thomas Monjalon <thomas@monjalon.net>,
	"ferruh.yigit@intel.com" <ferruh.yigit@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH 1/2] net/mlx4: fix memory barrier incorrectly placed
Date: Tue, 11 May 2021 12:02:29 +0000	[thread overview]
Message-ID: <DM6PR12MB37536D843B1CBB616CD1E22ADF539@DM6PR12MB3753.namprd12.prod.outlook.com> (raw)
In-Reply-To: <1481eb69-6ff6-4575-6640-b511bb82b6f7@huawei.com>

> -----Original Message-----
> From: fengchengwen <fengchengwen@huawei.com>
> Sent: Tuesday, May 11, 2021 14:09
> To: Slava Ovsiienko <viacheslavo@nvidia.com>; NBU-Contact-Thomas
> Monjalon <thomas@monjalon.net>; ferruh.yigit@intel.com
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 1/2] net/mlx4: fix memory barrier incorrectly
> placed
> 
> 
> 
> On 2021/5/11 17:23, Slava Ovsiienko wrote:
> >> -----Original Message-----
> >> From: dev <dev-bounces@dpdk.org> On Behalf Of Chengwen Feng
> >> Sent: Monday, May 10, 2021 15:06
> >> To: NBU-Contact-Thomas Monjalon <thomas@monjalon.net>;
> >> ferruh.yigit@intel.com
> >> Cc: dev@dpdk.org
> >> Subject: [dpdk-dev] [PATCH 1/2] net/mlx4: fix memory barrier
> >> incorrectly placed
> >>
> >> The memory barrier is used to ensure that the response is returned
> >> only after the Tx/Rx function is set, it should place after the Rx/Tx
> function is set.
> >>
> >> Fixes: 0203d33a1059 ("net/mlx4: support secondary process")
> >> Cc: stable@dpdk.org
> >>
> >> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
> > Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> >
> >
> > Hi, Chengwen
> >
> > Nice catch, thank you for the patches.
> > Just out of curiosity - did we meet the real issue with this ineffective
> barrier?
> >
> > With best regards,
> > Slava
> >
> 
> Hi, Slava
> 
> It's just a theoretical analysis that's possible, I think it should never happen in
> practice.
> We found this problem when checking the memory barrier of the hns3 driver
> (ps: the implementation of hns3 mp is somewhat similar to that of mlx), this
> memory barrier got us a little confused, so we fix it to make it just less
> confusing.

OK, thank you for the answer.

With best regards,
Slava


> 
> Best Regards
> 
> >> ---
> >>  drivers/net/mlx4/mlx4_mp.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/mlx4/mlx4_mp.c b/drivers/net/mlx4/mlx4_mp.c
> >> index ddf7bdb..8fcfb54 100644
> >> --- a/drivers/net/mlx4/mlx4_mp.c
> >> +++ b/drivers/net/mlx4/mlx4_mp.c
> >> @@ -126,7 +126,6 @@ mp_secondary_handle(const struct rte_mp_msg
> >> *mp_msg, const void *peer)
> >>  	switch (param->type) {
> >>  	case MLX4_MP_REQ_START_RXTX:
> >>  		INFO("port %u starting datapath", dev->data->port_id);
> >> -		rte_mb();
> >>  		dev->tx_pkt_burst = mlx4_tx_burst;
> >>  		dev->rx_pkt_burst = mlx4_rx_burst;  #ifdef
> >> HAVE_IBV_MLX4_UAR_MMAP_OFFSET @@ -144,6 +143,7 @@
> >> mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void
> >> *peer)
> >>  			}
> >>  		}
> >>  #endif
> >> +		rte_mb();
> >>  		mp_init_msg(dev, &mp_res, param->type);
> >>  		res->result = 0;
> >>  		ret = rte_mp_reply(&mp_res, peer);
> >> --
> >> 2.8.1
> >
> >
> > .
> >


  reply	other threads:[~2021-05-11 12:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-10 12:06 [dpdk-dev] [PATCH 0/2] bugfix for mlx4 and mlx5 Chengwen Feng
2021-05-10 12:06 ` [dpdk-dev] [PATCH 1/2] net/mlx4: fix memory barrier incorrectly placed Chengwen Feng
2021-05-11  9:23   ` Slava Ovsiienko
2021-05-11 11:08     ` fengchengwen
2021-05-11 12:02       ` Slava Ovsiienko [this message]
2021-05-10 12:06 ` [dpdk-dev] [PATCH 2/2] net/mlx5: " Chengwen Feng
2021-05-11  9:24   ` Slava Ovsiienko
2021-05-10 12:12 ` [dpdk-dev] [PATCH 0/2] bugfix for mlx4 and mlx5 Thomas Monjalon
2021-05-12  8:54 ` Thomas Monjalon

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