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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3753.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: be403525-f95d-4f43-8570-08daa088ffee X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Sep 2022 13:05:49.5852 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: udeRoP70sIG2tlL06hosDPkRMy9+6ehr3KosnTuDguNRXeITopPyfPCNSprPysEypdHhoUE75I5PIoTZ3PUpPA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5148 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Dariusz Sosnowski > Sent: Monday, September 19, 2022 19:37 > To: Matan Azrad ; Slava Ovsiienko > Cc: dev@dpdk.org > Subject: [PATCH 4/7] net/mlx5: allow hairpin Tx queue in RTE memory >=20 > This patch adds a capability to place hairpin Tx queue in host memory > managed by DPDK. This capability is equivalent to storing hairpin SQ's WQ > buffer in host memory. >=20 > Hairpin Tx queue creation is extended with allocating a memory buffer of > proper size (calculated from required number of packets and WQE BB size > advertised in HCA capabilities). >=20 > force_memory flag of hairpin queue configuration is also supported. > If it is set and: >=20 > - allocation of memory buffer fails, > - or hairpin SQ creation fails, >=20 > then device start will fail. If it is unset, PMD will fallback to creatin= g > the hairpin SQ with WQ buffer located in unlocked device memory. >=20 > Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko