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charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] DPDK 21.11 NVIDIA Mellanox Roadmap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Below is NVIDIA Mellanox's roadmap for DPDK21.11, on which we are currently= working: ethdev new APIs: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D [1] Introduce an optimization in memory/performance for the case of scaled-= up interfaces. Motivation: An application (e.g. OVS) polls all representors = queues. Each queue contains descriptors, and each descriptor is utilizing m= bufs. As the number of interfaces grows (e.g. 1k Scalable Functions(SFs) ),= the memory footprint grows dramatically (#queues X depth_of_queue X mbufs_= memory X 1k ports), and CPU usage becomes inefficient, due to cache evictio= ns between the queue contexts. The new optimization will aggregate the queu= es into a single one. It will reduce the number of entities to poll as well= as reduce the memory footprint, allowing streamlined and efficient process= ing with much less cache evictions. rte_flow new APIs: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D [2] Extend rte_flow api to support the definition of flexible parsers. Motivation: NVIDIA Mellanox NICs supports flexible parser con= figuration, and we've made use of that capability within the mlx5 PMD befor= e. Now we are exposing an API to allow applications to configure the NIC to= support matching over custom/non-supported protocol. With that configurati= on done, matching can be applied to traffic using that protocol. mlx5 PMD updates: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D mlx5 PMD will support the rte_flow update changes listed above and below [3]Extend mlx5 PMD capability to support up to 512 interfaces(VFs,SFs) Motivation: Allow applications like VDPA to utilize larger nu= mber of interfaces. Another example would be in the DPU in which hundreds o= f applications can be supported using SFs rte_mempool updates: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D [4] Improve memory registration and sharing between drivers Motivation: In a Data Processing Unit (DPU) environment, ther= e's a need to share data between the host memory and the DPU/arm memory to = facilitate fast data transfer of different drivers like regex and network t= hat operates on the same physical device. For that, we are refactoring the = memory registration and sharing method so that the memory region registrati= on will be abstracted through that method (not left for each driver to do) = which will enable sharing of a memory region between host and DPU/arm memor= y subset. Together with this change, wewill also optimize the huge page ini= tialization and cross NUMA memory registration to speed up application star= t-up time. testpmd updates: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D testpmd updated to support the changes listed above