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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM8PR11MB5605.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 68968dce-0990-4328-195e-08d9d43f4578 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jan 2022 13:44:06.2226 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5CI5OhcVIAi/A8MenMpsDZdDuAMU4iQNpvGnnWcV5SRmTkHjcMumzlRzZLjHJWIOKqnRaWUboMwa9ikxJwVaNA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR11MB5637 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Bruce, > what values for the write_idx and ids_returned vars give this error, and = how > does masking help? I'd expect masking to increase the number of times the > function returns zero, rather than decreasing it. Here are the values from the idxd dump: dev_capa: 0x500000051 - mem2mem sva handles_errors copy fill max_vchans_supported: 1 nb_vchans_configured: 1 silent_mode: off IDXD Private Data =3D=3D Portal: 0x7ffff7ffb000 Config: { ring_size: 4096 } Batch ring (sz =3D 129, max_batches =3D 128): 62370 62402 62434 62466 62498 62530 62562 62594 62626 62658 62690= 62722 62754 62786 62818 62850 62882 62914 62946 62978 63010 630= 42 63074 6 3106 63138 63170 63202 63234 63266 63298 63330 63362 63394 63426 = 63458 63490 63522 63554 63586 63618 63650 63682 63714 63746 6377= 8 63810 63842 63874 63906 63938 63970 64002 64034 64066 64098 64= 13 0 64162 64194 64226 64258 64290 64322 64354 64386 64418 64450 64= 482 64514 64546 64578 64610 64642 64674 64706 64738 64770 64802 = 64834 64866 64898 64930 64962 64994 65026 65058 65090 65122 65154= =20 65186 65218 65250 65282 65314 65346 65378 65410 65442 65474 65506= [rd ptr] 2 [wr ptr] 61442 61474 61506 61538 61570 61602 61634 616= 66 61698 61730 61762 61794 61826 61858 61890 61922 61954 61986 6= 20 18 62050 62082 62114 62146 62178 62210 62242 62274 62306 62338 Curr batch: start =3D 2, size =3D 0 IDS: avail =3D 65506, returned: 65506 max packets per batch from hw: 1024 batches left: 127, ring space left: 4064 idxd->desc_ring_mask: 4095, used_space: 4128, used_space: 4128, idxd->max_b= atch_size: 1024, idxd->batch_size: 0 write_idx: 4098, idxd->batch_idx_read: 98, idxd->batch_idx_write: 99, idxd-= >desc_ring_mask - used_space: 65503 relevant data from above: write_idx: 4098 , IDS returned: 65506, idxd->desc_ring_mask: 4095 without the fix : used_space =3D write_idx - idxd->ids_returned; (4098 - 65506) =3D -61408 with fix:=20 used_space =3D (write_idx - idxd->ids_returned)& idxd->desc_ring_mask; (409= 8 - 65506)&4095 =3D 32=20 which seems to match the rd ptr and wr ptr. Thanks and regards, Sunil