From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id D15B4CBE0 for ; Fri, 17 Jun 2016 00:22:35 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 16 Jun 2016 15:22:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,481,1459839600"; d="scan'208";a="999297025" Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by orsmga002.jf.intel.com with ESMTP; 16 Jun 2016 15:22:34 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.183]) by IRSMSX106.ger.corp.intel.com ([169.254.8.145]) with mapi id 14.03.0248.002; Thu, 16 Jun 2016 23:22:32 +0100 From: "De Lara Guarch, Pablo" To: "Shen, Wei1" , "dev@dpdk.org" CC: "Ananyev, Konstantin" , "stephen@networkplumber.org" , "Tai, Charlie" , "Maciocco, Christian" , "Gobriel, Sameh" Thread-Topic: [PATCH v3] rte_hash: add scalable multi-writer insertion w/ Intel TSX Thread-Index: AQHRyByBqnCQEJzTG0qCO8JWpBTzMJ/sl9gAgAASfyA= Date: Thu, 16 Jun 2016 22:22:32 +0000 Message-ID: References: <1466052753-69632-1-git-send-email-wei1.shen@intel.com> <1466115254-114498-1-git-send-email-wei1.shen@intel.com> <1466115254-114498-2-git-send-email-wei1.shen@intel.com> In-Reply-To: <1466115254-114498-2-git-send-email-wei1.shen@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTA2OWFlMzktYjkyYi00NzFjLTkyNWEtYzdiZjhiMTQ5MDA4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ikw0cm5Ydlp6dnRtUHpzaXVCK1pQdmlyc1pYbytONUdHb29ITWJuM2wxd2s9In0= x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] rte_hash: add scalable multi-writer insertion w/ Intel TSX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Jun 2016 22:22:36 -0000 > -----Original Message----- > From: Shen, Wei1 > Sent: Thursday, June 16, 2016 11:14 PM > To: dev@dpdk.org > Cc: De Lara Guarch, Pablo; Ananyev, Konstantin; > stephen@networkplumber.org; Tai, Charlie; Maciocco, Christian; Gobriel, > Sameh; Shen, Wei1 > Subject: [PATCH v3] rte_hash: add scalable multi-writer insertion w/ Inte= l TSX >=20 > This patch introduced scalable multi-writer Cuckoo Hash insertion > based on a split Cuckoo Search and Move operation using Intel > TSX. It can do scalable hash insertion with 22 cores with little > performance loss and negligible TSX abortion rate. >=20 > * Added an extra rte_hash flag definition to switch default single writer > Cuckoo Hash behavior to multiwriter. > - If HTM is available, it would use hardware feature for concurrency. > - If HTM is not available, it would fall back to spinlock. >=20 > * Created a rte_cuckoo_hash_x86.h file to hold all x86-arch related > cuckoo_hash functions. And rte_cuckoo_hash.c uses compile time flag to > select x86 file or other platform-specific implementations. While HTM c= heck > is still done at runtime (same idea with > RTE_HASH_EXTRA_FLAGS_TRANS_MEM_SUPPORT) >=20 > * Moved rte_hash private struct definitions to rte_cuckoo_hash.h, to allo= w > rte_cuckoo_hash_x86.h or future platform dependent functions to include= . >=20 > * Following new functions are created for consistent names when new > platform > TM support are added. > - rte_hash_cuckoo_move_insert_mw_tm: do insertion with bucket > movement. > - rte_hash_cuckoo_insert_mw_tm: do insertion without bucket movement. >=20 > * One extra multi-writer test case is added. >=20 > Signed-off-by: Shen Wei > Signed-off-by: Sameh Gobriel Acked-by: Pablo de Lara