From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id AD3C5903; Sat, 28 Feb 2015 15:33:40 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 28 Feb 2015 06:33:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,667,1418112000"; d="scan'208";a="460681478" Received: from pgsmsx107.gar.corp.intel.com ([10.221.44.105]) by FMSMGA003.fm.intel.com with ESMTP; 28 Feb 2015 06:27:39 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by PGSMSX107.gar.corp.intel.com (10.221.44.105) with Microsoft SMTP Server (TLS) id 14.3.195.1; Sat, 28 Feb 2015 22:33:35 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.161]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.209]) with mapi id 14.03.0195.001; Sat, 28 Feb 2015 22:33:34 +0800 From: "Zhang, Helin" To: lhffjzh , 'Thomas Monjalon' Thread-Topic: [dpdk-dev] Why only rx queue "0" can receive network packet by i40e NIC Thread-Index: AdBSe++3hYejogolSOOWUQUj62OZbAAdqO6QAARY9PAAAJniMAAXRa5w Date: Sat, 28 Feb 2015 14:33:34 +0000 Message-ID: References: <1416936405-25333-1-git-send-email-ssujith@cisco.com> <03fb01d05269$fe8d2110$fba76330$@com> <1566601.Xkl8jJDb44@xps13> <046801d052f8$9090a530$b1b1ef90$@com> <049801d0530f$b866bce0$293436a0$@com> In-Reply-To: <049801d0530f$b866bce0$293436a0$@com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" , "maintainers@dpdk.org" Subject: Re: [dpdk-dev] Why only rx queue "0" can receive network packet by i40e NIC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Feb 2015 14:33:41 -0000 Good to know that! > -----Original Message----- > From: lhffjzh [mailto:lhffjzh@126.com] > Sent: Saturday, February 28, 2015 12:34 PM > To: Zhang, Helin; 'Thomas Monjalon' > Cc: dev@dpdk.org; maintainers@dpdk.org > Subject: RE: [dpdk-dev] Why only rx queue "0" can receive network packet = by > i40e NIC >=20 > Hi Helin, >=20 > Thanks a lot for your great help, all of rx queue received network packet= after I > update rss_hf from "ETH_RSS_IP" to " ETH_RSS_PROTO_MASK ". >=20 > static struct rte_eth_conf port_conf =3D { > .rxmode =3D { > .mq_mode =3D ETH_MQ_RX_RSS, > .max_rx_pkt_len =3D ETHER_MAX_LEN, > .split_hdr_size =3D 0, > .header_split =3D 0, /**< Header Split disabled */ > .hw_ip_checksum =3D 1, /**< IP checksum offload enabled */ > .hw_vlan_filter =3D 0, /**< VLAN filtering disabled */ > .jumbo_frame =3D 0, /**< Jumbo Frame Support disabled */ > .hw_strip_crc =3D 0, /**< CRC stripped by hardware */ > }, > .rx_adv_conf =3D { > .rss_conf =3D { > .rss_key =3D NULL, > .rss_hf =3D ETH_RSS_PROTO_MASK, > }, > }, > .txmode =3D { > .mq_mode =3D ETH_MQ_TX_NONE, > }, > .fdir_conf.mode =3D RTE_FDIR_MODE_SIGNATURE, }; >=20 >=20 > Regards, > Haifeng >=20 > -----Original Message----- > From: Zhang, Helin [mailto:helin.zhang@intel.com] > Sent: Saturday, February 28, 2015 11:18 AM > To: lhffjzh; 'Thomas Monjalon' > Cc: dev@dpdk.org; maintainers@dpdk.org > Subject: RE: [dpdk-dev] Why only rx queue "0" can receive network packet = by > i40e NIC >=20 > Hi Haifeng >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of lhffjzh > > Sent: Saturday, February 28, 2015 9:48 AM > > To: 'Thomas Monjalon' > > Cc: dev@dpdk.org; maintainers@dpdk.org > > Subject: Re: [dpdk-dev] Why only rx queue "0" can receive network > > packet > by > > i40e NIC > > > > Hi Thomas, > > > > Thanks very much for your reminder, you give me many help in this mail > list. > > > > The issue with detailed information just as below. but I don't know > > who is > the > > dpdk i40e maintainers? is maintainers@dpdk.org? > > > > Hardware list: > > 2 i40e 40G NICs > > Xeon E5-2670 v2(10 cores) > > 32G memory > > > > I loopback 2 i40e NICs by QSFP cable, one NIC send UDP network packet > > by DPDK, and another for receiving. I bind 4 processor's logical cores > > with 4 > rx > > queue "0,1,2,3" on receiving NIC, when I start to send packet, only rx > queue > > "0" > > can receive > > the UDP packet, the others queue always receive nothing. but it is > > work > well on > > ixgbe 10G NICs, I can receive network packet from all rx queues. does > anyone > > kindly know why? > Could you help to list the DPDK version you are using now? > Two possible reasons: > 1. UDP rss is not enabled on your board correctly. > I40e has different rss flags from ixgbe, so I am wondering if you use it > correctly. > In addition, this will be unified from 2.0. So I care about the DPDK ver= sion. > 2. The UDP stream is occasionally hit the hash key of queue 0. > You'd better to try to send your UDP stream with random 5-tuples, to get > the > hash value hit different queues randomly. >=20 > Regards, > Helin >=20 > > > > > > Regards, > > Haifeng > > > > -----Original Message----- > > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > > Sent: Friday, February 27, 2015 6:55 PM > > To: lhffjzh > > Cc: dev@dpdk.org > > Subject: Re: Why only rx queue "0" can receive network packet by i40e > > NIC > > > > 2015-02-27 16:47, lhffjzh: > > > Hi All, > > > > > > We use 4 cores loop 4 rx queues on one i40e port, but only rx queue "= 0" > > can > > > receive network packet, do anyone kindly know why? BTW, all of > > > network packet has same destination ip address but has more than 200 > > > different source ip address. > > > > It's possible that you don't have any answer for 2 reasons: > > - you replied in a thread dedicated to Cisco enic questions > > - you didn't describe your usage enough to understand your problem > > > > I suggest to use the button "new email" instead of "reply all" to > > start a new question with enough details. > > > > Did you noticed you put some Cisco guys in CC instead of putting the > > Intel responsible for i40e (see MAINTAINERS file)? > > >=20