From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 9EC9C9AA0 for ; Tue, 24 Mar 2015 02:54:23 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 23 Mar 2015 18:54:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,455,1422950400"; d="scan'208";a="696677241" Received: from pgsmsx107.gar.corp.intel.com ([10.221.44.105]) by fmsmga002.fm.intel.com with ESMTP; 23 Mar 2015 18:54:21 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by PGSMSX107.gar.corp.intel.com (10.221.44.105) with Microsoft SMTP Server (TLS) id 14.3.224.2; Tue, 24 Mar 2015 09:54:20 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.149]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.36]) with mapi id 14.03.0224.002; Tue, 24 Mar 2015 09:54:19 +0800 From: "Zhang, Helin" To: "xuelin.shi@freescale.com" , "thomas.monjalon@6wind.com" Thread-Topic: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe PCI and CPU Thread-Index: AQHQRdAFb4xtZfyCEku0BAmWuYzD1J0rHX1g Date: Tue, 24 Mar 2015 01:54:18 +0000 Message-ID: References: <1423637385-25077-1-git-send-email-xuelin.shi@freescale.com> In-Reply-To: <1423637385-25077-1-git-send-email-xuelin.shi@freescale.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe PCI and CPU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Mar 2015 01:54:24 -0000 Hi Xuelin > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of > xuelin.shi@freescale.com > Sent: Wednesday, February 11, 2015 2:50 PM > To: thomas.monjalon@6wind.com > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixg= be > PCI and CPU >=20 > From: Xuelin Shi >=20 > make sure: > CPU read from ixgbe with IXGBE_LE32_TO_CPUS > CPU write to ixgbe with IXGBE_CPU_TO_LE32 >=20 > otherwise, there is endian issue for ixgbe on BIG_ENDIAN CPU. I got your concern, but you modified in wrong places. Source files in linux= /kni/ will be compiled into a kernel module. So the endian issue will be handled quite= well by kernel functions like writel, readl, etc. And your modifications are not needed at= all for KNI kernel module. But I think the similar changes are needed in librte_pmd_e1000, librte_pmd_= ixgbe, librte_pmd_i40e, etc. Regards, Helin >=20 > Signed-off-by: Xuelin Shi > --- > .../linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h | 24 > ++++++++++++++++------ > 1 file changed, 18 insertions(+), 6 deletions(-) >=20 > diff --git a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > index d161600..0612632 100644 > --- a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > +++ b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > @@ -53,6 +53,16 @@ >=20 > #undef ASSERT >=20 > +static inline uint32_t ixgbe_read_addr(volatile void* addr) { > + return IXGBE_LE32_TO_CPUS(*((volatile uint32_t *)addr)); } > + > +static inline uint32_t ixgbe_write_addr(u32 value, volatile void* addr) > +{ > + return writel(IXGBE_CPU_TO_LE32(value), addr); } > + > #ifdef DBG > #define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A) > #else > @@ -91,19 +101,20 @@ > default: \ > break; \ > } \ > - writel((value), ((a)->hw_addr + (reg))); \ > + ixgbe_write_addr((value), ((a)->hw_addr + (reg))); \ > } while (0) > #else > -#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + > (reg))) > +#define IXGBE_WRITE_REG(a, reg, value) \ > + ixgbe_write_addr((value), ((a)->hw_addr + (reg))) > #endif >=20 > -#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg)) > +#define IXGBE_READ_REG(a, reg) ixgbe_read_addr((a)->hw_addr + (reg)) >=20 > #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \ > - writel((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) > + ixgbe_write_addr((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) >=20 > #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \ > - readl((a)->hw_addr + (reg) + ((offset) << 2))) > + ixgbe_read_addr((a)->hw_addr + (reg) + ((offset) << 2))) >=20 > #ifndef writeq > #define writeq(val, addr) do { writel((u32) (val), addr); \ > @@ -111,7 +122,8 @@ > } while (0); > #endif >=20 > -#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + > (reg))) > +#define IXGBE_WRITE_REG64(a, reg, value) \ > + writeq((cpu_to_le64(value)), ((a)->hw_addr + (reg))) >=20 > #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) > struct ixgbe_hw; > -- > 1.9.1