From: "Zhang, Helin" <helin.zhang@intel.com>
To: "Wu, Jingjing" <jingjing.wu@intel.com>,
"thomas.monjalon@6wind.com" <thomas.monjalon@6wind.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] i40e: move PCI device ids to driver
Date: Mon, 11 Jul 2016 06:19:36 +0000 [thread overview]
Message-ID: <F35DEAC7BCE34641BA9FAC6BCA4A12E717D953B3@SHSMSX103.ccr.corp.intel.com> (raw)
In-Reply-To: <1468209673-21685-1-git-send-email-jingjing.wu@intel.com>
Hi Jingjing
I'd suggest to add a new header file in each PMD to define what we defined in rte_pci_dev_ids.h.
There was a patch set submitted several months ago, like that.
Regards,
Helin
> -----Original Message-----
> From: Wu, Jingjing
> Sent: Monday, July 11, 2016 12:01 PM
> To: thomas.monjalon@6wind.com
> Cc: Zhang, Helin <helin.zhang@intel.com>; dev@dpdk.org; Wu, Jingjing
> <jingjing.wu@intel.com>
> Subject: [PATCH] i40e: move PCI device ids to driver
>
> move PCI device ids from rte_pci_dev_ids.h to driver.
>
> Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
> ---
> drivers/net/i40e/i40e_ethdev.c | 21 ++++++--
> drivers/net/i40e/i40e_ethdev_vf.c | 9 ++--
> lib/librte_eal/common/include/rte_pci_dev_ids.h | 71 -------------------------
> 3 files changed, 24 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index 31c2e11..e75d911 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -454,9 +454,24 @@ static void i40e_set_default_mac_addr(struct
> rte_eth_dev *dev, static int i40e_dev_mtu_set(struct rte_eth_dev *dev,
> uint16_t mtu);
>
> static const struct rte_pci_id pci_id_i40e_map[] = { -#define
> RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
> -#include "rte_pci_dev_ids.h"
> -{ .vendor_id = 0, /* sentinel */ },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID,
> I40E_DEV_ID_1G_BASE_T_X722) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID,
> I40E_DEV_ID_10G_BASE_T_X722) },
> + { .vendor_id = 0, /* sentinel */ },
> };
>
> static const struct eth_dev_ops i40e_eth_dev_ops = { diff --git
> a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
> index 31547db..a616ae0 100644
> --- a/drivers/net/i40e/i40e_ethdev_vf.c
> +++ b/drivers/net/i40e/i40e_ethdev_vf.c
> @@ -1110,9 +1110,12 @@ i40evf_get_link_status(struct rte_eth_dev *dev,
> struct rte_eth_link *link) }
>
> static const struct rte_pci_id pci_id_i40evf_map[] = { -#define
> RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
> -#include "rte_pci_dev_ids.h"
> -{ .vendor_id = 0, /* sentinel */ },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
> + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
> + { .vendor_id = 0, /* sentinel */ },
> };
>
> static inline int
> diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h
> b/lib/librte_eal/common/include/rte_pci_dev_ids.h
> index af39fbb..9a06313 100644
> --- a/lib/librte_eal/common/include/rte_pci_dev_ids.h
> +++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h
> @@ -74,8 +74,6 @@
> * RTE_PCI_DEV_ID_DECL_IGBVF
> * RTE_PCI_DEV_ID_DECL_IXGBE
> * RTE_PCI_DEV_ID_DECL_IXGBEVF
> - * RTE_PCI_DEV_ID_DECL_I40E
> - * RTE_PCI_DEV_ID_DECL_I40EVF
> * RTE_PCI_DEV_ID_DECL_VIRTIO
> * at the time when this file is included.
> *
> @@ -117,14 +115,6 @@
> #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) #endif
>
> -#ifndef RTE_PCI_DEV_ID_DECL_I40E
> -#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) -#endif
> -
> -#ifndef RTE_PCI_DEV_ID_DECL_I40EVF
> -#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) -#endif
> -
> #ifndef RTE_PCI_DEV_ID_DECL_VIRTIO
> #define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) #endif @@ -528,52 +518,6
> @@ RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL,
> IXGBE_DEV_ID_X550EM_X_KR)
> RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL,
> IXGBE_DEV_ID_82599_BYPASS) #endif
>
> -/*************** Physical I40E devices from i40e_type.h
> *****************/
> -
> -#define I40E_DEV_ID_SFP_XL710 0x1572
> -#define I40E_DEV_ID_QEMU 0x1574
> -#define I40E_DEV_ID_KX_B 0x1580
> -#define I40E_DEV_ID_KX_C 0x1581
> -#define I40E_DEV_ID_QSFP_A 0x1583
> -#define I40E_DEV_ID_QSFP_B 0x1584
> -#define I40E_DEV_ID_QSFP_C 0x1585
> -#define I40E_DEV_ID_10G_BASE_T 0x1586
> -#define I40E_DEV_ID_20G_KR2 0x1587
> -#define I40E_DEV_ID_20G_KR2_A 0x1588
> -#define I40E_DEV_ID_10G_BASE_T4 0x1589
> -#define I40E_DEV_ID_25G_B 0x158A
> -#define I40E_DEV_ID_25G_SFP28 0x158B
> -#define I40E_DEV_ID_X722_A0 0x374C
> -#define I40E_DEV_ID_KX_X722 0x37CE
> -#define I40E_DEV_ID_QSFP_X722 0x37CF
> -#define I40E_DEV_ID_SFP_X722 0x37D0
> -#define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
> -#define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
> -#define I40E_DEV_ID_SFP_I_X722 0x37D3
> -#define I40E_DEV_ID_QSFP_I_X722 0x37D4
> -
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_SFP_XL710)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QEMU)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_B)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_C)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_A)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_B)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_C)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_10G_BASE_T)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_20G_KR2)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_20G_KR2_A)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_10G_BASE_T4)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_25G_B)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_25G_SFP28)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_X722_A0)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_X722)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_X722)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_SFP_X722)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_1G_BASE_T_X722)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_10G_BASE_T_X722)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_SFP_I_X722)
> -RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_QSFP_I_X722)
> -
> /*************** Physical FM10K devices from fm10k_type.h
> ***************/
>
> #define FM10K_DEV_ID_PF 0x15A4
> @@ -618,19 +562,6 @@
> RTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL,
> IXGBE_DEV_ID_X550EM_A_VF_HV)
> RTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL,
> IXGBE_DEV_ID_X550EM_X_VF)
> RTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL,
> IXGBE_DEV_ID_X550EM_X_VF_HV)
>
> -/****************** Virtual I40E devices from i40e_type.h
> ********************/
> -
> -#define I40E_DEV_ID_VF 0x154C
> -#define I40E_DEV_ID_VF_HV 0x1571
> -#define I40E_DEV_ID_X722_A0_VF 0x374D
> -#define I40E_DEV_ID_X722_VF 0x37CD
> -#define I40E_DEV_ID_X722_VF_HV 0x37D9
> -
> -RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF)
> -RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF_HV)
> -RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_X722_A0_VF)
> -RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_X722_VF)
> -RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL,
> I40E_DEV_ID_X722_VF_HV)
>
> /****************** Virtio devices from virtio.h ******************/
>
> @@ -737,8 +668,6 @@
> RTE_PCI_DEV_ID_DECL_BNXT(PCI_VENDOR_ID_BROADCOM,
> BROADCOM_DEV_ID_57314) #undef RTE_PCI_DEV_ID_DECL_IGBVF #undef
> RTE_PCI_DEV_ID_DECL_IXGBE #undef RTE_PCI_DEV_ID_DECL_IXGBEVF
> -#undef RTE_PCI_DEV_ID_DECL_I40E -#undef RTE_PCI_DEV_ID_DECL_I40EVF
> #undef RTE_PCI_DEV_ID_DECL_VIRTIO #undef
> RTE_PCI_DEV_ID_DECL_VMXNET3 #undef RTE_PCI_DEV_ID_DECL_FM10K
> --
> 2.4.0
next prev parent reply other threads:[~2016-07-11 6:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-11 4:01 Jingjing Wu
2016-07-11 6:19 ` Zhang, Helin [this message]
2016-07-11 6:55 ` Thomas Monjalon
2016-07-11 7:02 ` Zhang, Helin
2016-07-11 7:29 ` Wu, Jingjing
2016-07-11 8:31 ` Zhang, Helin
2016-07-11 16:31 ` Thomas Monjalon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=F35DEAC7BCE34641BA9FAC6BCA4A12E717D953B3@SHSMSX103.ccr.corp.intel.com \
--to=helin.zhang@intel.com \
--cc=dev@dpdk.org \
--cc=jingjing.wu@intel.com \
--cc=thomas.monjalon@6wind.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).