From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35C26A0613 for ; Fri, 27 Sep 2019 07:28:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 16E9E1E34; Fri, 27 Sep 2019 07:28:14 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id C94FD9E4 for ; Fri, 27 Sep 2019 07:28:11 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 22:28:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,554,1559545200"; d="scan'208";a="194368376" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga006.jf.intel.com with ESMTP; 26 Sep 2019 22:28:06 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 26 Sep 2019 22:27:33 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 26 Sep 2019 22:27:33 -0700 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 22:27:33 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.92]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.195]) with mapi id 14.03.0439.000; Fri, 27 Sep 2019 13:27:31 +0800 From: "Yang, Qiming" To: "Zhang, Qi Z" , "Lu, Wenzhuo" CC: "dev@dpdk.org" , "Ye, Xiaolong" , "Nowlin, Dan" , "Stillwell Jr, Paul M" Thread-Topic: [PATCH 5/8] net/ice/base: improvements to Flow Director masking Thread-Index: AQHVdOoB0WlVR6M6lkyeaE03W5vnSqc+/gXQ Date: Fri, 27 Sep 2019 05:27:30 +0000 Message-ID: References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20190927041646.34712-1-qi.z.zhang@intel.com> <20190927041646.34712-6-qi.z.zhang@intel.com> In-Reply-To: <20190927041646.34712-6-qi.z.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGE5MTE5NGUtNjYzMS00Y2E5LWE5NjctNDRjMWU2YTU1OGIwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiczc1RWcxZWRQWVBBMlcrcFpJc1wvXC9aK1lZQ2lVbWJQeEt0S1FuZkl2akxFeXNpUDRvT0xRMDI1cjZXZGEyTVFLIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 5/8] net/ice/base: improvements to Flow Director masking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Qi > -----Original Message----- > From: Zhang, Qi Z > Sent: Friday, September 27, 2019 12:17 PM > To: Lu, Wenzhuo ; Yang, Qiming > > Cc: dev@dpdk.org; Ye, Xiaolong ; Zhang, Qi Z > ; Nowlin, Dan ; Stillwell Jr, > Paul M > Subject: [PATCH 5/8] net/ice/base: improvements to Flow Director masking >=20 > Currently, 3-tuple FD matching is implemented using masking. However, thi= s > is using up twenty-four of the thirty-two FD masks available. This patch = uses > the swap register more efficiently to implement the 3-tuple matches, whic= h > saves all FD masks for other uses. >=20 > Added IPV6 versions of DSCP, TTL and Protocol fields for FD use. >=20 > Signed-off-by: Dan Nowlin > Signed-off-by: Paul M Stillwell Jr > Signed-off-by: Qi Zhang > --- > drivers/net/ice/base/ice_flex_pipe.c | 71 +++++++++------------ > drivers/net/ice/base/ice_flex_type.h | 4 +- > drivers/net/ice/base/ice_flow.c | 118 ++++++++++++++++++++---------= ------ > drivers/net/ice/base/ice_flow.h | 10 ++- > 4 files changed, 108 insertions(+), 95 deletions(-) >=20 > diff --git a/drivers/net/ice/base/ice_flex_pipe.c > b/drivers/net/ice/base/ice_flex_pipe.c > index 75bb87079..8f8cab86e 100644 > --- a/drivers/net/ice/base/ice_flex_pipe.c > +++ b/drivers/net/ice/base/ice_flex_pipe.c > @@ -1248,25 +1248,6 @@ void ice_free_seg(struct ice_hw *hw) } >=20 [snip] > @@ -4342,29 +4321,39 @@ ice_update_fd_swap(struct ice_hw *hw, u16 > prof_id, struct ice_fv_word *es) > si -=3D indexes_used; > } >=20 > - /* for each set of 4 swap indexes, write the appropriate register */ > + /* for each set of 4 swap and 4 inset indexes, write the appropriate > + * register > + */ > for (j =3D 0; j < hw->blk[ICE_BLK_FD].es.fvw / 4; j++) { > - u32 raw_entry =3D 0; > + u32 raw_swap =3D 0; > + u32 raw_in =3D 0; >=20 > for (k =3D 0; k < 4; k++) { > u8 idx; >=20 > idx =3D (j * 4) + k; > - if (used[idx]) > - raw_entry |=3D used[idx] << (k * > BITS_PER_BYTE); > + if (used[idx] && !(mask_sel & BIT(idx))) { > + raw_swap |=3D used[idx] << (k * > BITS_PER_BYTE); #define > +ICE_INSET_DFLT 0x9f Is this macro defined within this function? > + raw_in |=3D ICE_INSET_DFLT << (k * > BITS_PER_BYTE); > + } > } >=20 [snip] Qiming