From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D841BA3160 for ; Thu, 10 Oct 2019 05:09:06 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B4FF81E89B; Thu, 10 Oct 2019 05:09:06 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 15DDC1E537 for ; Thu, 10 Oct 2019 05:09:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2019 20:09:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,278,1566889200"; d="scan'208";a="218881338" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga004.fm.intel.com with ESMTP; 09 Oct 2019 20:09:04 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 9 Oct 2019 20:09:03 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.96]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.119]) with mapi id 14.03.0439.000; Thu, 10 Oct 2019 11:09:01 +0800 From: "Yang, Qiming" To: "Zhang, Qi Z" , "Lu, Wenzhuo" CC: "dev@dpdk.org" , "Ye, Xiaolong" , "Nowlin, Dan" , "Stillwell Jr, Paul M" Thread-Topic: [PATCH v3 11/12] net/ice/base: add QFI for Flow Director Thread-Index: AQHVfXpj7LMo4D91nUmWyZCfjyNL36dTNRaA Date: Thu, 10 Oct 2019 03:09:00 +0000 Message-ID: References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> <20191008015018.17086-12-qi.z.zhang@intel.com> In-Reply-To: <20191008015018.17086-12-qi.z.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 11/12] net/ice/base: add QFI for Flow Director X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" -----Original Message----- From: Zhang, Qi Z=20 Sent: Tuesday, October 8, 2019 09:50 To: Lu, Wenzhuo ; Yang, Qiming Cc: dev@dpdk.org; Ye, Xiaolong ; Zhang, Qi Z ; Nowlin, Dan ; Stillwell Jr, Paul M <= paul.m.stillwell.jr@intel.com> Subject: [PATCH v3 11/12] net/ice/base: add QFI for Flow Director Added the GTP QFI field to the Flow director interface to allow matching ag= ainst this field. Since this field only appears in GTP packets with extensi= on headers, this also requires adding profile TCAM mask matching capability= . This allows comprehending different PTYPE attributes by examining flags = from the parser. Using this method, different profiles can be used by exami= ning flag values from the parser. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 245 ++++++++++++++-----------------= ---- drivers/net/ice/base/ice_flex_pipe.h | 6 +- drivers/net/ice/base/ice_flex_type.h | 66 ++++++++++ drivers/net/ice/base/ice_flow.c | 57 +++++++- drivers/net/ice/base/ice_flow.h | 24 +++- 5 files changed, 238 insertions(+), 160 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ic= e_flex_pipe.c index bf14149b8..c2af1dfe8 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -2692,34 +2692,7 @@ ice_find_prof_id_with_mask(struct ice_hw *hw, enum i= ce_block blk, continue; =20 /* check if masks settings are the same for this profile */ - if (!ice_prof_has_mask(hw, blk, i, masks)) - continue; - - *prof_id =3D i; - return ICE_SUCCESS; - } - - return ICE_ERR_DOES_NOT_EXIST; -} - -/** - * ice_find_prof_id - find profile ID for a given field vector - * @hw: pointer to the hardware structure - * @blk: HW block - * @fv: field vector to search for - * @prof_id: receives the profile ID - */ -static enum ice_status -ice_find_prof_id(struct ice_hw *hw, enum ice_block blk, - struct ice_fv_word *fv, u8 *prof_id) -{ - struct ice_es *es =3D &hw->blk[blk].es; - u16 off, i; - - for (i =3D 0; i < es->count; i++) { - off =3D i * es->fvw; - - if (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv))) + if (masks && !ice_prof_has_mask(hw, blk, i, masks)) continue; =20 *prof_id =3D i; @@ -4364,127 +4337,58 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id,= struct ice_fv_word *es) return ICE_SUCCESS; } =20 +/* The entries here needs to match the order of enum ice_ptype_attrib=20 +*/ static const struct ice_ptype_attrib_info ice_ptype_attributes[] =3D { + { ICE_GTP_PDU_EH, ICE_GTP_PDU_FLAG_MASK }, + { ICE_GTP_SESSION, ICE_GTP_FLAGS_MASK }, + { ICE_GTP_DOWNLINK, ICE_GTP_FLAGS_MASK }, + { ICE_GTP_UPLINK, ICE_GTP_FLAGS_MASK }, +}; + /** - * ice_add_prof_with_mask - add profile - * @hw: pointer to the HW struct - * @blk: hardware block - * @id: profile tracking ID - * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits) - * @es: extraction sequence (length of array is determined by the block) - * @masks: extraction sequence (length of array is determined by the block= ) - * - * This function registers a profile, which matches a set of PTYPES with a - * particular extraction sequence. While the hardware profile is allocated - * it will not be written until the first call to ice_add_flow that specif= ies - * the ID value used here. + * ice_get_ptype_attrib_info - get ptype attribute information + * @type: attribute type + * @info: pointer to variable to the attribute information */ -enum ice_status -ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id, - u8 ptypes[], struct ice_fv_word *es, u16 *masks) +static void +ice_get_ptype_attrib_info(enum ice_ptype_attrib_type type, + struct ice_ptype_attrib_info *info) { - u32 bytes =3D DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE); - ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT); - struct ice_prof_map *prof; - enum ice_status status; - u32 byte =3D 0; - u8 prof_id; - - ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT); - - ice_acquire_lock(&hw->blk[blk].es.prof_map_lock); - - /* search for existing profile */ - status =3D ice_find_prof_id_with_mask(hw, blk, es, masks, &prof_id); - if (status) { - /* allocate profile ID */ - status =3D ice_alloc_prof_id(hw, blk, &prof_id); - if (status) - goto err_ice_add_prof; - if (blk =3D=3D ICE_BLK_FD) { - /* For Flow Director block, the extraction sequence may - * need to be altered in the case where there are paired - * fields that have no match. This is necessary because - * for Flow Director, src and dest fields need to paired - * for filter programming and these values are swapped - * during Tx. - */ - status =3D ice_update_fd_swap(hw, prof_id, es); - if (status) - goto err_ice_add_prof; - } - status =3D ice_update_prof_masking(hw, blk, prof_id, es, masks); - if (status) - goto err_ice_add_prof; - - /* and write new es */ - ice_write_es(hw, blk, prof_id, es); - } - - ice_prof_inc_ref(hw, blk, prof_id); - - /* add profile info */ - - prof =3D (struct ice_prof_map *)ice_malloc(hw, sizeof(*prof)); - if (!prof) - goto err_ice_add_prof; - - prof->profile_cookie =3D id; - prof->prof_id =3D prof_id; - prof->ptg_cnt =3D 0; - prof->context =3D 0; - - /* build list of ptgs */ - while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) { - u32 bit; - - if (!ptypes[byte]) { - bytes--; - byte++; - continue; - } - /* Examine 8 bits per byte */ - for (bit =3D 0; bit < 8; bit++) { - if (ptypes[byte] & BIT(bit)) { - u16 ptype; - u8 ptg; - u8 m; - - ptype =3D byte * BITS_PER_BYTE + bit; - - /* The package should place all ptypes in a - * non-zero PTG, so the following call should - * never fail. - */ - if (ice_ptg_find_ptype(hw, blk, ptype, &ptg)) - continue; + *info =3D ice_ptype_attributes[type]; +} =20 - /* If PTG is already added, skip and continue */ - if (ice_is_bit_set(ptgs_used, ptg)) - continue; +/** + * ice_add_prof_attrib - add any ptg with attributes to profile + * @prof: pointer to the profile to which ptg entries will be added + * @ptg: PTG to be added + * @ptype: PTYPE that needs to be looked up + * @attr: array of attributes that will be considered + * @attr_cnt: number of elements in the attribute array */ static enum=20 +ice_status ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16=20 +ptype, + const struct ice_ptype_attributes *attr, u16 attr_cnt) { + bool found =3D false; + u16 i; =20 - ice_set_bit(ptg, ptgs_used); - prof->ptg[prof->ptg_cnt] =3D ptg; + for (i =3D 0; i < attr_cnt; i++) { + if (attr[i].ptype =3D=3D ptype) { + found =3D true; =20 - if (++prof->ptg_cnt >=3D ICE_MAX_PTG_PER_PROFILE) - break; + prof->ptg[prof->ptg_cnt] =3D ptg; + ice_get_ptype_attrib_info(attr[i].attrib, + &prof->attr[prof->ptg_cnt]); =20 - /* nothing left in byte, then exit */ - m =3D ~((1 << (bit + 1)) - 1); - if (!(ptypes[byte] & m)) - break; - } + if (++prof->ptg_cnt >=3D ICE_MAX_PTG_PER_PROFILE) + return ICE_ERR_MAX_LIMIT; } - - bytes--; - byte++; } =20 - LIST_ADD(&prof->list, &hw->blk[blk].es.prof_map); - status =3D ICE_SUCCESS; + if (!found) + return ICE_ERR_DOES_NOT_EXIST; =20 -err_ice_add_prof: - ice_release_lock(&hw->blk[blk].es.prof_map_lock); - return status; + return ICE_SUCCESS; } =20 /** @@ -4493,16 +4397,20 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_= block blk, u64 id, * @blk: hardware block * @id: profile tracking ID * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits) + * @attr: array of attributes + * @attr_cnt: number of elements in attrib array * @es: extraction sequence (length of array is determined by the block) + * @masks: mask for extraction sequence * - * This function registers a profile, which matches a set of PTGs with a + * This function registers a profile, which matches a set of PTYPES=20 + with a * particular extraction sequence. While the hardware profile is allocated * it will not be written until the first call to ice_add_flow that specif= ies * the ID value used here. */ enum ice_status ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], - struct ice_fv_word *es) + const struct ice_ptype_attributes *attr, u16 attr_cnt, + struct ice_fv_word *es, u16 *masks) { u32 bytes =3D DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE); ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT); @@ -4516,7 +4424,7 @@ ice_ad= d_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], ice_acquire_lock(&hw->blk[blk].es.prof_map_lock); =20 /* search for existing profile */ - status =3D ice_find_prof_id(hw, blk, es, &prof_id); + status =3D ice_find_prof_id_with_mask(hw, blk, es, masks, &prof_id); if (status) { /* allocate profile ID */ status =3D ice_alloc_prof_id(hw, blk, &prof_id); @@ -4534,6 +4442,9 @@ i= ce_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], if (status) goto err_ice_add_prof; } + status =3D ice_update_prof_masking(hw, blk, prof_id, es, masks); + if (status) + goto err_ice_add_prof; =20 /* and write new es */ ice_write_es(hw, blk, prof_id, es); @@ -4582,10 +4493,25 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk,= u64 id, u8 ptypes[], continue; =20 ice_set_bit(ptg, ptgs_used); - prof->ptg[prof->ptg_cnt] =3D ptg; - - if (++prof->ptg_cnt >=3D ICE_MAX_PTG_PER_PROFILE) + /* Check to see there are any attributes for + * this ptype, and add them if found. + */ + status =3D ice_add_prof_attrib(prof, ptg, ptype, + attr, attr_cnt); + if (status =3D=3D ICE_ERR_MAX_LIMIT) break; + if (status) { + /* This is simple a ptype/ptg with no + * attribute + */ + prof->ptg[prof->ptg_cnt] =3D ptg; + prof->attr[prof->ptg_cnt].flags =3D 0; + prof->attr[prof->ptg_cnt].mask =3D 0; + + if (++prof->ptg_cnt >=3D + ICE_MAX_PTG_PER_PROFILE) + break; + } =20 /* nothing left in byte, then exit */ m =3D ~((1 << (bit + 1)) - 1); @@ -4928,6 +4854,7 @@ ice_get_prof(struct ice_hw *hw, enum ice_block blk, u= 64 hdl, p->type =3D ICE_PTG_ES_ADD; p->ptype =3D 0; p->ptg =3D map->ptg[i]; + p->attr =3D map->attr[i]; p->add_ptg =3D 0; =20 p->add_prof =3D 1; @@ -5017,6 +4944,7 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block= blk, p->tcam[i].prof_id =3D map->prof_id; p->tcam[i].tcam_idx =3D ICE_INVALID_TCAM; p->tcam[i].ptg =3D map->ptg[i]; + p->tcam[i].attr =3D map->attr[i]; } =20 LIST_ADD(&p->list, lst); @@ -5064,6 +4992,19 @@ ice_move_vsi(struct ice_hw *hw, enum ice_block blk, = u16 vsi, u16 vsig, } =20 /** + * ice_set_tcam_flags - set tcam flag don't care mask + * @mask: mask for flags + * @dc_mask: pointer to the don't care mask */ static void=20 +ice_set_tcam_flags(u16 mask, u8 dc_mask[ICE_TCAM_KEY_VAL_SZ]) { + u16 *flag_word; + + /* flags are lowest u16 */ + flag_word =3D (u16 *)dc_mask; + *flag_word =3D ~mask; +} +/** * ice_prof_tcam_ena_dis - add enable or disable TCAM change * @hw: pointer to the HW struct * @blk: hardware block @@ -5105,9 +5046,12 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_bl= ock blk, bool enable, if (!p) return ICE_ERR_NO_MEMORY; =20 + /* set don't care masks for tcam flags */ + ice_set_tcam_flags(tcam->attr.mask, dc_msk); + status =3D ice_tcam_write_entry(hw, blk, tcam->tcam_idx, tcam->prof_id, - tcam->ptg, vsig, 0, 0, vl_msk, dc_msk, - nm_msk); + tcam->ptg, vsig, 0, tcam->attr.flags, + vl_msk, dc_msk, nm_msk); if (status) goto err_ice_prof_tcam_ena_dis; =20 @@ -5258,6 +5202,7 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_bloc= k blk, u16 vsig, u64 hdl, t->tcam[i].ptg =3D map->ptg[i]; t->tcam[i].prof_id =3D map->prof_id; t->tcam[i].tcam_idx =3D tcam_idx; + t->tcam[i].attr =3D map->attr[i]; t->tcam[i].in_use =3D true; =20 p->type =3D ICE_TCAM_ADD; @@ -5267,11 +5212,15 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_bl= ock blk, u16 vsig, u64 hdl, p->vsig =3D vsig; p->tcam_idx =3D t->tcam[i].tcam_idx; =20 + /* set don't care masks for tcam flags */ + ice_set_tcam_flags(t->tcam[i].attr.mask, dc_msk); + /* write the TCAM entry */ status =3D ice_tcam_write_entry(hw, blk, t->tcam[i].tcam_idx, t->tcam[i].prof_id, - t->tcam[i].ptg, vsig, 0, 0, - vl_msk, dc_msk, nm_msk); + t->tcam[i].ptg, vsig, 0, + t->tcam[i].attr.flags, vl_msk, + dc_msk, nm_msk); if (status) goto err_ice_add_prof_id_vsig; =20 diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ic= e_flex_pipe.h index e7d42e3de..b24a09b4d 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -52,11 +52,9 @@ ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ic= e_tunnel_type *type); enum ice_status ice_vsig_find_vsi(struct ice_hw *hw= , enum ice_block blk, u16 vsi, u16 *vsig); enum ice_status -ice_add_prof_w= ith_mask(struct ice_hw *hw, enum ice_block blk, u64 id, - u8 ptypes[], struct ice_fv_word *es, u16 *masks); -enum ice_status ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], - struct ice_fv_word *es); + const struct ice_ptype_attributes *attr, u16 attr_cnt, + struct ice_fv_word *es, u16 *masks); void ice_init_all_prof_masks(struct ice_hw *hw); void ice_shutdown_all_pr= of_masks(struct ice_hw *hw); struct ice_prof_map * diff --git a/drivers/ne= t/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 92d205ac7..1be98ea52 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -278,6 +278,69 @@ enum ice_sect { #define ICE_PTYPE_IPV6_TCP_PAY 92 #define ICE_PTYPE_IPV6_SCTP_PAY 93 #define ICE_PTYPE_IPV6_ICMP_PAY 94 +#define ICE_MAC_IPV4_GTPC_TEID 325 +#define ICE_MAC_IPV6_GTPC_TEID 326 +#define ICE_MAC_IPV4_GTPC 327 +#define ICE_MAC_IPV6_GTPC 328 +#define ICE_MAC_IPV4_GTPU 329 +#define ICE_MAC_IPV6_GTPU 330 +#define ICE_MAC_IPV4_GTPU_IPV4_FRAG 331 +#define ICE_MAC_IPV4_GTPU_IPV4_PAY 332 +#define ICE_MAC_IPV4_GTPU_IPV4_UDP_PAY 333 +#define ICE_MAC_IPV4_GTPU_IPV4_TCP 334 +#define ICE_MAC_IPV4_GTPU_IPV4_ICMP 335 +#define ICE_MAC_IPV6_GTPU_IPV4_FRAG 336 +#define ICE_MAC_IPV6_GTPU_IPV4_PAY 337 +#define ICE_MAC_IPV6_GTPU_IPV4_UDP_PAY 338 +#define ICE_MAC_IPV6_GTPU_IPV4_TCP 339 +#define ICE_MAC_IPV6_GTPU_IPV4_ICMP 340 +#define ICE_MAC_IPV4_GTPU_IPV6_FRAG 341 +#define ICE_MAC_IPV4_GTPU_IPV6_PAY 342 +#define ICE_MAC_IPV4_GTPU_IPV6_UDP_PAY 343 +#define ICE_MAC_IPV4_GTPU_IPV6_TCP 344 +#define ICE_MAC_IPV4_GTPU_IPV6_ICMPV6 345 +#define ICE_MAC_IPV6_GTPU_IPV6_FRAG 346 +#define ICE_MAC_IPV6_GTPU_IPV6_PAY 347 +#define ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY 348 +#define ICE_MAC_IPV6_GTPU_IPV6_TCP 349 +#define ICE_MAC_IPV6_GTPU_IPV6_ICMPV6 350 + +/* Attributes that can modify PTYPE definitions. + * + * These values will represent special attributes for PTYPES, which=20 +will + * resolve into metadata packet flags definitions that can be used in=20 +the TCAM + * for identifying a PTYPE with specific characteristics. + */ +enum ice_ptype_attrib_type { + /* GTP PTYPES */ + ICE_PTYPE_ATTR_GTP_PDU_EH, + ICE_PTYPE_ATTR_GTP_SESSION, + ICE_PTYPE_ATTR_GTP_DOWNLINK, + ICE_PTYPE_ATTR_GTP_UPLINK, +}; + +struct ice_ptype_attrib_info { + u16 flags; + u16 mask; +}; + +/* TCAM flag definitions */ +#define ICE_GTP_PDU BIT(14) +#define ICE_GTP_PDU_LINK BIT(13) + +/* GTP attributes */ +#define ICE_GTP_PDU_FLAG_MASK (ICE_GTP_PDU) +#define ICE_GTP_PDU_EH ICE_GTP_PDU + +#define ICE_GTP_FLAGS_MASK (ICE_GTP_PDU | ICE_GTP_PDU_LINK) +#define ICE_GTP_SESSION 0 +#define ICE_GTP_DOWNLINK ICE_GTP_PDU +#define ICE_GTP_UPLINK (ICE_GTP_PDU | ICE_GTP_PDU_LINK) + +struct ice_ptype_attributes { + u16 ptype; + enum ice_ptype_attrib_type attrib; +}; =20 /* Packet Type Groups (PTG) - Inner Most fields (IM) */ #define ICE_PTG_IM_IPV4_TCP 16 @@ -530,12 +593,14 @@ struct ice_prof_map { u8 prof_id; u8 ptg_cnt; u8 ptg[ICE_MAX_PTG_PER_PROFILE]; + struct ice_ptype_attrib_info attr[ICE_MAX_PTG_PER_PROFILE]; }; =20 #define ICE_INVALID_TCAM 0xFFFF =20 struct ice_tcam_inf { u16 tcam_idx; + struct ice_ptype_attrib_info attr; u8 ptg; u8 prof_id; u8 in_use; @@ -708,6 +773,7 @@ struct ice_chs_chg { u16 vsig; u16 orig_vsig; u16 tcam_idx; + struct ice_ptype_attrib_info attr; }; =20 #define ICE_FLOW_PTYPE_MAX ICE_XLT1_CNT diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flo= w.c index 38c7c42f7..f4f961167 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -20,6 +20,7 @@ #define ICE_FLOW_FLD_SZ_ARP_OPER 2 #define ICE_FLOW_FLD_SZ_GRE_KEYID 4 #define ICE_FLOW_FLD_SZ_GTP_TEID 4 +#define ICE_FLOW_FLD_SZ_GTP_QFI 2 #define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2 =20 /* Describe properties of a protocol header field */ @@ -126,6 +127,12 @@ = struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] =3D { /* ICE_FLOW_FIELD_IDX_GTPU_IP_TEID */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_IP, 12, ICE_FLOW_FLD_SZ_GTP_TEID), + /* ICE_FLOW_FIELD_IDX_GTPU_EH_TEID */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_EH, 12, + ICE_FLOW_FLD_SZ_GTP_TEID), + /* ICE_FLOW_FIELD_IDX_GTPU_EH_QFI */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_GTPU_EH, 20, + ICE_FLOW_FLD_SZ_GTP_QFI, 0x003f), /* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12, ICE_FLOW_FLD_SZ_GTP_TEID), @@ -169,7 +176,7 @@ static const u32 ice_ptypes_macvlan_il[] =3D { static = const u32 ice_ptypes_ipv4_ofos[] =3D { 0x1DC00000, 0x04000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x000FC000, 0x00000000, 0x00000000, + 0x0003000F, 0x000FC000, 0x03E0F800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -193,7 +200,7 @@ stati= c const u32 ice_ptypes_ipv4_il[] =3D { static const u32 ice_ptypes_ipv6_of= os[] =3D { 0x00000000, 0x00000000, 0x77000000, 0x10002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x03F00000, 0x00000000, 0x00000000, + 0x00080F00, 0x03F00000, 0x7C1F0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -336,10 +343,33 @@ sta= tic const u32 ice_ptypes_gtpc_tid[] =3D { }; =20 /* Packet types for GTPU */ +static const struct ice_ptype_attributes ice_attr_gtpu_eh[] =3D { + { ICE_MAC_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH }, }; + static const u32 ice_ptypes_gtpu[] =3D { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x7FFFF800, 0x00000000, + 0x00000000, 0x00000000, 0x7FFFFE00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -370,6 +400,10 @@ stru= ct ice_flow_prof_params { * This will give us the direction flags. */ struct ice_fv_word es[ICE_MAX_FV_WORDS]; + /* attributes can be used to add attributes to a particular PTYPE */ + const struct ice_ptype_attributes *attr; + u16 attr_cnt; + u16 mask[ICE_MAX_FV_WORDS]; ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX); }; @@ -562,6 +596,16 @@ = ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); } + } else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_EH) { + if (!i) { + src =3D (const ice_bitmap_t *)ice_ptypes_gtpu; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } + + /* Attributes for GTP packet with Extension Header */ + params->attr =3D ice_attr_gtpu_eh; + params->attr_cnt =3D ARRAY_SIZE(ice_attr_gtpu_eh); } } =20 @@ -711,6 +755,8 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_= prof_params *params, case ICE_FLOW_FIELD_IDX_GTPU_IP_TEID: case ICE_FLOW_FIELD_IDX_GTPU_UP_TEID: case ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID: + case ICE_FLOW_FIELD_IDX_GTPU_EH_TEID: + case ICE_FLOW_FIELD_IDX_GTPU_EH_QFI: /* GTP is accessed through UDP OF protocol */ prot_id =3D ICE_PROT_UDP_OF; break; @@ -1176,8 +1222,9 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_bl= ock blk, } =20 /* Add a HW profile for this flow profile */ - status =3D ice_add_prof_with_mask(hw, blk, prof_id, (u8 *)params.ptypes, - params.es, params.mask); + status =3D ice_add_prof(hw, blk, prof_id, (u8 *)params.ptypes, + params.attr, params.attr_cnt, params.es, + params.mask); if (status) { ice_debug(hw, ICE_DBG_FLOW, "Error adding a HW flow profile\n"); goto out; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flo= w.h index c224e6ebf..4686274af 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -58,6 +58,19 @@ #define ICE_FLOW_HASH_GTP_U_IPV6_TEID \ (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_TEID) =20 +#define ICE_FLOW_HASH_GTP_U_EH_TEID \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_TEID)) + +#define ICE_FLOW_HASH_GTP_U_EH_QFI \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_QFI)) + +#define ICE_FLOW_HASH_GTP_U_IPV4_EH \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_U_EH_TEID | \ + ICE_FLOW_HASH_GTP_U_EH_QFI) +#define ICE_FLOW_HASH_GTP_U_IPV6_EH \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_EH_TEID | \ + ICE_FLOW_HASH_GTP_U_EH_QFI) + #define ICE_FLOW_HASH_PPPOE_SESS_ID \ (BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID)) =20 @@ -89,9 +102,10 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_GTPC =3D 0x00000400, ICE_FLOW_SEG_HDR_GTPC_TEID =3D 0x00000800, ICE_FLOW_SEG_HDR_GTPU_IP =3D 0x00001000, - ICE_FLOW_SEG_HDR_GTPU_DWN =3D 0x00002000, - ICE_FLOW_SEG_HDR_GTPU_UP =3D 0x00004000, - ICE_FLOW_SEG_HDR_PPPOE =3D 0x00008000, + ICE_FLOW_SEG_HDR_GTPU_EH =3D 0x00002000, + ICE_FLOW_SEG_HDR_GTPU_DWN =3D 0x00004000, + ICE_FLOW_SEG_HDR_GTPU_UP =3D 0x00008000, + ICE_FLOW_SEG_HDR_PPPOE =3D 0x00010000, }; =20 /* These segements all have the same PTYPES, but are otherwise distinguish= ed by @@ -99,6 +113,7 @@ enum ice_flow_seg_hdr { * * gtp_eh_pdu gtp_eh_pdu_link * ICE_FLOW_SEG_HDR_GTPU_IP 0 0 + * ICE_FLOW_SEG_HDR_GTPU_EH 1 don't care * ICE_FLOW_SEG_HDR_GTPU_DWN 1 0 * ICE_FLOW_SEG_HDR_GTPU_UP 1 1 */ @@ -147,6 +162,9 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_GTPC_TEID, /* GTPU_IP */ ICE_FLOW_FIELD_IDX_GTPU_IP_TEID, + /* GTPU_EH */ + ICE_FLOW_FIELD_IDX_GTPU_EH_TEID, + ICE_FLOW_FIELD_IDX_GTPU_EH_QFI, /* GTPU_UP */ ICE_FLOW_FIELD_IDX_GTPU_UP_TEID, /* GTPU_DWN */ -- 2.13.6 Acked-by: Qiming Yang