From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 50778A00E6 for ; Tue, 11 Jun 2019 18:27:01 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3FEFB1D08D; Tue, 11 Jun 2019 18:27:00 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6236F1D08B for ; Tue, 11 Jun 2019 18:26:58 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jun 2019 09:26:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,362,1557212400"; d="scan'208";a="183853547" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga002.fm.intel.com with ESMTP; 11 Jun 2019 09:26:57 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 11 Jun 2019 09:26:57 -0700 Received: from fmsmsx120.amr.corp.intel.com ([169.254.15.191]) by fmsmsx117.amr.corp.intel.com ([169.254.3.141]) with mapi id 14.03.0415.000; Tue, 11 Jun 2019 09:26:57 -0700 From: "Stillwell Jr, Paul M" To: "Rong, Leyi" , "Zhang, Qi Z" CC: "dev@dpdk.org" , "Nguyen, Anthony L" Thread-Topic: [PATCH v2 21/66] net/ice/base: add helper functions for PHY caching Thread-Index: AQHVIG3oi4Yl03VH4kqnJvCUTGjyLKaWo+Zg Date: Tue, 11 Jun 2019 16:26:56 +0000 Message-ID: References: <20190604054248.68510-1-leyi.rong@intel.com> <20190611155221.2703-1-leyi.rong@intel.com> <20190611155221.2703-22-leyi.rong@intel.com> In-Reply-To: <20190611155221.2703-22-leyi.rong@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWY5N2RiOTQtNTEzNS00M2EwLWE4NGYtNjdhMDNjNjY4NmM3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZDVhejl0TUx5Sm5KaHhWYzVWZHJnOEVjTzdTUlZWUTBhV29cL051T3JENXZNTEtQYmlLb2VpK3ZNSzNaMDg5cVkifQ== x-originating-ip: [10.1.200.108] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 21/66] net/ice/base: add helper functions for PHY caching X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Rong, Leyi > Sent: Tuesday, June 11, 2019 8:52 AM > To: Zhang, Qi Z > Cc: dev@dpdk.org; Rong, Leyi ; Nguyen, Anthony L > ; Stillwell Jr, Paul M > > Subject: [PATCH v2 21/66] net/ice/base: add helper functions for PHY cach= ing >=20 > Add additional functions to aide in caching PHY configuration. > In order to cache the initial modes, we need to determine the operating > mode based on capabilities. Add helper functions for flow control and FEC= to > take a set of capabilities and return the operating mode matching those > capabilities. Also add a helper function to determine whether a PHY capab= ility > matches a PHY configuration. >=20 > Signed-off-by: Tony Nguyen > Signed-off-by: Paul M Stillwell Jr > Signed-off-by: Leyi Rong > --- > drivers/net/ice/base/ice_adminq_cmd.h | 1 + > drivers/net/ice/base/ice_common.c | 83 > +++++++++++++++++++++++++++ > drivers/net/ice/base/ice_common.h | 9 ++- > 3 files changed, 91 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/ice/base/ice_adminq_cmd.h > b/drivers/net/ice/base/ice_adminq_cmd.h > index 739f79e88..77f93b950 100644 > --- a/drivers/net/ice/base/ice_adminq_cmd.h > +++ b/drivers/net/ice/base/ice_adminq_cmd.h > @@ -1594,6 +1594,7 @@ struct ice_aqc_get_link_status_data { > #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 > #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 > __le16 link_speed; > +#define ICE_AQ_LINK_SPEED_M 0x7FF > #define ICE_AQ_LINK_SPEED_10MB BIT(0) > #define ICE_AQ_LINK_SPEED_100MB BIT(1) > #define ICE_AQ_LINK_SPEED_1000MB BIT(2) > diff --git a/drivers/net/ice/base/ice_common.c > b/drivers/net/ice/base/ice_common.c > index 5b4a13a41..7f7f4dad0 100644 > --- a/drivers/net/ice/base/ice_common.c > +++ b/drivers/net/ice/base/ice_common.c > @@ -2552,6 +2552,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi, > } > } >=20 > +/** > + * ice_caps_to_fc_mode > + * @caps: PHY capabilities > + * > + * Convert PHY FC capabilities to ice FC mode */ enum ice_fc_mode > +ice_caps_to_fc_mode(u8 caps) { > + if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && > + caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) > + return ICE_FC_FULL; > + > + if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) > + return ICE_FC_TX_PAUSE; > + > + if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) > + return ICE_FC_RX_PAUSE; > + > + return ICE_FC_NONE; > +} > + > +/** > + * ice_caps_to_fec_mode > + * @caps: PHY capabilities > + * @fec_options: Link FEC options > + * > + * Convert PHY FEC capabilities to ice FEC mode */ enum ice_fec_mode > +ice_caps_to_fec_mode(u8 caps, u8 fec_options) { > + if (caps & ICE_AQC_PHY_EN_AUTO_FEC) > + return ICE_FEC_AUTO; > + > + if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | > + ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | > + ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | > + ICE_AQC_PHY_FEC_25G_KR_REQ)) > + return ICE_FEC_BASER; > + > + if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | > + ICE_AQC_PHY_FEC_25G_RS_544_REQ | > + ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) > + return ICE_FEC_RS; > + > + return ICE_FEC_NONE; > +} > + Is there DPDK code to call the above functions? If not, then drop this patc= h. > /** > * ice_set_fc > * @pi: port information structure > @@ -2658,6 +2705,42 @@ ice_set_fc(struct ice_port_info *pi, u8 > *aq_failures, bool ena_auto_link_update) > return status; > } >=20 > +/** > + * ice_phy_caps_equals_cfg > + * @phy_caps: PHY capabilities > + * @phy_cfg: PHY configuration > + * > + * Helper function to determine if PHY capabilities matches PHY > + * configuration > + */ > +bool > +ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, > + struct ice_aqc_set_phy_cfg_data *phy_cfg) { > + u8 caps_mask, cfg_mask; > + > + if (!phy_caps || !phy_cfg) > + return false; > + > + /* These bits are not common between capabilities and > configuration. > + * Do not use them to determine equality. > + */ > + caps_mask =3D ICE_AQC_PHY_CAPS_MASK & > ~(ICE_AQC_PHY_AN_MODE | > + ICE_AQC_PHY_EN_MOD_QUAL); > + cfg_mask =3D ICE_AQ_PHY_ENA_VALID_MASK & > ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; > + > + if (phy_caps->phy_type_low !=3D phy_cfg->phy_type_low || > + phy_caps->phy_type_high !=3D phy_cfg->phy_type_high || > + ((phy_caps->caps & caps_mask) !=3D (phy_cfg->caps & cfg_mask)) || > + phy_caps->low_power_ctrl !=3D phy_cfg->low_power_ctrl || > + phy_caps->eee_cap !=3D phy_cfg->eee_cap || > + phy_caps->eeer_value !=3D phy_cfg->eeer_value || > + phy_caps->link_fec_options !=3D phy_cfg->link_fec_opt) > + return false; > + > + return true; > +} > + > /** > * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration dat= a > * @caps: PHY ability structure to copy date from diff --git > a/drivers/net/ice/base/ice_common.h > b/drivers/net/ice/base/ice_common.h > index 4cd87fc1e..10131b473 100644 > --- a/drivers/net/ice/base/ice_common.h > +++ b/drivers/net/ice/base/ice_common.h > @@ -136,14 +136,19 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw > *hw); enum ice_status ice_aq_set_phy_cfg(struct ice_hw *hw, struct > ice_port_info *pi, > struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd > *cd); > +enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); enum ice_fec_mode > +ice_caps_to_fec_mode(u8 caps, u8 fec_options); > enum ice_status > ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, > bool ena_auto_link_update); > -void > -ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum > ice_fec_mode fec); > +bool > +ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, > + struct ice_aqc_set_phy_cfg_data *cfg); > void > ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps, > struct ice_aqc_set_phy_cfg_data *cfg); > +void > +ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum > ice_fec_mode > +fec); > enum ice_status > ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, > struct ice_sq_cd *cd); > -- > 2.17.1