From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 2E2892BDF for ; Fri, 4 Mar 2016 02:47:24 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP; 03 Mar 2016 17:47:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,533,1449561600"; d="scan'208";a="663522682" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 03 Mar 2016 17:47:08 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 3 Mar 2016 17:47:07 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.232]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.42]) with mapi id 14.03.0248.002; Fri, 4 Mar 2016 09:47:06 +0800 From: "He, Shaopeng" To: "Lu, Wenzhuo" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v4 3/7] ixgbe: support l2 tunnel config Thread-Index: AQHRafapFA0tpafvbUGMzB1XQX05MZ9IiT/w Date: Fri, 4 Mar 2016 01:47:05 +0000 Message-ID: References: <1454051035-25757-1-git-send-email-wenzhuo.lu@intel.com> <1455763573-2867-1-git-send-email-wenzhuo.lu@intel.com> <1455763573-2867-4-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1455763573-2867-4-git-send-email-wenzhuo.lu@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 3/7] ixgbe: support l2 tunnel config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Mar 2016 01:47:24 -0000 Hi Wenzhuo, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu > Sent: Thursday, February 18, 2016 10:46 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v4 3/7] ixgbe: support l2 tunnel config >=20 > Add support of l2 tunnel configuration. > Support modifying ether type of a type of l2 tunnel. > Support enabling and disabling the support of a type of l2 tunnel. > Only E-tag tunnel is supported now. >=20 > Signed-off-by: Wenzhuo Lu > --- > drivers/net/ixgbe/ixgbe_ethdev.c | 140 > +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 140 insertions(+) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c > b/drivers/net/ixgbe/ixgbe_ethdev.c > index b99e48e..b15a4b6 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -139,6 +139,10 @@ > #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL >=20 > #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 > +#define DEFAULT_ETAG_ETYPE 0x893f > +#define IXGBE_ETAG_ETYPE 0x00005084 > +#define IXGBE_ETAG_ETYPE_MASK 0x0000ffff > +#define IXGBE_ETAG_ETYPE_VALID 0x80000000 >=20 > static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev); > static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); > @@ -339,6 +343,14 @@ static int ixgbe_timesync_read_time(struct > rte_eth_dev *dev, > struct timespec *timestamp); > static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, > const struct timespec *timestamp); > +static int ixgbe_dev_l2_tunnel_eth_type_conf > + (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel *l2_tunnel); > +static int ixgbe_dev_l2_tunnel_enable > + (struct rte_eth_dev *dev, > + enum rte_eth_l2_tunnel_type l2_tunnel_type); > +static int ixgbe_dev_l2_tunnel_disable > + (struct rte_eth_dev *dev, > + enum rte_eth_l2_tunnel_type l2_tunnel_type); >=20 > /* > * Define VF Stats MACRO for Non "cleared on read" register > @@ -497,6 +509,9 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops =3D > { > .timesync_adjust_time =3D ixgbe_timesync_adjust_time, > .timesync_read_time =3D ixgbe_timesync_read_time, > .timesync_write_time =3D ixgbe_timesync_write_time, > + .l2_tunnel_eth_type_conf =3D ixgbe_dev_l2_tunnel_eth_type_conf, > + .l2_tunnel_enable =3D ixgbe_dev_l2_tunnel_enable, > + .l2_tunnel_disable =3D ixgbe_dev_l2_tunnel_disable, > }; >=20 > /* > @@ -6201,6 +6216,131 @@ ixgbe_dev_get_dcb_info(struct rte_eth_dev > *dev, > return 0; > } >=20 > +/* Update e-tag ether type */ > +static int > +ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, > + uint16_t ether_type) > +{ > + uint32_t etag_etype; > + > + if (hw->mac.type !=3D ixgbe_mac_X550 && > + hw->mac.type !=3D ixgbe_mac_X550EM_x) { > + return -ENOTSUP; > + } > + > + etag_etype =3D IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); > + etag_etype &=3D ~IXGBE_ETAG_ETYPE_MASK; > + etag_etype |=3D ether_type; > + IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); > + IXGBE_WRITE_FLUSH(hw); > + > + return 0; > +} > + > +/* Config l2 tunnel ether type */ > +static int > +ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, > + struct rte_eth_l2_tunnel *l2_tunnel) > +{ > + int ret =3D 0; > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > + if (l2_tunnel =3D=3D NULL) > + return -EINVAL; > + > + switch (l2_tunnel->l2_tunnel_type) { > + case RTE_L2_TUNNEL_TYPE_E_TAG: > + ret =3D ixgbe_update_e_tag_eth_type(hw, l2_tunnel- > >ether_type); > + break; > + default: > + PMD_DRV_LOG(ERR, "Invalid tunnel type"); > + ret =3D -1; Better to use: ret =3D -EINVAL? > + break; > + } > + > + return ret; > +} > + > +/* Enable e-tag tunnel */ > +static int > +ixgbe_e_tag_enable(struct ixgbe_hw *hw) > +{ > + uint32_t etag_etype; > + > + if (hw->mac.type !=3D ixgbe_mac_X550 && > + hw->mac.type !=3D ixgbe_mac_X550EM_x) { > + return -ENOTSUP; > + } > + > + etag_etype =3D IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); > + etag_etype |=3D IXGBE_ETAG_ETYPE_VALID; > + IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); > + IXGBE_WRITE_FLUSH(hw); > + > + return 0; > +} > + > +/* Enable l2 tunnel */ > +static int > +ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, > + enum rte_eth_l2_tunnel_type l2_tunnel_type) > +{ > + int ret =3D 0; > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > + switch (l2_tunnel_type) { > + case RTE_L2_TUNNEL_TYPE_E_TAG: > + ret =3D ixgbe_e_tag_enable(hw); > + break; > + default: > + PMD_DRV_LOG(ERR, "Invalid tunnel type"); > + ret =3D -1; > + break; > + } > + > + return ret; > +} > + > +/* Disable e-tag tunnel */ > +static int > +ixgbe_e_tag_disable(struct ixgbe_hw *hw) > +{ > + uint32_t etag_etype; > + > + if (hw->mac.type !=3D ixgbe_mac_X550 && > + hw->mac.type !=3D ixgbe_mac_X550EM_x) { > + return -ENOTSUP; > + } > + > + etag_etype =3D IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); > + etag_etype &=3D ~IXGBE_ETAG_ETYPE_VALID; > + IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); > + IXGBE_WRITE_FLUSH(hw); > + > + return 0; > +} > + > +/* Disable l2 tunnel */ > +static int > +ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, > + enum rte_eth_l2_tunnel_type l2_tunnel_type) > +{ > + int ret =3D 0; > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > + switch (l2_tunnel_type) { > + case RTE_L2_TUNNEL_TYPE_E_TAG: > + ret =3D ixgbe_e_tag_disable(hw); > + break; > + default: > + PMD_DRV_LOG(ERR, "Invalid tunnel type"); > + ret =3D -1; > + break; > + } > + > + return ret; > +} > + > static struct rte_driver rte_ixgbe_driver =3D { > .type =3D PMD_PDEV, > .init =3D rte_ixgbe_pmd_init, > -- > 1.9.3