From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50062.outbound.protection.outlook.com [40.107.5.62]) by dpdk.org (Postfix) with ESMTP id 7B364B62 for ; Thu, 2 May 2019 07:46:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sYkJvyiO5MF6tbmSQx34J5i3Jy6wNYm9maaqZ/Ssrfc=; b=fALl/unJOGCSSwoJuqqLmvLMv3BzHGpizdguyJZ6gzKDc6aGbpviojXRi+TM78/9tEE+xPykx4L0H4juIGUuxbajjqqyCsqt4cxuDTF/e4HO7tMep/JGh9sCS19tR94phLAoI6D6OeI6O1VD9BRLnESsyPk+l1CbhVmYOb6n6Og= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB4010.eurprd05.prod.outlook.com (52.134.66.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1856.11; Thu, 2 May 2019 05:46:49 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::e8d5:4aff:902d:6e98]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::e8d5:4aff:902d:6e98%5]) with mapi id 15.20.1856.008; Thu, 2 May 2019 05:46:49 +0000 From: Yongseok Koh To: Honnappa Nagarahalli CC: "jerinj@marvell.com" , Shahaf Shuler , Thomas Monjalon , "dev@dpdk.org" , "bruce.richardson@intel.com" , "pbhagavatula@marvell.com" , "Gavin Hu (Arm Technology China)" , nd Thread-Topic: [PATCH 1/2] build: add option for armv8 crypto extension Thread-Index: AQHVAJ1jFjSOyak/l0SpncZMuk1966ZXU6IA Date: Thu, 2 May 2019 05:46:49 +0000 Message-ID: References: <20190502015806.41497-1-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 459beacc-9464-49f4-ee62-08d6cec1922b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:DB3PR0502MB4010; x-ms-traffictypediagnostic: DB3PR0502MB4010: x-ld-processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtAddr x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 0025434D2D x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(39860400002)(346002)(366004)(376002)(396003)(199004)(189003)(4326008)(7736002)(478600001)(6916009)(86362001)(6246003)(5660300002)(3846002)(76176011)(76116006)(25786009)(68736007)(54906003)(316002)(66066001)(66946007)(66556008)(66446008)(66476007)(64756008)(14454004)(99286004)(305945005)(73956011)(91956017)(83716004)(71190400001)(71200400001)(476003)(486006)(6512007)(229853002)(26005)(8936002)(6486002)(36756003)(81156014)(2616005)(11346002)(33656002)(446003)(81166006)(6436002)(14444005)(53936002)(6116002)(256004)(102836004)(53546011)(186003)(8676002)(82746002)(6506007)(2906002); DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB4010; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: MbyXN0RgjOR0qIMWZdjewixDptuNf0b8BlsqfsSFMXT0Hh9VQ5jxqLgB552SDSz655IuWhzlBcEjbGjzOvZqR3Cy0rNfDMA5lvMeox6m8bDLT85J3kp1SKoQkau2nLdH2uOpf+aVX/pGJXoxOjbFiVrWyPUoeiDLKauxkDyQqC/wfg0Fy6q4AObX9QdiVYuV98e1itWeDtWlDoFDlzIibOYyfZPKIRF9BwiBj8xEPkxJAmiFkweWT5CP+Qg03L/1NoKYHzdePL78iEL/a7Ic0+vkGxfiTzwbNt7PJ7kI8COp76Y2ZCB/DoI2SEvRP+IIeaLxU+r4FbwJdNYPeZREBcrDtmW0U6Rqd1r50sNPBCGTRliqieYMghhQdpMtWCGdKgq6hc9K6kSszkM+fNeMA1Q6yhu8pC2UBYH3ScIcQ8c= Content-Type: text/plain; charset="us-ascii" Content-ID: <5914592403D0E04F9620A8718E219A39@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 459beacc-9464-49f4-ee62-08d6cec1922b X-MS-Exchange-CrossTenant-originalarrivaltime: 02 May 2019 05:46:49.4255 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4010 Subject: Re: [dpdk-dev] [PATCH 1/2] build: add option for armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 May 2019 05:46:51 -0000 > On May 1, 2019, at 9:13 PM, Honnappa Nagarahalli wrote: >=20 >> Per armv8 crypto extension support, make build always enable it by defau= lt >> as long as compiler supports the feature while meson build only enables = it for >> 'default' machine of generic armv8 architecture. For example, specifying= '- >> mcpu=3Dcortex-a72' doesn't enable it but '+crypto' is required in order = to >> enable the feature. >>=20 >> It is also known that not all the armv8 platforms have the crypto extens= ion. >> For example, Mellanox BlueField has a variant which doesn't have it. If = crypto >> enabled binary runs on such a platform, rte_eal_init() fails. >>=20 >> Therefore, an option to control this feature is necessary. It is still e= nabled by >> default but can be selectively disabled by vendors. > The distro/binary portable image needs to be built without crypto. Only t= he crypto drivers need to be built with crypto and at run time we need to h= ook up the correct function pointers. So, IMO, by default crypto should be = disabled and should be enabled in specific target machine configs. I make it enabled by default simply because I don't want to change the curr= ent behavior, no breakage. I also want to hear from others. Jerin, Thomas? >>=20 >> Signed-off-by: Yongseok Koh >> --- >> config/arm/meson.build | 16 +++++++++------- >> config/common_armv8a_linux | 1 + >> drivers/crypto/armv8/Makefile | 4 ++++ >> meson_options.txt | 2 ++ >> mk/machine/armv8a/rte.vars.mk | 4 ++++ >> 5 files changed, 20 insertions(+), 7 deletions(-) >>=20 >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> 7fa6ed3105..3b53842d08 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -8,6 +8,8 @@ march_opt =3D '-march=3D@0@'.format(machine) >> arm_force_native_march =3D false arm_force_default_march =3D (machine = =3D=3D >> 'default') >>=20 >> +crypto_flag =3D get_option('enable_armv8_crypto') ? '+crypto' : '' >> + >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test >> (memcpy_perf_autotest) >> # to determine the best threshold in code. Refer to notes in source >> file @@ -74,14 +76,14 @@ flags_octeontx2_extra =3D [ >> ['RTE_USE_C11_MEM_MODEL', true]] >>=20 >> machine_args_generic =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['default', ['-march=3Darmv8-a+crc' + crypto_flag]], >> ['native', ['-march=3Dnative']], >> - ['0xd03', ['-mcpu=3Dcortex-a53']], >> - ['0xd04', ['-mcpu=3Dcortex-a35']], >> - ['0xd07', ['-mcpu=3Dcortex-a57']], >> - ['0xd08', ['-mcpu=3Dcortex-a72']], >> - ['0xd09', ['-mcpu=3Dcortex-a73']], >> - ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + ['0xd03', ['-mcpu=3Dcortex-a53' + crypto_flag]], >> + ['0xd04', ['-mcpu=3Dcortex-a35' + crypto_flag]], >> + ['0xd07', ['-mcpu=3Dcortex-a57' + crypto_flag]], >> + ['0xd08', ['-mcpu=3Dcortex-a72' + crypto_flag]], >> + ['0xd09', ['-mcpu=3Dcortex-a73' + crypto_flag]], >> + ['0xd0a', ['-mcpu=3Dcortex-a75' + crypto_flag]]] >>=20 >> machine_args_cavium =3D [ >> ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> diff --git a/config/common_armv8a_linux b/config/common_armv8a_linux >> index 72091de1c7..0efa3e2eb2 100644 >> --- a/config/common_armv8a_linux >> +++ b/config/common_armv8a_linux >> @@ -5,6 +5,7 @@ >> #include "common_linux" >>=20 >> CONFIG_RTE_MACHINE=3D"armv8a" >> +CONFIG_RTE_ENABLE_ARMV8_CRYPTO=3Dy >>=20 >> CONFIG_RTE_ARCH=3D"arm64" >> CONFIG_RTE_ARCH_ARM64=3Dy >> diff --git a/drivers/crypto/armv8/Makefile b/drivers/crypto/armv8/Makefi= le >> index f71f6b14a4..867a5206cf 100644 >> --- a/drivers/crypto/armv8/Makefile >> +++ b/drivers/crypto/armv8/Makefile >> @@ -4,6 +4,10 @@ >>=20 >> include $(RTE_SDK)/mk/rte.vars.mk >>=20 >> +ifneq ($(CONFIG_RTE_ENABLE_ARMV8_CRYPTO),y) >> +$(error "Please enable CONFIG_RTE_ENABLE_ARMV8_CRYPTO") endif >> + >> ifneq ($(MAKECMDGOALS),clean) >> ifneq ($(MAKECMDGOALS),config) >> ifeq ($(ARMV8_CRYPTO_LIB_PATH),) >> diff --git a/meson_options.txt b/meson_options.txt index >> 16d9f92c65..4ca09771de 100644 >> --- a/meson_options.txt >> +++ b/meson_options.txt >> @@ -4,6 +4,8 @@ option('allow_invalid_socket_id', type: 'boolean', value= : >> false, >> description: 'allow out-of-range NUMA socket id\'s for platforms that >> don\'t report the value correctly') option('drivers_install_subdir', ty= pe: >> 'string', value: 'dpdk/pmds-', >> description: 'Subdirectory of libdir where to install PMDs. Defaults to >> using a versioned subdirectory.') >> +option('enable_armv8_crypto', type: 'boolean', value: true, >> + description: 'enable armv8 crypto extension') >> option('enable_docs', type: 'boolean', value: false, >> description: 'build documentation') >> option('enable_kmods', type: 'boolean', value: true, diff --git >> a/mk/machine/armv8a/rte.vars.mk b/mk/machine/armv8a/rte.vars.mk index >> 8252efbb7b..4893d01a2d 100644 >> --- a/mk/machine/armv8a/rte.vars.mk >> +++ b/mk/machine/armv8a/rte.vars.mk >> @@ -28,4 +28,8 @@ >> # CPU_LDFLAGS =3D >> # CPU_ASFLAGS =3D >>=20 >> +ifeq ($(CONFIG_RTE_ENABLE_ARMV8_CRYPTO),y) >> MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc+crypto >> +else >> +MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc >> +endif >> -- >> 2.11.0 >=20 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 50C94A0AC5 for ; Thu, 2 May 2019 07:46:54 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 58B271F28; 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Thu, 2 May 2019 05:46:49 +0000 From: Yongseok Koh To: Honnappa Nagarahalli CC: "jerinj@marvell.com" , Shahaf Shuler , Thomas Monjalon , "dev@dpdk.org" , "bruce.richardson@intel.com" , "pbhagavatula@marvell.com" , "Gavin Hu (Arm Technology China)" , nd Thread-Topic: [PATCH 1/2] build: add option for armv8 crypto extension Thread-Index: AQHVAJ1jFjSOyak/l0SpncZMuk1966ZXU6IA Date: Thu, 2 May 2019 05:46:49 +0000 Message-ID: References: <20190502015806.41497-1-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 459beacc-9464-49f4-ee62-08d6cec1922b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4618075)(2017052603328)(7193020); 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A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: MbyXN0RgjOR0qIMWZdjewixDptuNf0b8BlsqfsSFMXT0Hh9VQ5jxqLgB552SDSz655IuWhzlBcEjbGjzOvZqR3Cy0rNfDMA5lvMeox6m8bDLT85J3kp1SKoQkau2nLdH2uOpf+aVX/pGJXoxOjbFiVrWyPUoeiDLKauxkDyQqC/wfg0Fy6q4AObX9QdiVYuV98e1itWeDtWlDoFDlzIibOYyfZPKIRF9BwiBj8xEPkxJAmiFkweWT5CP+Qg03L/1NoKYHzdePL78iEL/a7Ic0+vkGxfiTzwbNt7PJ7kI8COp76Y2ZCB/DoI2SEvRP+IIeaLxU+r4FbwJdNYPeZREBcrDtmW0U6Rqd1r50sNPBCGTRliqieYMghhQdpMtWCGdKgq6hc9K6kSszkM+fNeMA1Q6yhu8pC2UBYH3ScIcQ8c= Content-Type: text/plain; charset="UTF-8" Content-ID: <5914592403D0E04F9620A8718E219A39@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 459beacc-9464-49f4-ee62-08d6cec1922b X-MS-Exchange-CrossTenant-originalarrivaltime: 02 May 2019 05:46:49.4255 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4010 Subject: Re: [dpdk-dev] [PATCH 1/2] build: add option for armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190502054649.DUO_YQ_Y1r-_ZiZFZWvPuoufNebMDCKdNJAOEYGnO0s@z> > On May 1, 2019, at 9:13 PM, Honnappa Nagarahalli wrote: >=20 >> Per armv8 crypto extension support, make build always enable it by defau= lt >> as long as compiler supports the feature while meson build only enables = it for >> 'default' machine of generic armv8 architecture. For example, specifying= '- >> mcpu=3Dcortex-a72' doesn't enable it but '+crypto' is required in order = to >> enable the feature. >>=20 >> It is also known that not all the armv8 platforms have the crypto extens= ion. >> For example, Mellanox BlueField has a variant which doesn't have it. If = crypto >> enabled binary runs on such a platform, rte_eal_init() fails. >>=20 >> Therefore, an option to control this feature is necessary. It is still e= nabled by >> default but can be selectively disabled by vendors. > The distro/binary portable image needs to be built without crypto. Only t= he crypto drivers need to be built with crypto and at run time we need to h= ook up the correct function pointers. So, IMO, by default crypto should be = disabled and should be enabled in specific target machine configs. I make it enabled by default simply because I don't want to change the curr= ent behavior, no breakage. I also want to hear from others. Jerin, Thomas? >>=20 >> Signed-off-by: Yongseok Koh >> --- >> config/arm/meson.build | 16 +++++++++------- >> config/common_armv8a_linux | 1 + >> drivers/crypto/armv8/Makefile | 4 ++++ >> meson_options.txt | 2 ++ >> mk/machine/armv8a/rte.vars.mk | 4 ++++ >> 5 files changed, 20 insertions(+), 7 deletions(-) >>=20 >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> 7fa6ed3105..3b53842d08 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -8,6 +8,8 @@ march_opt =3D '-march=3D@0@'.format(machine) >> arm_force_native_march =3D false arm_force_default_march =3D (machine = =3D=3D >> 'default') >>=20 >> +crypto_flag =3D get_option('enable_armv8_crypto') ? '+crypto' : '' >> + >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test >> (memcpy_perf_autotest) >> # to determine the best threshold in code. Refer to notes in source >> file @@ -74,14 +76,14 @@ flags_octeontx2_extra =3D [ >> ['RTE_USE_C11_MEM_MODEL', true]] >>=20 >> machine_args_generic =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['default', ['-march=3Darmv8-a+crc' + crypto_flag]], >> ['native', ['-march=3Dnative']], >> - ['0xd03', ['-mcpu=3Dcortex-a53']], >> - ['0xd04', ['-mcpu=3Dcortex-a35']], >> - ['0xd07', ['-mcpu=3Dcortex-a57']], >> - ['0xd08', ['-mcpu=3Dcortex-a72']], >> - ['0xd09', ['-mcpu=3Dcortex-a73']], >> - ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + ['0xd03', ['-mcpu=3Dcortex-a53' + crypto_flag]], >> + ['0xd04', ['-mcpu=3Dcortex-a35' + crypto_flag]], >> + ['0xd07', ['-mcpu=3Dcortex-a57' + crypto_flag]], >> + ['0xd08', ['-mcpu=3Dcortex-a72' + crypto_flag]], >> + ['0xd09', ['-mcpu=3Dcortex-a73' + crypto_flag]], >> + ['0xd0a', ['-mcpu=3Dcortex-a75' + crypto_flag]]] >>=20 >> machine_args_cavium =3D [ >> ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> diff --git a/config/common_armv8a_linux b/config/common_armv8a_linux >> index 72091de1c7..0efa3e2eb2 100644 >> --- a/config/common_armv8a_linux >> +++ b/config/common_armv8a_linux >> @@ -5,6 +5,7 @@ >> #include "common_linux" >>=20 >> CONFIG_RTE_MACHINE=3D"armv8a" >> +CONFIG_RTE_ENABLE_ARMV8_CRYPTO=3Dy >>=20 >> CONFIG_RTE_ARCH=3D"arm64" >> CONFIG_RTE_ARCH_ARM64=3Dy >> diff --git a/drivers/crypto/armv8/Makefile b/drivers/crypto/armv8/Makefi= le >> index f71f6b14a4..867a5206cf 100644 >> --- a/drivers/crypto/armv8/Makefile >> +++ b/drivers/crypto/armv8/Makefile >> @@ -4,6 +4,10 @@ >>=20 >> include $(RTE_SDK)/mk/rte.vars.mk >>=20 >> +ifneq ($(CONFIG_RTE_ENABLE_ARMV8_CRYPTO),y) >> +$(error "Please enable CONFIG_RTE_ENABLE_ARMV8_CRYPTO") endif >> + >> ifneq ($(MAKECMDGOALS),clean) >> ifneq ($(MAKECMDGOALS),config) >> ifeq ($(ARMV8_CRYPTO_LIB_PATH),) >> diff --git a/meson_options.txt b/meson_options.txt index >> 16d9f92c65..4ca09771de 100644 >> --- a/meson_options.txt >> +++ b/meson_options.txt >> @@ -4,6 +4,8 @@ option('allow_invalid_socket_id', type: 'boolean', value= : >> false, >> description: 'allow out-of-range NUMA socket id\'s for platforms that >> don\'t report the value correctly') option('drivers_install_subdir', ty= pe: >> 'string', value: 'dpdk/pmds-', >> description: 'Subdirectory of libdir where to install PMDs. Defaults to >> using a versioned subdirectory.') >> +option('enable_armv8_crypto', type: 'boolean', value: true, >> + description: 'enable armv8 crypto extension') >> option('enable_docs', type: 'boolean', value: false, >> description: 'build documentation') >> option('enable_kmods', type: 'boolean', value: true, diff --git >> a/mk/machine/armv8a/rte.vars.mk b/mk/machine/armv8a/rte.vars.mk index >> 8252efbb7b..4893d01a2d 100644 >> --- a/mk/machine/armv8a/rte.vars.mk >> +++ b/mk/machine/armv8a/rte.vars.mk >> @@ -28,4 +28,8 @@ >> # CPU_LDFLAGS =3D >> # CPU_ASFLAGS =3D >>=20 >> +ifeq ($(CONFIG_RTE_ENABLE_ARMV8_CRYPTO),y) >> MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc+crypto >> +else >> +MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc >> +endif >> -- >> 2.11.0 >=20