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Fri, 19 Aug 2016 09:43:36 +0000 From: Nipun Gupta To: Jerin Jacob , "dev@dpdk.org" CC: "thomas.monjalon@6wind.com" , "jianbo.liu@linaro.org" , "viktorin@rehivetech.com" , Hemant Agrawal Thread-Topic: [dpdk-dev] [PATCH] eal/armv8: high-resolution cycle counter Thread-Index: AQHR+Ub9d3myw1YNN06Cd1lxYKxaIqBQA2ag Date: Fri, 19 Aug 2016 09:43:36 +0000 Message-ID: References: <1471521090-21067-1-git-send-email-jerin.jacob@caviumnetworks.com> In-Reply-To: <1471521090-21067-1-git-send-email-jerin.jacob@caviumnetworks.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=nipun.gupta@nxp.com; x-originating-ip: [192.88.169.1] x-ms-office365-filtering-correlation-id: f51befa5-0f2d-43b1-ac27-08d3c8154b13 x-microsoft-exchange-diagnostics: 1; HE1PR0401MB1867; 6:T455d1EsFMwfuOGDHRhSx0ZPz1FtH4erQvQEBOWZkET6GByWnRiYMbo5oVTasipXcAq9xqnKZcoLBzaTauEFMRvAQpH9BclEKOIZ4DV/lrNxIk7vPT9QqUqpRz9xJDo7x9CVgDmxaQQa/RbTmzSsyvn8vG1Dj594OslVMJEfq468hV9eQnl7zK0roeQvFZ7arnhlF0NIqS8gMoHQzhh7OqWY2c2UkqrLDQN6HqKaf2716tQFKucwiekU8Z4+S8XRLpwZ8T4VImJEz2ZWhrjZcXvriFnM5uwNvd5pXNWes7UTptek4+mQ2JZgGWZcbCXwgwYKIgvoNH5HADYqDaRGmQ==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0401MB1867; H:HE1PR0401MB1866.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Aug 2016 09:43:36.5807 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0401MB1867 Subject: Re: [dpdk-dev] [PATCH] eal/armv8: high-resolution cycle counter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Aug 2016 09:43:40 -0000 Hi Jerin, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > Sent: Thursday, August 18, 2016 17:22 > To: dev@dpdk.org > Cc: thomas.monjalon@6wind.com; jianbo.liu@linaro.org; > viktorin@rehivetech.com; Jerin Jacob > Subject: [dpdk-dev] [PATCH] eal/armv8: high-resolution cycle counter >=20 > Existing cntvct_el0 based rte_rdtsc() provides portable > means to get wall clock counter at user space. Typically > it runs at <=3D 100MHz. >=20 > The alternative method to enable rte_rdtsc() for high resolution > wall clock counter is through armv8 PMU subsystem. > The PMU cycle counter runs at CPU frequency, However, > access to PMU cycle counter from user space is not enabled > by default in the arm64 linux kernel. > It is possible to enable cycle counter at user space access > by configuring the PMU from the privileged mode (kernel space). >=20 > by default rte_rdtsc() implementation uses portable > cntvct_el0 scheme. Application can choose the PMU based > implementation with CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU >=20 > Signed-off-by: Jerin Jacob > --- >=20 > The PMU based scheme useful for high accuracy performance profiling. > Find below the example steps to configure the PMU based cycle counter on = an > armv8 machine. >=20 > # git clone https://github.com/jerinjacobk/armv8_pmu_cycle_counter_el0 > # cd armv8_pmu_cycle_counter_el0 > # make > # sudo insmod pmu_el0_cycle_counter.ko > # cd $DPDK_DIR > # make config T=3Darm64-armv8a-linuxapp-gcc > # echo "CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU=3Dy" >> build/.config > # make -j 4 Can we make this kernel module also a part of DPDK. May be in the linuxapp = so that it is also compiled with DPDK? >=20 > --- > .../common/include/arch/arm/rte_cycles_64.h | 33 > ++++++++++++++++++++++ > 1 file changed, 33 insertions(+) >=20 > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > index 14f2612..867a946 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > @@ -45,6 +45,11 @@ extern "C" { > * @return > * The time base for this lcore. > */ > +#ifndef RTE_ARM_EAL_RDTSC_USE_PMU > +/** > + * This call is portable to any ARMv8 architecture, however, typically > + * cntvct_el0 runs at <=3D 100MHz and it may be imprecise for some tasks= . > + */ > static inline uint64_t > rte_rdtsc(void) > { > @@ -53,6 +58,34 @@ rte_rdtsc(void) > asm volatile("mrs %0, cntvct_el0" : "=3Dr" (tsc)); > return tsc; > } > +#else > +/** > + * This is an alternative method to enable rte_rdtsc() with high resolut= ion > + * PMU cycles counter.The cycle counter runs at cpu frequency and this s= cheme > + * uses ARMv8 PMU subsystem to get the cycle counter at userspace, Howev= er, > + * access to PMU cycle counter from user space is not enabled by default= in > + * arm64 linux kernel. > + * It is possible to enable cycle counter at user space access by config= uring > + * the PMU from the privileged mode (kernel space). > + * > + * asm volatile("msr pmintenset_el1, %0" : : "r" ((u64)(0 << 31))); > + * asm volatile("msr pmcntenset_el0, %0" :: "r" BIT(31)); > + * asm volatile("msr pmuserenr_el0, %0" : : "r"(BIT(0) | BIT(2))); > + * asm volatile("mrs %0, pmcr_el0" : "=3Dr" (val)); > + * val |=3D (BIT(0) | BIT(2)); > + * isb(); > + * asm volatile("msr pmcr_el0, %0" : : "r" (val)); In your git repo I see that on cleanup the cycle count register is not disa= bled (PMCNTENCLR_EL0). It shall be better to disable the cycle count regist= er too at module exit. > + * > + */ > +static inline uint64_t > +rte_rdtsc(void) > +{ > + uint64_t tsc; > + > + asm volatile("mrs %0, pmccntr_el0" : "=3Dr"(tsc)); > + return tsc; > +} > +#endif >=20 > static inline uint64_t > rte_rdtsc_precise(void) > -- > 2.5.5 Do you also plan to support performance monitor event counters? Regards, Nipun