From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-he1eur01on0085.outbound.protection.outlook.com [104.47.0.85]) by dpdk.org (Postfix) with ESMTP id 6FC977CCA for ; Thu, 1 Jun 2017 12:25:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=+qnJioTlHpo92pMBtQPmC5x0aZ+FCIFTYjDbbLg5pu0=; b=XQEe8sRcz0cFR+nsitszAbjeVXoGnQCoDcOFCj8ZcwxzRzQWj4qTLTQR2vieTXfrl5GIbOAX0MOjv9vLhXYoGbXh6wj8fAXTvE1XpYQGNGMQeugmRKiHFG6WLTWp6gffysJezJwICelbfTuD8IPxp8d/hCJYS4HqxVotHwPnoiE= Received: from HE1PR0401MB2425.eurprd04.prod.outlook.com (10.168.33.22) by HE1PR0401MB2460.eurprd04.prod.outlook.com (10.168.147.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1124.9; Thu, 1 Jun 2017 10:25:03 +0000 Received: from HE1PR0401MB2425.eurprd04.prod.outlook.com ([fe80::c0d0:93f:4f63:54db]) by HE1PR0401MB2425.eurprd04.prod.outlook.com ([fe80::c0d0:93f:4f63:54db%18]) with mapi id 15.01.1143.012; Thu, 1 Jun 2017 10:25:02 +0000 From: Nipun Gupta To: Jerin Jacob CC: "dev@dpdk.org" , Hemant Agrawal , "harry.van.haaren@intel.com" , "bruce.richardson@intel.com" , "gage.eads@intel.com" , Shreyansh Jain Thread-Topic: [PATCH 10/20] event/dpaa2: add initialization of event device Thread-Index: AQHS1YIR4j81ym1fjEakJ3uVe2ChZqIOlPGAgAE6CVA= Date: Thu, 1 Jun 2017 10:25:02 +0000 Message-ID: References: <1495735671-4917-1-git-send-email-nipun.gupta@nxp.com> <1495735671-4917-11-git-send-email-nipun.gupta@nxp.com> <20170531151003.GB16598@jerin> In-Reply-To: <20170531151003.GB16598@jerin> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: caviumnetworks.com; dkim=none (message not signed) header.d=none; caviumnetworks.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.88.169.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; HE1PR0401MB2460; 7:rdymWVg3kO9zCx6jkrAb8R3sVdF7CR6ptAbK7QLVPiw7RrTXlOUQrl3rOxGpc5DmznXv6k99H/3R5+ph2t0oF6UZmuWXpG8d3Vbbx5og25+1dm3eS1NnzbXnf1xr9O0+IZ7Al99so6W/vc0dlqdVQoBZZrZxpFGjSAvakSyteT+4tOQ0yaeto2myW2hMOZesAsBsu8aO8EuSBaaTnYK5hjlUdGmwBa7TZY1VaqzvPuPkF1qUBhYjMD+Pv5Qs8lRlty5GYesnl/qdzM1vm5duVMToEoQSICZ+S7F6IMLl13WIi83yGKH4Ia0j8l8TnZBfLRfch2N+u8hp/TDir3QSQw== x-forefront-antispam-report: SFV:SKI; SCL:-1SFV:NSPM; SFS:(10009020)(6009001)(39450400003)(39400400002)(39850400002)(39840400002)(39410400002)(39860400002)(13464003)(189998001)(2906002)(7736002)(3846002)(305945005)(6116002)(86362001)(8936002)(3660700001)(5250100002)(6506006)(2900100001)(50986999)(53546009)(76176999)(8676002)(5660300001)(3280700002)(38730400002)(345774005)(6246003)(110136004)(81166006)(6436002)(102836003)(25786009)(54356999)(74316002)(54906002)(33656002)(66066001)(4326008)(55016002)(2950100002)(7696004)(9686003)(14454004)(478600001)(99286003)(53936002)(229853002)(87944003); DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0401MB2460; H:HE1PR0401MB2425.eurprd04.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; x-ms-traffictypediagnostic: HE1PR0401MB2460: x-ms-office365-filtering-correlation-id: 93f40384-efdf-4a62-69e8-08d4a8d876ea x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081); SRVR:HE1PR0401MB2460; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(185117386973197)(275809806118684)(228905959029699); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(93006095)(93001095)(6055026)(6041248)(20161123564025)(20161123560025)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123558100)(6072148); SRVR:HE1PR0401MB2460; BCL:0; PCL:0; RULEID:; SRVR:HE1PR0401MB2460; x-forefront-prvs: 0325F6C77B spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jun 2017 10:25:02.6152 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0401MB2460 Subject: Re: [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Jun 2017 10:25:14 -0000 > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Wednesday, May 31, 2017 20:40 > To: Nipun Gupta > Cc: dev@dpdk.org; Hemant Agrawal ; > harry.van.haaren@intel.com; bruce.richardson@intel.com; > gage.eads@intel.com; Shreyansh Jain > Subject: Re: [PATCH 10/20] event/dpaa2: add initialization of event devic= e >=20 > -----Original Message----- > > Date: Thu, 25 May 2017 23:37:41 +0530 > > From: Nipun Gupta > > To: dev@dpdk.org > > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com, > > harry.van.haaren@intel.com, bruce.richardson@intel.com, > > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta > > > > Subject: [PATCH 10/20] event/dpaa2: add initialization of event device > > X-Mailer: git-send-email 1.9.1 > > > > Signed-off-by: Nipun Gupta > > --- > > drivers/event/dpaa2/dpaa2_eventdev.c | 153 > ++++++++++++++++++++++++++++++++++- > > drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++++ > > 2 files changed, 171 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c > b/drivers/event/dpaa2/dpaa2_eventdev.c > > index 191901e..7fa17f2 100644 > > --- a/drivers/event/dpaa2/dpaa2_eventdev.c > > +++ b/drivers/event/dpaa2/dpaa2_eventdev.c > > @@ -30,17 +30,164 @@ > > * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH > DAMAGE. > > */ > > > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > +#include > > #include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > #include > > +#include > > +#include >=20 > Maintain alphabetical order in header inclusion. Thank you for the review. Regarding this I check most of the c files in DPDK and do not see that alph= abetical being maintained in the header file inclusions. Are you suggesting to have = an alphabetical order here across all inclusions of rte* as well as gcc standard header fil= es (combined) or to have them ordered separately? >=20 > > > > +#include > > +#include > > +#include > > +#include > > #include "dpaa2_eventdev.h" > > +#include > > +#include > > + > > +/* Clarifications > > + * Evendev =3D SoC Instance > > + * Eventport =3D DPIO Instance > > + * Eventqueue =3D DPCON Instance > > + * 1 Eventdev can have N Eventqueue > > + * Soft Event Flow is DPCI Instance > > + */ > > + > > +static uint16_t > > +dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[], > > + uint16_t nb_events) > > +{ > > + RTE_SET_USED(port); > > + RTE_SET_USED(ev); > > + RTE_SET_USED(nb_events); > > + > > + return 0; > > +} > > + > > +static uint16_t > > +dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev) > > +{ > > + return dpaa2_eventdev_enqueue_burst(port, ev, 1); > > +} > > + > > +static uint16_t > > +dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[], > > + uint16_t nb_events, uint64_t timeout_ticks) > > +{ > > + RTE_SET_USED(port); > > + RTE_SET_USED(ev); > > + RTE_SET_USED(nb_events); > > + RTE_SET_USED(timeout_ticks); > > + > > + return 0; > > +} > > + > > +static uint16_t > > +dpaa2_eventdev_dequeue(void *port, struct rte_event *ev, > > + uint64_t timeout_ticks) > > +{ > > + return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks); > > +} > > + > > +static const struct rte_eventdev_ops dpaa2_eventdev_ops; > > + > > +static int > > +dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev, > > + struct dpaa2_dpcon_dev *dpcon_dev) > > +{ > > + struct dpci_rx_queue_cfg rx_queue_cfg; > > + int ret, i; > > + > > + /*Do settings to get the frame on a DPCON object*/ > > + rx_queue_cfg.options =3D DPCI_QUEUE_OPT_DEST; > > + rx_queue_cfg.dest_cfg.dest_type =3D DPCI_DEST_DPCON; > > + rx_queue_cfg.dest_cfg.dest_id =3D dpcon_dev->dpcon_id; > > + rx_queue_cfg.dest_cfg.priority =3D DPAA2_EVENT_DEFAULT_DPCI_PRIO; > > + > > + for (i =3D 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) { > > + rx_queue_cfg.user_ctx =3D (uint64_t)(&dpci_dev->queue[i]); > > + ret =3D dpci_set_rx_queue(&dpci_dev->dpci, > > + CMD_PRI_LOW, > > + dpci_dev->token, i, > > + &rx_queue_cfg); > > + if (ret) { > > + PMD_DRV_LOG(ERR, PMD, > > + "set_rx_q failed with err code: %d", ret); > > + return ret; > > + } > > + } > > + return 0; > > +} > > > > static int > > dpaa2_eventdev_create(const char *name) > > { > > - RTE_SET_USED(name); > > + struct rte_eventdev *eventdev; > > + struct dpaa2_eventdev *priv; > > + struct dpaa2_dpcon_dev *dpcon_dev =3D NULL; > > + struct dpaa2_dpci_dev *dpci_dev =3D NULL; > > + int ret; > > + > > + eventdev =3D rte_event_pmd_vdev_init(name, > > + sizeof(struct dpaa2_eventdev), > > + rte_socket_id()); > > + if (eventdev =3D=3D NULL) { > > + PMD_DRV_ERR("Failed to create eventdev vdev %s", name); > > + goto fail; > > + } > > + > > + eventdev->dev_ops =3D &dpaa2_eventdev_ops; > > + eventdev->schedule =3D NULL; > > + eventdev->enqueue =3D dpaa2_eventdev_enqueue; > > + eventdev->enqueue_burst =3D dpaa2_eventdev_enqueue_burst; > > + eventdev->dequeue =3D dpaa2_eventdev_dequeue; > > + eventdev->dequeue_burst =3D dpaa2_eventdev_dequeue_burst; >=20 > If it makes senses, you can return from here if its in multi process mode= . Makes sense. Ill update this in next version. >=20 > > + > > + priv =3D eventdev->data->dev_private; > > + priv->max_event_queues =3D 0; > > + > > + do { > > + dpcon_dev =3D rte_dpaa2_alloc_dpcon_dev(); > > + if (!dpcon_dev) > > + break; > > + priv->evq_info[priv->max_event_queues].dpcon =3D dpcon_dev; > > + > > + dpci_dev =3D rte_dpaa2_alloc_dpci_dev(); > > + if (!dpci_dev) { > > + rte_dpaa2_free_dpcon_dev(dpcon_dev); > > + break; > > + } > > + priv->evq_info[priv->max_event_queues].dpci =3D dpci_dev; > > + > > + ret =3D dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev); > > + if (ret) { > > + PMD_DRV_LOG(ERR, PMD, > > + "dpci setup failed with err code: %d", ret); > > + return ret; > > + } > > + priv->max_event_queues++; > > + } while (dpcon_dev && dpci_dev); > > > > return 0; > > +fail: > > + return -EFAULT; > > } > > > > static int > > @@ -61,9 +208,7 @@ > > name =3D rte_vdev_device_name(vdev); > > PMD_DRV_LOG(INFO, "Closing %s", name); > > > > - RTE_SET_USED(name); > > - > > - return 0; > > + return rte_event_pmd_vdev_uninit(name); > > }