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Sat, 5 May 2018 19:09:42 +0000 From: Shreyansh Jain To: "Xu, Rosen" , "dev@dpdk.org" CC: "declan.doherty@intel.com" , "bruce.richardson@intel.com" , "ferruh.yigit@intel.com" , "konstantin.ananyev@intel.com" , "tianfei.zhang@intel.com" , "song.liu@intel.com" , "hao.wu@intel.com" , "gaetan.rivet@6wind.com" , Yanglong Wu Thread-Topic: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Thread-Index: AQHT47GY0MJEDKQIGk+RCUT9+nzeb6QhgGvQ Date: Sat, 5 May 2018 19:09:32 +0000 Deferred-Delivery: Sat, 5 May 2018 19:08:32 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525443062-43231-1-git-send-email-rosen.xu@intel.com> <1525443062-43231-4-git-send-email-rosen.xu@intel.com> In-Reply-To: <1525443062-43231-4-git-send-email-rosen.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; x-originating-ip: [14.142.187.166] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 21388b91-c836-4e69-7ba5-08d5b2bbc1f5 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 21388b91-c836-4e69-7ba5-08d5b2bbc1f5 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 May 2018 19:09:42.4106 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3626 Subject: Re: [dpdk-dev] [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 May 2018 19:09:47 -0000 Though I had already acked this, I had a quick comment: > -----Original Message----- > From: Xu, Rosen [mailto:rosen.xu@intel.com] > Sent: Friday, May 4, 2018 7:41 PM > To: dev@dpdk.org > Cc: rosen.xu@intel.com; declan.doherty@intel.com; > bruce.richardson@intel.com; Shreyansh Jain ; > ferruh.yigit@intel.com; konstantin.ananyev@intel.com; > tianfei.zhang@intel.com; song.liu@intel.com; hao.wu@intel.com; > gaetan.rivet@6wind.com; Yanglong Wu > Subject: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver >=20 > From: Rosen Xu >=20 > Add Intel FPGA BUS Rawdev Driver which is based on > librte_rawdev library. >=20 > Signed-off-by: Rosen Xu > Signed-off-by: Yanglong Wu > Signed-off-by: Figo zhang > --- [...] > diff --git a/mk/rte.app.mk b/mk/rte.app.mk > index f47bbe8..b0a994f 100644 > --- a/mk/rte.app.mk > +++ b/mk/rte.app.mk > @@ -253,6 +253,7 @@ endif # CONFIG_RTE_LIBRTE_EVENTDEV >=20 > ifeq ($(CONFIG_RTE_LIBRTE_RAWDEV),y) > _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV) +=3D - > lrte_pmd_skeleton_rawdev > +_LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_RAWDEV) +=3D -lrte_ifpga_rawdev > endif # CONFIG_RTE_LIBRTE_RAWDEV This driver is dependent on CONFIG_RTE_LIBRTE_IFPGA_BUS and if someone disa= bles that, it would lead to build issues. I think you should enclose the IF= PGA_RAWDEV compilation into conditional for CONFIG_RTE_LIBRTE_IFPGA_BUS=3Dy= . Though, I do faintly remember a discussion in past that such thing should/c= an be left to individual environment configuration and it can be safely ass= umed that such erroneous configuration would be user-responsibility (at lea= st until a dependency based configuration system is available in DPDK). So,= it is a good-to-have rather a necessity. >=20 >=20 > -- > 1.8.3.1