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Wed, 4 Apr 2018 10:14:26 +0000 From: Shreyansh Jain To: Rosen Xu , "dev@dpdk.org" CC: "declan.doherty@intel.com" , "bruce.richardson@intel.com" , "ferruh.yigit@intel.com" , "konstantin.ananyev@intel.com" , "tianfei.zhang@intel.com" , "hao.wu@intel.com" , "gaetan.rivet@6wind.com" Thread-Topic: [PATCH v5 0/3] Introduce Intel FPGA BUS Thread-Index: AQHTy+EI0CMXOCyzI0yrFj/LKNGRFaPwYeJg Date: Wed, 4 Apr 2018 10:14:22 +0000 Deferred-Delivery: Wed, 4 Apr 2018 10:13:41 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522824677-86958-1-git-send-email-rosen.xu@intel.com> In-Reply-To: <1522824677-86958-1-git-send-email-rosen.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; x-originating-ip: [92.121.36.197] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; HE1PR0402MB2905; 7:cozP4dd6dtvo13bSEO3T2T/24wyFgurwdY26+EzWqsFpoCsjmhofvjwGjWdi0YIEO318B2jvPhTo0rg9eTJFvsWVytZ8ipyCBPdCiXZgoII9yAgulEmDRfTbinkIunYFAuDkR0oIFxkiEl6oPDPbOkVu9psyC6uCX1zTeu/jPIkpf5a+aR9Ksk6RxG2BU2eaxIBvBFfpMbFUsc0INAtb/JO0cK2ypiDD9KgIq+ZE4OZTIIAXsrJSc83x1wktYXNz x-ms-exchange-antispam-srfa-diagnostics: SOS; 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DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0402MB2905; H:HE1PR0402MB2780.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: naG++OxdX2ppPcgG0TovcQN1aYvTUaBo8Tt955vGX5CLa0CX1pq1iA+84Rx8W1TuAXYJOhxokYXRI1/inM3zWa2PX1rD2Qkx2W0TLg1lnsz8xS/GopatHFHFxEzyE7eHKPhvuX07H24N1z/R4QzyW0QkhINmeGXmiz39dYfZdZHG1Ybi5OUCzk14syyYGDGM0xE835IGJppx2tBuqYd3xhaJhOPLkDU4j79iOhIhPIcEsKaJ1uUGvQzldEVKpnj/HstEidWefinqTmTOGaW46o3NMqfjMsA1sVTQ8hFLcQkfwNXW871xUS7TNe0dHnxt6i/YDVQ0+026OuJDFd9pk7wvn/GubKXayv3oQNh1FGbB4ahowEqI7IhTuwEWU+HogtB1VOfB47weESVBItz+4Dd1WdLNyPEuakjTFBNYgYY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5e5e86ac-0e46-4edb-9ce4-08d59a14d83c X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2018 10:14:25.8636 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB2905 Subject: Re: [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Apr 2018 10:14:28 -0000 Hello Rosen, > -----Original Message----- > From: Rosen Xu [mailto:rosen.xu@intel.com] > Sent: Wednesday, April 4, 2018 12:21 PM > To: dev@dpdk.org > Cc: declan.doherty@intel.com; bruce.richardson@intel.com; Shreyansh Jain > ; ferruh.yigit@intel.com; > konstantin.ananyev@intel.com; tianfei.zhang@intel.com; hao.wu@intel.com; > gaetan.rivet@6wind.com > Subject: [PATCH v5 0/3] Introduce Intel FPGA BUS >=20 > Intel FPGA BUS in DPDK > ------------------------- >=20 > This patch set introduces Intel FPGA BUS support in DPDK. >=20 > v5 updates: > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > - Fixed SHARED LIB Build issue > - Changed command name to IFPGA Rawdev name, > so remove pci library datastruct and function. > - Fixed PATCH v2/v3/v4 comments >=20 [...] Primary problems I see with your patches: 1. They are not split enough. Still the patch 2/3 is dependent on 3/3. That= mean, it would break the compilation. There is no simpler way to solve thi= s except breaking the patch into multiple patches and slowly introducing ea= ch function/feature. (One obvious way would be to have 3/3 as 2/3 and vice-versa - Not sure wha= t that blocks). 2. Documentation - there is none right now. Being a special use case for PC= I, I think a lot of people would benefit if you can explain the comments ab= out why iFPGA bus is required through documentation. 3. Meson as requested by Bruce. Problem you will face is that rawdev doesn'= t yet have meson enabled. I will work on that. If you can still rework your= patches for (1)+(2), I think meson enable over rawdev would be trivial. Other issues being license plate in opae code not being SPDX. But, I will l= eave that you and maintainers to decice.