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Sun, 6 May 2018 11:54:19 +0000 From: Shreyansh Jain To: "Xu, Rosen" , "dev@dpdk.org" , "thomas@monjalon.net" CC: "declan.doherty@intel.com" , "bruce.richardson@intel.com" , "ferruh.yigit@intel.com" , "konstantin.ananyev@intel.com" , "tianfei.zhang@intel.com" , "song.liu@intel.com" , "hao.wu@intel.com" , "gaetan.rivet@6wind.com" Thread-Topic: [PATCH v8 5/5] iFPGA: add document for iFPGA driver Thread-Index: AQHT5RXLVrCQs4I6FkCoN4kLyepoX6QilfrQ Date: Sun, 6 May 2018 11:54:17 +0000 Deferred-Delivery: Sun, 6 May 2018 11:53:27 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525596044-84881-1-git-send-email-rosen.xu@intel.com> <1525596044-84881-6-git-send-email-rosen.xu@intel.com> In-Reply-To: <1525596044-84881-6-git-send-email-rosen.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; x-originating-ip: [122.177.192.50] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: af61b309-51d2-4e7d-7db9-08d5b34819b1 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: af61b309-51d2-4e7d-7db9-08d5b34819b1 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 May 2018 11:54:19.0685 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3337 Subject: Re: [dpdk-dev] [PATCH v8 5/5] iFPGA: add document for iFPGA driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 06 May 2018 11:54:23 -0000 Hi Rosen, > -----Original Message----- > From: Xu, Rosen [mailto:rosen.xu@intel.com] > Sent: Sunday, May 6, 2018 2:11 PM > To: dev@dpdk.org > Cc: rosen.xu@intel.com; declan.doherty@intel.com; > bruce.richardson@intel.com; Shreyansh Jain ; > ferruh.yigit@intel.com; konstantin.ananyev@intel.com; > tianfei.zhang@intel.com; song.liu@intel.com; hao.wu@intel.com; > gaetan.rivet@6wind.com > Subject: [PATCH v8 5/5] iFPGA: add document for iFPGA driver >=20 > From: Figo Zhang >=20 > add some introduction, motivation and usage for iFPGA driver. >=20 > Signed-off-by: Rosen Xu > Signed-off-by: Figo Zhang > --- > doc/guides/rawdevs/ifpga_rawdev.rst | 112 > +++++++++++++++++++++++++++++++++ > doc/guides/rel_notes/release_18_05.rst | 13 ++++ > 2 files changed, 125 insertions(+) > create mode 100644 doc/guides/rawdevs/ifpga_rawdev.rst >=20 > diff --git a/doc/guides/rawdevs/ifpga_rawdev.rst > b/doc/guides/rawdevs/ifpga_rawdev.rst > new file mode 100644 > index 0000000..37ae4cc > --- /dev/null > +++ b/doc/guides/rawdevs/ifpga_rawdev.rst > @@ -0,0 +1,112 @@ > +.. SPDX-License-Identifier: BSD-3-Clause > + Copyright(c) 2018 Intel Corporation. > + > +IFPGA Rawdev Driver > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +FPGA is used more and more widely in Cloud and NFV, one primary reason > is > +that FPGA not only provides ASIC performance but also it's more > flexible > +than ASIC. > + > +FPGA uses Partial Reconfigure (PR) Parts of Bit Stream to achieve its > +flexibility. That means one FPGA Device Bit Stream is divided into > many Parts > +of Bit Stream(each Part of Bit Stream is defined as AFU-Accelerated > Function > +Unit), and each AFU is a hardware acceleration unit which can be > dynamically > +reloaded respectively. > + > +By PR (Partial Reconfiguration) AFUs, one FPGA resources can be time- > shared by > +different users. FPGA hot upgrade and fault tolerance can be provided > easily. > + > +The SW IFPGA Rawdev Driver (**ifpga_rawdev**) provides a Rawdev driver > +that utilizes Intel FPGA Software Stack OPAE(Open Programmable > Acceleration > +Engine) for FPGA management. > + > +Implementation details > +---------------------- > + > +Each instance of IFPGA Rawdev Driver is probed by Intel FpgaDev. In > coordination > +with OPAE share code IFPGA Rawdev Driver provides common FPGA > management ops > +for FPGA operation, OPAE provides all following operations: > +- FPGA PR (Partial Reconfiguration) management > +- FPGA AFUs Identifying > +- FPGA Thermal Management > +- FPGA Power Management > +- FPGA Performance reporting > +- FPGA Remote Debug > + > +All configuration parameters are taken by vdev_ifpga_cfg driver. > Besides > +configuration, vdev_ifpga_cfg driver also hot plugs in IFPGA Bus. > + > +All of the AFUs of one FPGA may share same PCI BDF and AFUs scan > depend on > +IFPGA Rawdev Driver so IFPGA Bus takes AFU device scan and AFU drivers > probe. > +All AFU device driver bind to AFU device by its UUID (Universally > Unique > +Identifier). > + > +To avoid unnecessary code duplication and ensure maximum performance, > +handling of AFU devices is left to different PMDs; all the design as > +summarized by the following block diagram:: > + > + +---------------------------------------------------------------+ > + | Application(s) | > + +----------------------------.----------------------------------+ > + | > + | > + +----------------------------'----------------------------------+ > + | DPDK Framework (APIs) | > + +----------|------------|--------.---------------------|--------+ > + / \ | > + / \ | > + +-------'-------+ +-------'-------+ +--------'--------+ > + | Eth PMD | | Crypto PMD | | | > + +-------.-------+ +-------.-------+ | | > + | | | | > + | | | | > + +-------'-------+ +-------'-------+ | IFPGA | > + | Eth AFU Dev | |Crypto AFU Dev | | Rawdev Driver | > + +-------.-------+ +-------.-------+ |(OPAE Share Code)| > + | | | | > + | | Rawdev | | > + +-------'------------------'-------+ Ops | | > + | IFPGA Bus | -------->| | > + +-----------------.----------------+ +--------.--------+ > + | | > + Hot-plugin -->| | > + | | > + +-----------------'------------------+ +--------'--------+ > + | vdev_ifpga_cfg driver | | Intel FpgaDev | > + +------------------------------------+ +-----------------+ > + > +Build options > +------------- > + > +- ``CONFIG_RTE_LIBRTE_IFPGA_BUS`` (default ``y``) > + > + Toggle compilation of IFPGA Bus library. > + > +- ``CONFIG_RTE_LIBRTE_IFPGA_RAWDEV`` (default ``y``) > + > + Toggle compilation of the ``ifpga_rawdev`` driver. > + > +Run-time parameters > +------------------- > + > +This driver is invoked automatically in systems added with Intel FPGA, > +but PR and IFPGA Bus scan is trigged by command line using > +``--vdev 'net_ifpga_cfg`` EAL option. > + > +The following device parameters are supported: > + > +- ``ifpga`` [string] > + > + Provide a specific Intel FPGA device PCI BDF. Can be provided > multiple > + times for additional instances. > + > +- ``port`` [int] > + > + Each FPGA can provide many channels to PR AFU by software, each > channels > + is identified by this parameter. > + > +- ``afu_bts`` [string] > + > + If null, the AFU Bit Stream has been PR in FPGA, if not forces PR > and > + identifies AFU Bit Stream file. [...] If you don't introduce this file into doc/guides/rawdevs/index.rst (like yo= ur v7), the doc index won't be generated. I think you misunderstood my comment in [1] - I meant that you will have to= rebase over CMDIF because it has already introduced the doc/guides/rawdevs= /index.rst file. Your patch v7 was adding this file. It would have conflict= ed for Thomas' eventual merge. [1] http://dpdk.org/ml/archives/dev/2018-May/100313.html Unfortunately, you might have to send a v9 or maybe Thomas can take care of= this while merging.