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SFP:1101; X-MS-Office365-Filtering-Correlation-Id-Prvs: 402ecba6-8d59-466e-bcbc-08d82c78060b X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Cl8JbY2bxY02ltrJhVQji/GaGy1M52nvuGUhstI2h8uts5g0bgDoSYvq1J44II3urOaLwRTXjVTSSMMvnOLSMqLIEhMdf/35huuDeBOtbIqN7YIIFkR9hpcneBSsxR9u0UMqJwK/pVG76ggdcdpsTtDwqTlZB7cJBbH/yUxxmD6UFQ94lcNlYFfbCDIzaPj0Dk+nMHhejVLwPW9zxomFU5YEMCjKUAPYzNE5xBiF+9z0KxIJgfOvgOlHSc9CWHRv/Kr4S2Dz/eC7oCplTMkhBEFw29atKmKcpK8BCPynYbJpeIAj1H93xNmZ6yzpS5/sslIns914aZR5J0ZEnt5qw8t0GiLO58+zzO+sJux1kwNzfoiPQdJBTpbKKvOp5qysmMf6FbqR61Gx4uyD3fCNEA== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2020 06:42:15.7341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a298750-7f30-4c03-ab33-08d82c780a91 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT013.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB3972 Subject: Re: [dpdk-dev] [PATCH v8 1/4] eal: add WC store functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Radu Nicolau > Sent: Friday, July 17, 2020 6:50 PM > To: dev@dpdk.org > Cc: beilei.xing@intel.com; jia.guo@intel.com; bruce.richardson@intel.com; > konstantin.ananyev@intel.com; jerinjacobk@gmail.com; > david.marchand@redhat.com; fiona.trahe@intel.com; wei.zhao1@intel.com; > Ruifeng Wang ; Radu Nicolau > > Subject: [PATCH v8 1/4] eal: add WC store functions >=20 > Add rte_write32_wc and rte_write32_wc_relaxed functions that implement > 32bit stores using write combining memory protocol. > Provided generic stubs and x86 implementation. >=20 > Signed-off-by: Radu Nicolau > Acked-by: Bruce Richardson > --- > lib/librte_eal/arm/include/rte_io_64.h | 12 +++++++ > lib/librte_eal/include/generic/rte_io.h | 48 > ++++++++++++++++++++++++++++ > lib/librte_eal/x86/include/rte_io.h | 56 > +++++++++++++++++++++++++++++++++ > 3 files changed, 116 insertions(+) >=20 > diff --git a/lib/librte_eal/arm/include/rte_io_64.h > b/lib/librte_eal/arm/include/rte_io_64.h > index e534624..d07d9cb 100644 > --- a/lib/librte_eal/arm/include/rte_io_64.h > +++ b/lib/librte_eal/arm/include/rte_io_64.h > @@ -164,6 +164,18 @@ rte_write64(uint64_t value, volatile void *addr) > rte_write64_relaxed(value, addr); > } >=20 > +static __rte_always_inline void > +rte_write32_wc(uint32_t value, volatile void *addr) { > + rte_write32(value, addr); > +} > + > +static __rte_always_inline void > +rte_write32_wc_relaxed(uint32_t value, volatile void *addr) { > + rte_write32_relaxed(value, addr); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/include/generic/rte_io.h > b/lib/librte_eal/include/generic/rte_io.h > index da457f7..0669baa 100644 > --- a/lib/librte_eal/include/generic/rte_io.h > +++ b/lib/librte_eal/include/generic/rte_io.h > @@ -229,6 +229,40 @@ rte_write32(uint32_t value, volatile void *addr); > static inline void rte_write64(uint64_t value, volatile void *addr); >=20 > +/** > + * Write a 32-bit value to I/O device memory address addr using write > + * combining memory write protocol. Depending on the platform write > +combining > + * may not be available and/or may be treated as a hint and the > +behavior may > + * fallback to a regular store. I'm trying to understand write combining use cases here. Is it applicable for all MMIO writes?=20 How to identify where to use rte_write32_wc(_relaxed)? Thanks. /Ruifeng > + * > + * @param value > + * Value to write > + * @param addr > + * I/O memory address to write the value to */ __rte_experimental > +static inline void rte_write32_wc(uint32_t value, volatile void *addr); > + > +/** > + * Write a 32-bit value to I/O device memory address addr using write > + * combining memory write protocol. Depending on the platform write > +combining > + * may not be available and/or may be treated as a hint and the > +behavior may > + * fallback to a regular store. > + * > + * The relaxed version does not have additional I/O memory barrier, > +useful in > + * accessing the device registers of integrated controllers which > +implicitly > + * strongly ordered with respect to memory access. > + * > + * @param value > + * Value to write > + * @param addr > + * I/O memory address to write the value to */ __rte_experimental > +static inline void rte_write32_wc_relaxed(uint32_t value, volatile void > +*addr); > + > #endif /* __DOXYGEN__ */ >=20 > #ifndef RTE_OVERRIDE_IO_H > @@ -345,6 +379,20 @@ rte_write64(uint64_t value, volatile void *addr) > rte_write64_relaxed(value, addr); > } >=20 > +#ifndef RTE_NATIVE_WRITE32_WC > +static __rte_always_inline void > +rte_write32_wc(uint32_t value, volatile void *addr) { > + rte_write32(value, addr); > +} > + > +static __rte_always_inline void > +rte_write32_wc_relaxed(uint32_t value, volatile void *addr) { > + rte_write32_relaxed(value, addr); > +} > +#endif /* RTE_NATIVE_WRITE32_WC */ > + > #endif /* RTE_OVERRIDE_IO_H */ >=20 > #endif /* _RTE_IO_H_ */ > diff --git a/lib/librte_eal/x86/include/rte_io.h > b/lib/librte_eal/x86/include/rte_io.h > index 2db71b1..c95ed67 100644 > --- a/lib/librte_eal/x86/include/rte_io.h > +++ b/lib/librte_eal/x86/include/rte_io.h > @@ -9,8 +9,64 @@ > extern "C" { > #endif >=20 > +#include "rte_cpuflags.h" > + > +#define RTE_NATIVE_WRITE32_WC > #include "generic/rte_io.h" >=20 > +/** > + * @internal > + * MOVDIRI wrapper. > + */ > +static __rte_always_inline void > +_rte_x86_movdiri(uint32_t value, volatile void *addr) { > + asm volatile( > + /* MOVDIRI */ > + ".byte 0x40, 0x0f, 0x38, 0xf9, 0x02" > + : > + : "a" (value), "d" (addr)); > +} > + > +static __rte_always_inline void > +rte_write32_wc(uint32_t value, volatile void *addr) { > + static int _x86_movdiri_flag =3D -1; > + if (_x86_movdiri_flag =3D=3D 1) { > + rte_wmb(); > + _rte_x86_movdiri(value, addr); > + } else if (_x86_movdiri_flag =3D=3D 0) { > + rte_write32(value, addr); > + } else { > + _x86_movdiri_flag =3D > + > (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIRI) > 0); > + if (_x86_movdiri_flag =3D=3D 1) { > + rte_wmb(); > + _rte_x86_movdiri(value, addr); > + } else { > + rte_write32(value, addr); > + } > + } > +} > + > +static __rte_always_inline void > +rte_write32_wc_relaxed(uint32_t value, volatile void *addr) { > + static int _x86_movdiri_flag =3D -1; > + if (_x86_movdiri_flag =3D=3D 1) { > + _rte_x86_movdiri(value, addr); > + } else if (_x86_movdiri_flag =3D=3D 0) { > + rte_write32_relaxed(value, addr); > + } else { > + _x86_movdiri_flag =3D > + > (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIRI) > 0); > + if (_x86_movdiri_flag =3D=3D 1) > + _rte_x86_movdiri(value, addr); > + else > + rte_write32_relaxed(value, addr); > + } > +} > + > #ifdef __cplusplus > } > #endif > -- > 2.7.4