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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(39860400002)(136003)(396003)(376002)(346002)(46966005)(4326008)(356005)(83380400001)(53546011)(5660300002)(47076004)(6506007)(70586007)(81166007)(186003)(70206006)(2906002)(9686003)(52536014)(82740400003)(7696005)(8936002)(316002)(86362001)(55016002)(15650500001)(336012)(478600001)(8676002)(110136005)(82310400002)(54906003)(26005)(36906005)(33656002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2020 03:41:49.6216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddfcd3cb-1b78-47e3-a83f-08d84328a3af X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB4561 Subject: Re: [dpdk-dev] [PATCH v3] eal/arm64: update CPU flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Wei Hu (Xavier) > Sent: Tuesday, August 18, 2020 10:44 AM > To: dev@dpdk.org > Cc: xavier.huwei@huawei.com; nd ; Honnappa Nagarahalli > ; Ruifeng Wang > ; jerinjacobk@gmail.com > Subject: [PATCH v3] eal/arm64: update CPU flags >=20 > From: "Wei Hu (Xavier)" >=20 > SVE is the next-generation SIMD extension of the ARMv8-A AArch64 > instruction set. > The related marco definition can be found in linux kernel: > arch/arm64/include/uapi/asm/hwcap.h >=20 > This patch updates cpu SVE flags on ARM64 platform, such as SVE, etc. >=20 > Signed-off-by: Chengwen Feng > Signed-off-by: Wei Hu (Xavier) > --- > v2 -> v3: > 1. Change commit log. > 2. Add HWCAP2_FLAGM2 and HWCAP2_FRINT to > rte_cpu_feature_table[]. > 3. Add the flags for newly added items into enum rte_cpu_flag_t. > v1 -> v2: > Adds more sve-related definition to rte_cpu_feature_table, > sunch as SVE2, etc. > --- > lib/librte_eal/arm/include/rte_cpuflags_64.h | 13 +++++++++++++ > lib/librte_eal/arm/rte_cpuflags.c | 13 +++++++++++++ > 2 files changed, 26 insertions(+) >=20 How about updating test_cpuflags() too to cover these new flags? Thanks. /Ruifeng > diff --git a/lib/librte_eal/arm/include/rte_cpuflags_64.h > b/lib/librte_eal/arm/include/rte_cpuflags_64.h > index 95cc01474..aa7a56d49 100644 > --- a/lib/librte_eal/arm/include/rte_cpuflags_64.h > +++ b/lib/librte_eal/arm/include/rte_cpuflags_64.h > @@ -22,6 +22,19 @@ enum rte_cpu_flag_t { > RTE_CPUFLAG_SHA2, > RTE_CPUFLAG_CRC32, > RTE_CPUFLAG_ATOMICS, > + RTE_CPUFLAG_SVE, > + RTE_CPUFLAG_SVE2, > + RTE_CPUFLAG_SVEAES, > + RTE_CPUFLAG_SVEPMULL, > + RTE_CPUFLAG_SVEBITPERM, > + RTE_CPUFLAG_SVESHA3, > + RTE_CPUFLAG_SVESM4, > + RTE_CPUFLAG_FLAGM2, > + RTE_CPUFLAG_FRINT, > + RTE_CPUFLAG_SVEI8MM, > + RTE_CPUFLAG_SVEF32MM, > + RTE_CPUFLAG_SVEF64MM, > + RTE_CPUFLAG_SVEBF16, > RTE_CPUFLAG_AARCH64, > /* The last item */ > RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ > diff --git a/lib/librte_eal/arm/rte_cpuflags.c > b/lib/librte_eal/arm/rte_cpuflags.c > index caf3dc83a..7b257b787 100644 > --- a/lib/librte_eal/arm/rte_cpuflags.c > +++ b/lib/librte_eal/arm/rte_cpuflags.c > @@ -95,6 +95,19 @@ const struct feature_entry rte_cpu_feature_table[] =3D= { > FEAT_DEF(SHA2, REG_HWCAP, 6) > FEAT_DEF(CRC32, REG_HWCAP, 7) > FEAT_DEF(ATOMICS, REG_HWCAP, 8) > + FEAT_DEF(SVE, REG_HWCAP, 22) > + FEAT_DEF(SVE2, REG_HWCAP2, 1) > + FEAT_DEF(SVEAES, REG_HWCAP2, 2) > + FEAT_DEF(SVEPMULL, REG_HWCAP2, 3) > + FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4) > + FEAT_DEF(SVESHA3, REG_HWCAP2, 5) > + FEAT_DEF(SVESM4, REG_HWCAP2, 6) > + FEAT_DEF(FLAGM2, REG_HWCAP2, 7) > + FEAT_DEF(FRINT, REG_HWCAP2, 8) > + FEAT_DEF(SVEI8MM, REG_HWCAP2, 9) > + FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) > + FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) > + FEAT_DEF(SVEBF16, REG_HWCAP2, 12) > FEAT_DEF(AARCH64, REG_PLATFORM, 1) > }; > #endif /* RTE_ARCH */ > -- > 2.27.0