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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(39850400004)(396003)(346002)(376002)(46966005)(336012)(316002)(2906002)(478600001)(9686003)(81166007)(55016002)(86362001)(110136005)(54906003)(356005)(8936002)(186003)(4326008)(82740400003)(33656002)(47076004)(6506007)(53546011)(83380400001)(70206006)(70586007)(82310400003)(7696005)(8676002)(5660300002)(26005)(52536014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2020 02:59:40.0591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 978eaa53-3f1d-4ee2-bb1d-08d86f24071c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4690 Subject: Re: [dpdk-dev] [PATCH v6] eal: add cache-line demote support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Omkar Maslekar > Sent: Monday, October 12, 2020 6:20 PM > To: dev@dpdk.org > Cc: bruce.richardson@intel.com; ciara.loftus@intel.com; > omkar.maslekar@intel.com; drc@linux.vnet.ibm.com; jerinj@marvell.com; > Ruifeng Wang ; Honnappa Nagarahalli > > Subject: [PATCH v6] eal: add cache-line demote support >=20 > rte_cldemote is similar to a prefetch hint - in reverse. cldemote(addr) > enables software to hint to hardware that line is likely to be shared. > Useful in core-to-core communications where cache-line is likely to be > shared. ARM and PPC implementation is provided with NOP and can be > added if any equivalent instructions could be used for implementation on > those architectures. >=20 > Signed-off-by: Omkar Maslekar > Acked-by: Bruce Richardson >=20 > --- > v6: marked rte_cldemote as experimental > added rte_cldemote call in existing app/test_prefetch.c >=20 > v5: documentation updated > fixed formatting issue in release notes > added Acked-by: Bruce Richardson > * > v4: updated bold text for title and fixed margin in release notes > * > v3: fixed warning regarding whitespace > * > v2: documentation updated > --- > --- > app/test/test_prefetch.c | 4 ++++ > doc/guides/rel_notes/release_20_11.rst | 7 +++++++ > lib/librte_eal/arm/include/rte_prefetch_32.h | 8 ++++++++ > lib/librte_eal/arm/include/rte_prefetch_64.h | 8 ++++++++ > lib/librte_eal/include/generic/rte_prefetch.h | 16 ++++++++++++++++ > lib/librte_eal/ppc/include/rte_prefetch.h | 8 ++++++++ > lib/librte_eal/x86/include/rte_prefetch.h | 12 ++++++++++++ > 7 files changed, 63 insertions(+) >=20 > diff --git a/app/test/test_prefetch.c b/app/test/test_prefetch.c index > 41f219a..5c58d0c 100644 > --- a/app/test/test_prefetch.c > +++ b/app/test/test_prefetch.c > @@ -26,7 +26,11 @@ > rte_prefetch1(&a); > rte_prefetch2(&a); >=20 > +/* test for marking a line as shared to test cldemote functionality */ > + rte_cldemote(&a); > + > return 0; > } >=20 > + > REGISTER_TEST_COMMAND(prefetch_autotest, test_prefetch); diff --git > a/doc/guides/rel_notes/release_20_11.rst > b/doc/guides/rel_notes/release_20_11.rst > index df227a1..dc402ab 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -55,6 +55,13 @@ New Features > Also, make sure to start the actual text at the margin. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D >=20 > +* **Added new function rte_cldemote in rte_prefetch.h.** > + > + Added a hardware hint CLDEMOTE, which is similar to prefetch in revers= e. > + CLDEMOTE moves the cache line to the more remote cache, where it > + expects sharing to be efficient. Moving the cache line to a level > + more distant from the processor helps to accelerate core-to-core > communication. > + Patch cannot apply. Maybe rebase is needed. >=20 > Removed Items > ------------- > diff --git a/lib/librte_eal/arm/include/rte_prefetch_32.h > b/lib/librte_eal/arm/include/rte_prefetch_32.h > index e53420a..062ed27 100644 > --- a/lib/librte_eal/arm/include/rte_prefetch_32.h > +++ b/lib/librte_eal/arm/include/rte_prefetch_32.h > @@ -10,6 +10,7 @@ > #endif >=20 > #include > +#include > #include "generic/rte_prefetch.h" >=20 > static inline void rte_prefetch0(const volatile void *p) @@ -33,6 +34,13= @@ > static inline void rte_prefetch_non_temporal(const volatile void *p) > rte_prefetch0(p); > } >=20 > +static inline void > +__rte_experimental See below. > +rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/arm/include/rte_prefetch_64.h > b/lib/librte_eal/arm/include/rte_prefetch_64.h > index fc2b391..6e5ee07 100644 > --- a/lib/librte_eal/arm/include/rte_prefetch_64.h > +++ b/lib/librte_eal/arm/include/rte_prefetch_64.h > @@ -10,6 +10,7 @@ > #endif >=20 > #include > +#include > #include "generic/rte_prefetch.h" >=20 > static inline void rte_prefetch0(const volatile void *p) @@ -32,6 +33,13= @@ > static inline void rte_prefetch_non_temporal(const volatile void *p) > asm volatile ("PRFM PLDL1STRM, [%0]" : : "r" (p)); } >=20 > +static inline void > +__rte_experimental > +rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/include/generic/rte_prefetch.h > b/lib/librte_eal/include/generic/rte_prefetch.h > index 6e47bdf..3474548 100644 > --- a/lib/librte_eal/include/generic/rte_prefetch.h > +++ b/lib/librte_eal/include/generic/rte_prefetch.h > @@ -51,4 +51,20 @@ > */ > static inline void rte_prefetch_non_temporal(const volatile void *p); >=20 > +/** > + * Demote a cache line to a more distant level of cache from the process= or. > + * > + * CLDEMOTE hints to hardware to move (demote) a cache line from the > +closest to > + * the processor to a level more distant from the processor. It is a > +hint and > + * not guarantee. rte_cldemote is intended to move the cache line to > +the more > + * remote cache, where it expects sharing to be efficient and to > +indicate that a > + * line may be accessed by a different core in the future. > + * > + * @param p > + * Address to demote > + */ > +static inline void > +__rte_experimental 1. Experimental tag is only needed in this file. Tags at other places can b= e removed. 2. To align with other codes, experimental tag can be put above 'static inl= ine void' line. > +rte_cldemote(const volatile void *p); > + > #endif /* _RTE_PREFETCH_H_ */ > diff --git a/lib/librte_eal/ppc/include/rte_prefetch.h > b/lib/librte_eal/ppc/include/rte_prefetch.h > index 9ba07c8..9630227 100644 > --- a/lib/librte_eal/ppc/include/rte_prefetch.h > +++ b/lib/librte_eal/ppc/include/rte_prefetch.h > @@ -11,6 +11,7 @@ > #endif >=20 > #include > +#include > #include "generic/rte_prefetch.h" >=20 > static inline void rte_prefetch0(const volatile void *p) @@ -34,6 +35,13= @@ > static inline void rte_prefetch_non_temporal(const volatile void *p) > rte_prefetch0(p); > } >=20 > +static inline void > +__rte_experimental > +rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/x86/include/rte_prefetch.h > b/lib/librte_eal/x86/include/rte_prefetch.h > index 384c6b3..e1e120e 100644 > --- a/lib/librte_eal/x86/include/rte_prefetch.h > +++ b/lib/librte_eal/x86/include/rte_prefetch.h > @@ -10,6 +10,7 @@ > #endif >=20 > #include > +#include > #include "generic/rte_prefetch.h" >=20 > static inline void rte_prefetch0(const volatile void *p) @@ -32,6 +33,17= @@ > static inline void rte_prefetch_non_temporal(const volatile void *p) > asm volatile ("prefetchnta %[p]" : : [p] "m" (*(const volatile char > *)p)); } >=20 > +/* > + * we're using raw byte codes for now as only the newest compiler > + * versions support this instruction natively. > + */ > +static inline void > +__rte_experimental > +rte_cldemote(const volatile void *p) > +{ > + asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (p)); } > + > #ifdef __cplusplus > } > #endif > -- > 1.8.3.1