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Tue, 6 Feb 2018 05:51:29 +0000 From: Herbert Guan To: Pavan Nikhilesh , "jerin.jacob@caviumnetworks.com" , "hemant.agrawal@nxp.com" , "bruce.richardson@intel.com" , "harry.van.haaren@intel.com" CC: "dev@dpdk.org" , Song Zhu Thread-Topic: [PATCH v1] build: add more implementers' IDs and PNs for Arm platforms Thread-Index: AQHTmmaoj9Rj9q1PD0+FdXINfIqpjaOVkPYAgAEiRuA= Date: Tue, 6 Feb 2018 05:51:29 +0000 Message-ID: References: <1517375549-29756-1-git-send-email-herbert.guan@arm.com> <1517384359-1438-1-git-send-email-herbert.guan@arm.com> <20180205092244.yf34vqtvvwu6djfz@Pavan-LT> In-Reply-To: <20180205092244.yf34vqtvvwu6djfz@Pavan-LT> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Herbert.Guan@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; HE1PR08MB0985; 7:giKZwxIBrQAdeIOUjdOgUTvwe426PbMRDpAjZN0XEj+/TPrQpc1gfI+hOiSFPE+fBsnu3VyajOl2m9VpfNNfApDpiqd+2e1zfb6CPCTsTLPIgakPmzb8P9MwuDz1jWtKetCWPwmMXxH7o2BmoTtvj9rno88Lun+RDQFFS1XNwV8UWaQ1svNilABbQbsuyRa6mS1gMYOrJvHPRte9HrJf5dTc2BwYh8ZhHknXhTZAPpLPAKS83bPw1mSgHVHsj0us x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; 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DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR08MB0985; H:HE1PR08MB2809.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: d+IMXViGuWBUv1suJMWlixctOz97mAeDUOijMxghDsP7Wm/2xriIVHLg2udOnHUXvyrT00t8C65aPWRTKHQTwA== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 52d10794-1733-4a47-248f-08d56d25ab41 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Feb 2018 05:51:29.5621 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR08MB0985 Subject: Re: [dpdk-dev] [PATCH v1] build: add more implementers' IDs and PNs for Arm platforms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Feb 2018 05:51:33 -0000 Hi Pavan, > -----Original Message----- > From: Pavan Nikhilesh [mailto:pbhagavatula@caviumnetworks.com] > Sent: Monday, February 5, 2018 17:23 > To: Herbert Guan ; > jerin.jacob@caviumnetworks.com; hemant.agrawal@nxp.com; > bruce.richardson@intel.com; harry.van.haaren@intel.com > Cc: dev@dpdk.org > Subject: Re: [PATCH v1] build: add more implementers' IDs and PNs for Arm > platforms > > Hi Herbert, > > On Wed, Jan 31, 2018 at 03:39:19PM +0800, Herbert Guan wrote: > > 1) Add native PN option '-march=3Dnative' to allow automatic detection. > > Set 'arm_force_native_march' to 'true' in config/arm/meson.build > > to use native PN option. > > 2) Add implementer_pn option for part num selection in cross compile > > 3) Add known Arm cortex PN support > > 4) Add known implementers' IDs (use generic flags/archs by default) > > 5) Sync build options with config/common_armv8a_linuxapp > > > > Signed-off-by: Herbert Guan > > --- > > > + > > machine_args_generic =3D [ > > -['default', ['-march=3Darmv8-a+crc+crypto']]] > > +['default', ['-march=3Darmv8-a']], > > Any specific reason for this change? > Traditional make uses > MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc+crypto > found at mk/machine/armv8a/rte.vars.mk > Both CRC and Crypto are optional instructions / extensions on Arm v8 CPUs. When making a general build (e.g. a release build for distribution), we nee= d to ensure all targeted CPUs (all Armv8 for example) can support this compiled binary. Defaulting crc and crypto to be supported may introduce risks. Fo= r a certain CPU/platform, '-march=3Dnative' may be used, or CPU implementers can furthe= r Customize these args in this file. On the other hand, the rte_cpuflags.c is already supporting run-time CPU fl= ags (instruction sets) detection and this is the preferred approach. > > +['native', ['-march=3Dnative']], > > +['0xd03', ['-mcpu=3Dcortex-a53']], > > +['0xd04', ['-mcpu=3Dcortex-a35']], > > +['0xd07', ['-mcpu=3Dcortex-a57']], > > +['0xd08', ['-mcpu=3Dcortex-a72']], > > +['0xd09', ['-mcpu=3Dcortex-a73']], > > +['0xd0a', ['-mcpu=3Dcortex-a75']], > > +] > > machine_args_cavium =3D [ > > ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > > +['native', ['-march=3Dnative']], > > ['0xa1', ['-mcpu=3Dthunderxt88']], > > ['0xa2', ['-mcpu=3Dthunderxt81']], > > ['0xa3', ['-mcpu=3Dthunderxt83']]] > > > > -flags_generic =3D [[]] > > +flags_common_default =3D [ > > +# Accelarate rte_memcpy. Be sure to run unit test > (memcpy_perf_autotest) > > +# to determine the best threshold in code. Refer to notes in source > file > > +# (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for > more info. > > +['RTE_ARCH_ARM64_MEMCPY', false], > > +#['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048], > > +#['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512], > > +# Leave below RTE_ARM64_MEMCPY_xxx options commented out, > unless there're > > +# strong reasons. > > +#['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false], > > +#['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], > > +#['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], > > + > > +['RTE_LIBRTE_FM10K_PMD', false], > > +['RTE_LIBRTE_SFC_EFX_PMD', false], > > +['RTE_LIBRTE_AVP_PMD', false], > > + > > +['RTE_SCHED_VECTOR', false], > > +] > > + > > +flags_generic =3D [ > > +['RTE_MACHINE', '"armv8a"'], > > +['RTE_CACHE_LINE_SIZE', 128]] > > flags_cavium =3D [ > > ['RTE_MACHINE', '"thunderx"'], > > ['RTE_CACHE_LINE_SIZE', 128], > > @@ -22,8 +55,21 @@ flags_cavium =3D [ > > ['RTE_MAX_VFIO_GROUPS', 128], > > ['RTE_RING_USE_C11_MEM_MODEL', false]] > > > > +## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7- > 5321) > > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic= ] > > +impl_0x41 =3D ['Arm', flags_generic, machine_args_generic] > > +impl_0x42 =3D ['Broadcom', flags_generic, machine_args_generic] > > impl_0x43 =3D ['Cavium', flags_cavium, machine_args_cavium] > > +impl_0x44 =3D ['DEC', flags_generic, machine_args_generic] > > +impl_0x49 =3D ['Infineon', flags_generic, machine_args_generic] > > +impl_0x4d =3D ['Motorola', flags_generic, machine_args_generic] > > +impl_0x4e =3D ['NVIDIA', flags_generic, machine_args_generic] > > +impl_0x50 =3D ['AppliedMicro', flags_generic, machine_args_generic] > > +impl_0x51 =3D ['Qualcomm', flags_generic, machine_args_generic] > > +impl_0x53 =3D ['Samsung', flags_generic, machine_args_generic] > > +impl_0x56 =3D ['Marvell', flags_generic, machine_args_generic] > > +impl_0x69 =3D ['Intel', flags_generic, machine_args_generic] > > + > > > > One minor concern here is DPAA/DPAA2 use cacheline size og 64B unlike > traditional 128B armv8. found at config/defconfig_arm64-dpaa/2-linuxapp- > gcc > maybe Hemanth could comment on this. > > > if cc.get_define('__clang__') !=3D '' > > dpdk_conf.set_quoted('RTE_TOOLCHAIN', 'clang') > > @@ -55,19 +101,31 @@ else > > meson.current_source_dir(), > 'armv8_machine.py')) > > cmd =3D run_command(detect_vendor.path()) > > if cmd.returncode() =3D=3D 0 > > -cmd_output =3D cmd.stdout().strip().split(' ') > > +cmd_output =3D cmd.stdout().to_lower().strip().split(' ') > > endif > > > > Verified on thunderx with gcc 5.3.0/7.2.1 and clang 5.0.1 > > Regards, > Pavan > > > @@ -79,22 +137,19 @@ else > > # for gcc versions > 7 > > if cc.version().version_compare( > > '<7.0') or cmd_output.length() =3D=3D 0 > > -foreach marg: machine[2] > > -if marg[0] =3D=3D 'default' > > -foreach f: marg[1] > > -machine_args +=3D f > > -endforeach > > -endif > > -endforeach > > -else > > -foreach marg: machine[2] > > -if marg[0] =3D=3D cmd_output[3] > > -foreach f: marg[1] > > -machine_args +=3D f > > -endforeach > > -endif > > -endforeach > > +if not meson.is_cross_build() and arm_force_native_march > =3D=3D true > > +impl_pn =3D 'native' > > +else > > +impl_pn =3D 'default' > > +endif > > endif > > +foreach marg: machine[2] > > +if marg[0] =3D=3D impl_pn > > +foreach f: marg[1] > > +machine_args +=3D f > > +endforeach > > +endif > > +endforeach > > endif > > message(machine_args) > > > > -- > > 1.8.3.1 > > IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. 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