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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA0PR11MB7955.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcec845c-01b6-4f38-3bb0-08db1f9a6417 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2023 06:00:16.7569 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: C6/bNNwejxSAmz+zlEw4Y5+oKLpru3XmTjFcZEeHjFjNS8Vnwah7U6HuaRzNkdNBJymK+B8PFjXkI2+lBM6TlQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7790 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Su, Simei > Sent: Wednesday, March 8, 2023 12:37 PM > To: Zhang, Qi Z ; Yang, Qiming > > Cc: dev@dpdk.org; Wu, Wenjun1 ; Su, Simei > ; stable@dpdk.org > Subject: [PATCH v2] net/ice: fix incorrect Rx timestamp >=20 > For E822, the time value in Rx Flex Descriptors is 0 due to the missing P= HY > clock timer setup. Also, the source clock index in use is based on device > capabilities instead of always being zero. >=20 > Fixes: 953e74e6b73a ("net/ice: enable Rx timestamp on flex descriptor") > Fixes: 646dcbe6c701 ("net/ice: support IEEE 1588 PTP") > Fixes: fb800fde66f4 ("net/ice/base: work around missing PTP capabilities"= ) > Cc: stable@dpdk.org >=20 > Signed-off-by: Simei Su > --- > v2: > * Refine commit title and commit log. > * Remove duplicate code. > * Rework share code for "SIMICS_SUPPORT". >=20 > drivers/net/ice/base/ice_common.c | 4 +--- > drivers/net/ice/ice_ethdev.c | 36 ++++++++++++++++++++++-----------= --- > drivers/net/ice/ice_rxtx.h | 11 ++++++----- > 3 files changed, 29 insertions(+), 22 deletions(-) >=20 > diff --git a/drivers/net/ice/base/ice_common.c > b/drivers/net/ice/base/ice_common.c > index 5391bd6..1a02aad 100644 > --- a/drivers/net/ice/base/ice_common.c > +++ b/drivers/net/ice/base/ice_common.c > @@ -2554,9 +2554,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, > struct ice_hw_func_caps *func_p, > struct ice_aqc_list_caps_elem *cap) { > struct ice_ts_func_info *info =3D &func_p->ts_func_info; > - u32 number =3D ICE_TS_FUNC_ENA_M | ICE_TS_SRC_TMR_OWND_M | > - ICE_TS_TMR_ENA_M | ICE_TS_TMR_IDX_OWND_M | > - ICE_TS_TMR_IDX_ASSOC_M; > + u32 number =3D LE32_TO_CPU(cap->number); > u8 clk_freq; >=20 > ice_debug(hw, ICE_DBG_INIT, "1588 func caps: raw value %x\n", > number); diff --git a/drivers/net/ice/ice_ethdev.c > b/drivers/net/ice/ice_ethdev.c index 0d011bb..9a88cf9 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -2413,6 +2413,17 @@ ice_dev_init(struct rte_eth_dev *dev) > /* Initialize TM configuration */ > ice_tm_conf_init(dev); >=20 > + if (ice_is_e810(hw)) > + hw->phy_cfg =3D ICE_PHY_E810; > + else > + hw->phy_cfg =3D ICE_PHY_E822; > + > + if (hw->phy_cfg =3D=3D ICE_PHY_E822) { > + ret =3D ice_start_phy_timer_e822(hw, hw->pf_id, true); > + if (ret) > + PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); > + } > + > if (!ad->is_safe_mode) { > ret =3D ice_flow_init(ad); > if (ret) { > @@ -5814,11 +5825,6 @@ ice_timesync_enable(struct rte_eth_dev *dev) > return -1; > } >=20 > - if (ice_is_e810(hw)) > - hw->phy_cfg =3D ICE_PHY_E810; > - else > - hw->phy_cfg =3D ICE_PHY_E822; > - > if (hw->func_caps.ts_func_info.src_tmr_owned) { > ret =3D ice_ptp_init_phc(hw); > if (ret) { > @@ -5939,16 +5945,17 @@ ice_timesync_read_time(struct rte_eth_dev > *dev, struct timespec *ts) > struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > struct ice_adapter *ad =3D > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data- > >dev_private); > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > uint32_t hi, lo, lo2; > uint64_t time, ns; >=20 > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > - lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > + lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); >=20 > if (lo2 < lo) { > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > } >=20 > time =3D ((uint64_t)hi << 32) | lo; > @@ -5964,6 +5971,7 @@ ice_timesync_disable(struct rte_eth_dev *dev) > struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > struct ice_adapter *ad =3D > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data- > >dev_private); > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > uint64_t val; > uint8_t lport; >=20 > @@ -5971,12 +5979,12 @@ ice_timesync_disable(struct rte_eth_dev *dev) >=20 > ice_clear_phy_tstamp(hw, lport, 0); >=20 > - val =3D ICE_READ_REG(hw, GLTSYN_ENA(0)); > + val =3D ICE_READ_REG(hw, GLTSYN_ENA(tmr_idx)); > val &=3D ~GLTSYN_ENA_TSYN_ENA_M; > - ICE_WRITE_REG(hw, GLTSYN_ENA(0), val); > + ICE_WRITE_REG(hw, GLTSYN_ENA(tmr_idx), val); >=20 > - ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0); > - ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0); > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(tmr_idx), 0); > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(tmr_idx), 0); >=20 > ad->ptp_ena =3D 0; >=20 > diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h inde= x > 4947d5c..94f6bcf 100644 > --- a/drivers/net/ice/ice_rxtx.h > +++ b/drivers/net/ice/ice_rxtx.h > @@ -349,26 +349,27 @@ static inline > uint64_t ice_tstamp_convert_32b_64b(struct ice_hw *hw, struct ice_adapte= r > *ad, > uint32_t flag, uint32_t in_timestamp) { > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > const uint64_t mask =3D 0xFFFFFFFF; > uint32_t hi, lo, lo2, delta; > uint64_t ns; >=20 > if (flag) { > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); >=20 > /* > * On typical system, the delta between lo and lo2 is ~1000ns, > * so 10000 seems a large-enough but not overly-big guard > band. > */ > if (lo > (UINT32_MAX - > ICE_TIMESYNC_REG_WRAP_GUARD_BAND)) > - lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > + lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > else > lo2 =3D lo; >=20 > if (lo2 < lo) { > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > } >=20 > ad->time_hw =3D ((uint64_t)hi << 32) | lo; > -- > 2.9.5 Acked-by: Wenjun Wu Regards, Wenjun