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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA1PR12MB8078.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03eabcc0-609c-4d33-e1e1-08dc2c9579d2 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Feb 2024 13:12:48.4932 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: J6UkP6wlOtTvmJUBUl6lFzMldrh0+XbVzNUckNfGbK4tmfGmXlLjRSpAz8aQPz+1Rl28vH1kz6zjUAuJOSR7xQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7213 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi, Regarding "dev_out_of_buffer" - it is global counter, relates to the whole = device port, Including queues not managed by DPDK application - Mellanox/Nvidia NICs ope= rate In "bifurcated mode" - there might be queues managed by kernel or another D= PDK application. Not sure it makes a lot of sense, but I have no strong objecti= ons. The PCI related counters are also global ones and reflect statistics, impac= ted by PCI activity of the whole physical device, including all the network ports = located on the same NIC board (and, sometimes, by internal activity in BlueField). As I said, no objections from my side: Acked-by: Viacheslav Ovsiienko With best regards, Slava > -----Original Message----- > From: Wathsala Vithanage > Sent: Friday, February 9, 2024 10:42 PM > To: NBU-Contact-Thomas Monjalon (EXTERNAL) ; > Dariusz Sosnowski ; Slava Ovsiienko > ; Ori Kam ; Suanming Mou > ; Matan Azrad > Cc: dev@dpdk.org; nd@arm.com; Wathsala Vithanage > ; Honnappa Nagarahalli > > Subject: [PATCH] net/mlx5: enable PCI related counters >=20 > Versions of Mellanox NICs starting from CX5 have device counters related = to PCI. > These counters are helpful in debugging IO bottlenecks. For instance, the > outbound_pci_stalled_rd and outbound_pci_stalled_wr counters can help wit= h > identifying NIC stalls due to insufficient PCI credits, which otherwise w= ould have > required a PCI analyzer or a sophisticated PCI root port with a PMU. > Currently none of these are available in the MLX5 PMD even though ethtool= is > capable of reading some of them. > Since PMD uses the same ioctl used by ethtool (SIOCETHTOOL) and reads via= the > kernel driver it is possible to add support with ease. > There is one more PCI related counter and a device counter that aren't > implemented in the Linux driver at the moment. These two are named > outbound_pci_buffer_overflow and dev_out_of_buffer respectively. As per > Nvidia's documentation these two counters can tell the number of packets > dropped due to pci buffer overflow and the number of times the device own= ed > queue had not enough buffers allocated. >=20 > Signed-off-by: Wathsala Vithanage > Reviewed-by: Honnappa Nagarahalli > --- > .mailmap | 1 + > drivers/net/mlx5/linux/mlx5_ethdev_os.c | 33 > +++++++++++++++++++++++++ > 2 files changed, 34 insertions(+) >=20 > diff --git a/.mailmap b/.mailmap > index aa569ff456..f57415f7a1 100644 > --- a/.mailmap > +++ b/.mailmap > @@ -1510,6 +1510,7 @@ Walter Heymans > Wang Sheng-Hui Wangyu (Eric) > Waterman Cao > +Wathsala Vithanage > Weichun Chen > Wei Dai > Weifeng Li > diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c > b/drivers/net/mlx5/linux/mlx5_ethdev_os.c > index dd5a0c546d..8f1567f6a7 100644 > --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c > +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c > @@ -1574,6 +1574,39 @@ static const struct mlx5_counter_ctrl > mlx5_counters_init[] =3D { > .dpdk_name =3D "tx_vport_bytes", > .ctr_name =3D "vport_tx_bytes", > }, > + /* Device counters */ > + { > + .dpdk_name =3D "rx_pci_signal_integrity", > + .ctr_name =3D "rx_pci_signal_integrity", > + }, > + { > + .dpdk_name =3D "tx_pci_signal_integrity", > + .ctr_name =3D "tx_pci_signal_integrity", > + }, > + { > + .dpdk_name =3D "outbound_pci_buffer_overflow", > + .ctr_name =3D "outbound_pci_buffer_overflow", > + }, > + { > + .dpdk_name =3D "outbound_pci_stalled_rd", > + .ctr_name =3D "outbound_pci_stalled_rd", > + }, > + { > + .dpdk_name =3D "outbound_pci_stalled_wr", > + .ctr_name =3D "outbound_pci_stalled_wr", > + }, > + { > + .dpdk_name =3D "outbound_pci_stalled_rd_events", > + .ctr_name =3D "outbound_pci_stalled_rd_events", > + }, > + { > + .dpdk_name =3D "outbound_pci_stalled_wr_events", > + .ctr_name =3D "outbound_pci_stalled_wr_events", > + }, > + { > + .dpdk_name =3D "dev_out_of_buffer", > + .ctr_name =3D "dev_out_of_buffer", > + }, > }; >=20 > static const unsigned int xstats_n =3D RTE_DIM(mlx5_counters_init); > -- > 2.25.1