From: "Song, Yoong Siang" <yoong.siang.song@intel.com>
To: "Hore, Soumyadeep" <soumyadeep.hore@intel.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>,
"Zage, David" <david.zage@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: "stable@dpdk.org" <stable@dpdk.org>
Subject: RE: [PATCH v1 1/1] net/e1000: use device timestamp for igc read_clock() operation
Date: Sat, 8 Nov 2025 07:08:44 +0000 [thread overview]
Message-ID: <IA3PR11MB92542B87553924CDE5562FE0D8C0A@IA3PR11MB9254.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CY8PR11MB7747E4515099613475FE50CCF9C3A@CY8PR11MB7747.namprd11.prod.outlook.com>
On Saturday, November 8, 2025 1:11 AM, Hore, Soumyadeep <soumyadeep.hore@intel.com> wrote:
>Hi Song, on closer inspection I see the code implementation is similar to
>eth_igc_timesync_read_time().
>
>Please reuse the existing code as much as possible.
>
Hi Soumyadeep,
Thank for your comment. I will reuse the existing code and resubmit v2.
Thanks & Regards
Siang
>Change eth_igc_read_clock() to read from hardware timestamp registers
>(E1000_SYSTIML/E1000_SYSTIMH) instead of using system clock_gettime().
>
>This ensures that the clock reading is consistent with the hardware's internal time
>base used for Qbv cycle and launch time scheduling, providing better accuracy for
>Time-Sensitive Networking applications.
>
>Fixes: 9630f7c71ecd ("net/igc: enable launch time offloading")
>Cc: stable@dpdk.org
>
>Signed-off-by: David Zage <david.zage@intel.com>
>Signed-off-by: Song Yoong Siang <yoong.siang.song@intel.com>
>---
> drivers/net/intel/e1000/igc_ethdev.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/net/intel/e1000/igc_ethdev.c
>b/drivers/net/intel/e1000/igc_ethdev.c
>index b9c91d2446..045f7c784d 100644
>--- a/drivers/net/intel/e1000/igc_ethdev.c
>+++ b/drivers/net/intel/e1000/igc_ethdev.c
>@@ -2972,10 +2972,18 @@ eth_igc_timesync_disable(struct rte_eth_dev *dev)
>static int eth_igc_read_clock(__rte_unused struct rte_eth_dev *dev, uint64_t
>*clock) {
>- struct timespec system_time;
>+ struct e1000_hw *hw = IGC_DEV_PRIVATE_HW(dev);
>+ uint32_t nsec, sec;
>
>- clock_gettime(CLOCK_REALTIME, &system_time);
>- *clock = system_time.tv_sec * NSEC_PER_SEC + system_time.tv_nsec;
>+ /*
>+ * Reading the SYSTIML register latches the upper 32 bits to the SYSTIMH
>+ * shadow register for coherent access. As long as we read SYSTIML first
>+ * followed by SYSTIMH, we avoid race conditions where the time rolls
>+ * over between the two register reads.
>+ */
>+ nsec = E1000_READ_REG(hw, E1000_SYSTIML);
>+ sec = E1000_READ_REG(hw, E1000_SYSTIMH);
>+ *clock = (uint64_t)sec * NSEC_PER_SEC + (uint64_t)nsec;
>
> return 0;
> }
>--
>2.48.1
prev parent reply other threads:[~2025-11-08 7:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-07 3:15 Song Yoong Siang
2025-11-07 17:10 ` Hore, Soumyadeep
2025-11-08 7:08 ` Song, Yoong Siang [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=IA3PR11MB92542B87553924CDE5562FE0D8C0A@IA3PR11MB9254.namprd11.prod.outlook.com \
--to=yoong.siang.song@intel.com \
--cc=bruce.richardson@intel.com \
--cc=david.zage@intel.com \
--cc=dev@dpdk.org \
--cc=soumyadeep.hore@intel.com \
--cc=stable@dpdk.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).