From: Raslan Darawsheh <rasland@nvidia.com>
To: Gregory Etelson <getelson@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: Maayan Kashani <mkashani@nvidia.com>,
Dariusz Sosnowski <dsosnowski@nvidia.com>,
Slava Ovsiienko <viacheslavo@nvidia.com>,
Ori Kam <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Subject: RE: [PATCH] net/mlx5: fix pattern template size validation
Date: Wed, 13 Mar 2024 07:44:48 +0000 [thread overview]
Message-ID: <MN0PR12MB605651EB041C07276E442B93CF2A2@MN0PR12MB6056.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20240306073856.950136-1-getelson@nvidia.com>
Hi,
> -----Original Message-----
> From: Gregory Etelson <getelson@nvidia.com>
> Sent: Wednesday, March 6, 2024 9:39 AM
> To: dev@dpdk.org
> Cc: Gregory Etelson <getelson@nvidia.com>; Maayan Kashani
> <mkashani@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Dariusz
> Sosnowski <dsosnowski@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>; Suanming Mou
> <suanmingm@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Subject: [PATCH] net/mlx5: fix pattern template size validation
>
> PMD running in HWS FDB mode can be configured to steer group 0 to FW.
> In that case PMD activates legacy DV pattern processing.
> There are control flows that require HWS pattern processing in group 0.
>
> Pattern template validation tried to create a matcher both in group 0 and HWS
> group.
> As the result, during group 0 validation HWS tuned pattern was processed as
> DV.
>
> The patch removed pattern validation for group 0.
>
> Fixes: f3aadd103358 ("net/mlx5: improve pattern template validation")
> Signed-off-by: Gregory Etelson <getelson@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
prev parent reply other threads:[~2024-03-13 7:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 7:38 Gregory Etelson
2024-03-13 7:44 ` Raslan Darawsheh [this message]
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