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Wed, 30 Sep 2020 15:03:47 +0000 From: "Coyle, David" To: "Power, Ciara" , "dev@dpdk.org" CC: "Power, Ciara" , "Singh, Jasvinder" , Olivier Matz , "O'loingsigh, Mairtin" , "Ryan, Brendan" , "Richardson, Bruce" Thread-Topic: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth Thread-Index: AQHWlyuo2OB8abLGA0mSdjPBwdyNaqmBPw6g Date: Wed, 30 Sep 2020 15:03:47 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-18-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-18-ciara.power@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.78.247.248] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 62e5a35f-f097-425c-7557-08d86552088a x-ms-traffictypediagnostic: MN2PR11MB3757: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: uFFpjclGk2iQP/KSptJOLSSN7TrIB+E6xij/D8pC3eWKYqwLTbJcVTtA1Z3plhdXb50GktCkx987g+tbk0+9Uga1k0ZgR9LiDg94rflDF+iqEqvPJZs8eUNzJKhGnr9uK75eZ9wLI8x5R1orKWGC8C9tXSbfTbl01QnJoQOAjV8K2h9HAwSWIw0eKc3CtgH0HzQG8/J9eUqSYoSlYT/wlI31aMx76RGzYyvlvklQSzIt2eN4x0tMQsVJ37EYa8y4PtKiukTgV6i/JgcPcNujoN+BvyyuGjtssNDTLNkLEF2Heg6fOMrDaM56nhFYpLy+u+cQpWqWW2p9QAQpKhLFIpuLxk/rF3p2gQO7mLZBwpYcsCLLYJL2nu6gDGQAko0EcrKMueDP0szgpHgHFQEKiM7JsRNkFVJ1YGmc2F2EyjOx/u+7DJ9HlHm6T/1Lwa66mObLGlaniJHygxotAYwB5F59jmZtZRq1dk3um6EksWLESZerH2bZa8poWXkZkph2QB1wtCpsobIN714c2Kz9EYWo4VPceZsZW/I7Ibpr8JdGY0UrtpdDxmmUPjJcHuJx6f5PtEVSJhq2EjbRHn+ObD/6QLV5E0/1cFDrLXU4Cc3DbdftycTqPkoLwu9KTKZw0N52cuJM8dBuXYVPFtJkGQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3550.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 62e5a35f-f097-425c-7557-08d86552088a X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2020 15:03:47.6561 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YhZc8lh9CeL/C84dtPN7G6kNR2FXNeyvSPg05qjthiWwEs+yLy4MbarlSUQeS4oQXvJovEqJRxbbZKdm1e/jDg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3757 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Ciara, > From: dev On Behalf Of Ciara Power > When choosing a vector path to take, an extra condition must be satisfied= to > ensure the max SIMD bitwidth allows for the CPU enabled path. >=20 > The vector path was initially chosen in RTE_INIT, however this is no long= er > suitable as we cannot check the max SIMD bitwidth at that time. > The default chosen in RTE_INIT is now scalar. For best performance and to > use vector paths, apps must explicitly call the set algorithm function be= fore > using other functions from this library, as this is where vector handlers= are > now chosen. [DC] Has it been decided that it is ok to now require applications to pick = the CRC algorithm they want to use? An application which previously automatically got SSE4.2 CRC, for example, = will now automatically only get scalar. If this is ok, this should probably be called out explicitly in release not= es as it may not be Immediately noticeable to users that they now need to select the CRC= algo. Actually, in general, the release notes need to be updated for this patchse= t. >=20 > Suggested-by: Jasvinder Singh >=20 > Signed-off-by: Ciara Power >=20 > --- > v3: > - Moved choosing vector paths out of RTE_INIT. > - Moved checking max_simd_bitwidth into the set_alg function. > --- > lib/librte_net/rte_net_crc.c | 26 +++++++++++++++++--------- > lib/librte_net/rte_net_crc.h | 3 ++- > 2 files changed, 19 insertions(+), 10 deletions(-) >=20 > diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c = index > 9fd4794a9d..241eb16399 100644 > --- a/lib/librte_net/rte_net_crc.c > +++ b/lib/librte_net/rte_net_crc.c > @@ -145,18 +149,26 @@ rte_crc32_eth_handler(const uint8_t *data, > uint32_t data_len) void rte_net_crc_set_alg(enum rte_net_crc_alg alg) = { > + if (max_simd_bitwidth =3D=3D 0) > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > + > switch (alg) { > #ifdef X86_64_SSE42_PCLMULQDQ > case RTE_NET_CRC_SSE42: > - handlers =3D handlers_sse42; > - break; > + if (max_simd_bitwidth >=3D RTE_MAX_128_SIMD) { > + handlers =3D handlers_sse42; > + return; > + } > + RTE_LOG(INFO, NET, "Max SIMD Bitwidth too low, using > scalar\n"); [DC] Not sure if you're aware but there is another patchset which adds an A= VX512 CRC implementation and run-time checking of cpuflags to select the CRC path to = use: https://patchwork.dpdk.org/project/dpdk/list/?series=3D12596 There will be a task to merge these 2 patchsets if both are merged. It look= s fairly straightforward to me to merge these, but it would be good if you take a lo= ok too