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Thu, 1 Oct 2020 14:16:31 +0000 From: "Coyle, David" To: "Singh, Jasvinder" , "Power, Ciara" , "dev@dpdk.org" CC: "Power, Ciara" , Olivier Matz , "O'loingsigh, Mairtin" , "Ryan, Brendan" , "Richardson, Bruce" Thread-Topic: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth Thread-Index: AQHWlyuo2OB8abLGA0mSdjPBwdyNaqmBPw6ggAAVOICAAXKx0A== Date: Thu, 1 Oct 2020 14:16:31 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-18-ciara.power@intel.com> In-Reply-To: Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [51.37.79.167] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: abf819cb-b3bf-4a38-d1df-08d866149874 x-ms-traffictypediagnostic: MN2PR11MB3936: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: S55FKgrXYBqHN6N1FOmzhMe0m7E6E3w3ACXhO4OohVGASFrL50VIjYEbtlXFDWy8e0xTEhetLJrO7YJc0bK8beXRvgCS3g0hIN8Mn/Jm1U7ilc0oUnMC/XF4cDn9xQrFKGApQL0gIbXocW4OJzNec6guWQKqk4EbFfvncTI4UZ9D2c+a1bv5sDKvoHTYy0utk/0VzzclA2SbHkyz6PSc2Rl5twrGqX5rpFjTrf7qxFOQ0DGfyE97QHZH5tIMhADTd6FZGSHXT2x4lMSdkvddoyRy7PDCWH/f143b6Ridcv3QgQkuLolipGWzh8OgRqLc3VsWQUczuwd4L0ZBOn+Ap5XnL23nk2NuRi6pYNFXNs02D4K//FzuklWFiP1A7FRvmqHWqP8h0cB+NRN5/7MPKkcysJ92MH8B5Vufse5MKECutxm6CQTLQEL+JLLm5hW91lByZK9eX6V53l/d/4KcjAcuDrY8kS90I0L9jSpxDNWPOfBZYTv8czJpXrL9MtNonSFYik5LgFtp+LiTVqx0KoQHDhbeMrjYXo38hazQ4xJqnSHvp/Wn6J5HHmQMWbjQ3oPR4LMgMFFpMmyxjngz46ljA2vEhquN2VRcCaR2d0Tsm4vq2uoLh9hUTeGFFlfKhG/nharBgeNn9acHB3IZTA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3550.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: abf819cb-b3bf-4a38-d1df-08d866149874 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Oct 2020 14:16:31.4607 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4EQpY3JqagLLmIlIlfTOq7O6GSzE7QnMqE0nJntVE+rRTer+uSpeNi977rg7h6LnH1EM4/s7s07G7Tw/Wi0Ncw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3936 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jasvinder/Ciara > -----Original Message----- > From: Singh, Jasvinder > > > > > From: dev On Behalf Of Ciara Power When > > > choosing a vector path to take, an extra condition must be satisfied > > > to ensure the max SIMD bitwidth allows for the CPU enabled path. > > > > > > The vector path was initially chosen in RTE_INIT, however this is no > > > longer suitable as we cannot check the max SIMD bitwidth at that time= . > > > The default chosen in RTE_INIT is now scalar. For best performance > > > and to use vector paths, apps must explicitly call the set algorithm > > > function before using other functions from this library, as this is > > > where vector handlers are now chosen. > > > > [DC] Has it been decided that it is ok to now require applications to > > pick the CRC algorithm they want to use? > > > > An application which previously automatically got SSE4.2 CRC, for > > example, will now automatically only get scalar. > > > > If this is ok, this should probably be called out explicitly in > > release notes as it may not be Immediately noticeable to users that > > they now need to select the CRC algo. > > > > Actually, in general, the release notes need to be updated for this > patchset. >=20 > The decision to move rte_set_alg() out of RTE_INIT was taken to avoid che= ck > on max_simd_bitwidth in data path for every single time when crc_calc() a= pi > is invoked. Based on my understanding, max_simd_bitwidth is set after eal > init, and when used in crc_calc(), it might override the default crc algo= set > during RTE_INIT. Therefore, to avoid extra check on max_simd_bitwidth in > data path, better option will be to use this static configuration one ti= me after > eal init in the set_algo API. [DC] Yes that is a good change to have made to avoid extra datapath checks. Based on off-list discussion, I now also know the reason behind now default= ing to scalar CRC in RTE_INIT. If a higher bitwidth CRC was chosen by RTE_INIT = (e.g. SSE4.2 CRC) but the max_simd_bitwidth was then set to RTE_NO_SIMD (64) thro= ugh the EAL parameter or call to rte_set_max_simd_bitwidth(), then there is a m= ismatch if rte_net_crc_set_alg() is not then called to reconfigure the CRC. Default= ing to scalar avoids this mismatch and works on all archs As I mentioned before, I think this needs to be called out in release notes= , as it's an under-the-hood change which could cause app performance to drop if app deve= lopers aren't aware of it - the API itself hasn't changed, so they may not read th= e doxygen :) >=20 >=20 > > > > > > Suggested-by: Jasvinder Singh > > > > > > Signed-off-by: Ciara Power > > > > > > --- > > > v3: > > > - Moved choosing vector paths out of RTE_INIT. > > > - Moved checking max_simd_bitwidth into the set_alg function. > > > --- > > > lib/librte_net/rte_net_crc.c | 26 +++++++++++++++++--------- > > > lib/librte_net/rte_net_crc.h | 3 ++- > > > 2 files changed, 19 insertions(+), 10 deletions(-) > > > > > > diff --git a/lib/librte_net/rte_net_crc.c > > > b/lib/librte_net/rte_net_crc.c index > > > 9fd4794a9d..241eb16399 100644 > > > --- a/lib/librte_net/rte_net_crc.c > > > +++ b/lib/librte_net/rte_net_crc.c > > > > > > > > > @@ -145,18 +149,26 @@ rte_crc32_eth_handler(const uint8_t *data, > > > uint32_t data_len) void rte_net_crc_set_alg(enum rte_net_crc_alg > > > alg) { > > > + if (max_simd_bitwidth =3D=3D 0) > > > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > > > + > > > switch (alg) { > > > #ifdef X86_64_SSE42_PCLMULQDQ > > > case RTE_NET_CRC_SSE42: > > > - handlers =3D handlers_sse42; > > > - break; > > > + if (max_simd_bitwidth >=3D RTE_MAX_128_SIMD) { > > > + handlers =3D handlers_sse42; > > > + return; > > > + } > > > + RTE_LOG(INFO, NET, "Max SIMD Bitwidth too low, using > > > scalar\n"); > > > > [DC] Not sure if you're aware but there is another patchset which adds > > an > > AVX512 CRC implementation and run-time checking of cpuflags to select > > the CRC path to use: > > https://patchwork.dpdk.org/project/dpdk/list/?series=3D12596 > > > > There will be a task to merge these 2 patchsets if both are merged. It > > looks fairly straightforward to me to merge these, but it would be > > good if you take a look too