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charset="us-ascii" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: fec85572-f1b1-493e-a34d-08d7dba6b52b X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Apr 2020 10:22:14.4485 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PiHtEU8sdut/l+sdo18i8I+04HmkZ1A8/blMWh5rwv/FaVF/vorZ/vBUi+9+yuPP+bzMRDXI6QIfEvElVW5LtMz+7kciZCKG1g9gMJ0BHqA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4094 X-OriginatorOrg: intel.com Content-Transfer-Encoding: quoted-printable X-Mailman-Approved-At: Fri, 10 Apr 2020 14:45:50 +0200 Subject: Re: [dpdk-dev] [PATCH v2 3/4] net/i40e/base: add constants for PTP pins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ACK -----Original Message----- From: Min, JiaqiX = Sent: Wednesday, April 8, 2020 12:05 PM To: dev@dpdk.org Cc: Min, JiaqiX ; Kwapulinski, Piotr Subject: [PATCH v2 3/4] net/i40e/base: add constants for PTP pins Introduce constants for handling PTP pins used for external clock source. Signed-off-by: Piotr Kwapulinski Signed-off-by: Jiaqi Min Acked-by: Piotr Kwapulinski --- drivers/net/i40e/base/i40e_register.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/= i40e_register.h index 436f48efa..dffcc633c 100644 --- a/drivers/net/i40e/base/i40e_register.h +++ b/drivers/net/i40e/base/i40e_register.h @@ -2910,6 +2910,10 @@ #define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0= _PULSEW_SHIFT) #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 #define I40E_PRTTSYN_AUX_0_EV= NTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) +#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17 #define = +I40E_PRTTSYN_AUX_0_PTPFLAG_MASK \ + I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT) #define = +I40E_PRTTSYN_AUX_0_PTP_OUT_SYNC_CLK_IO 0xF #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /*= _i=3D0...1 */ /* Reset: GLOBR */ #define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 -- 2.17.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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