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mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from MN2PR12MB4286.namprd12.prod.outlook.com (2603:10b6:208:199::22) by BL0PR12MB4610.namprd12.prod.outlook.com (2603:10b6:208:84::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.22; Thu, 8 Oct 2020 09:47:26 +0000 Received: from MN2PR12MB4286.namprd12.prod.outlook.com ([fe80::61fd:a36e:cf4f:2d3f]) by MN2PR12MB4286.namprd12.prod.outlook.com ([fe80::61fd:a36e:cf4f:2d3f%9]) with mapi id 15.20.3455.023; Thu, 8 Oct 2020 09:47:26 +0000 From: Ori Kam <orika@nvidia.com> To: Bing Zhao <bingz@nvidia.com>, NBU-Contact-Thomas Monjalon <thomas@monjalon.net>, "ferruh.yigit@intel.com" <ferruh.yigit@intel.com>, "arybchenko@solarflare.com" <arybchenko@solarflare.com>, "mdr@ashroe.eu" <mdr@ashroe.eu>, "nhorman@tuxdriver.com" <nhorman@tuxdriver.com>, "bernard.iremonger@intel.com" <bernard.iremonger@intel.com>, "beilei.xing@intel.com" <beilei.xing@intel.com>, "wenzhuo.lu@intel.com" <wenzhuo.lu@intel.com> CC: "dev@dpdk.org" <dev@dpdk.org> Thread-Topic: [PATCH v2 6/6] doc: update for two ports hairpin mode Thread-Index: AQHWnVBnJL5jCFpT1UCx1SdQN1mUtamNdVJw Date: Thu, 8 Oct 2020 09:47:26 +0000 Message-ID: <MN2PR12MB42866138FC9669850AC9DC51D60B0@MN2PR12MB4286.namprd12.prod.outlook.com> References: <1601511962-21532-1-git-send-email-bingz@nvidia.com> <1602147098-9768-1-git-send-email-bingz@nvidia.com> <1602147098-9768-7-git-send-email-bingz@nvidia.com> In-Reply-To: <1602147098-9768-7-git-send-email-bingz@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fef7ac70-45d7-4c54-37d4-08d86b6f2a05 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2020 09:47:26.1660 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ZouKK8QDoAEMwrqWxUqcm2YcDRWYYdyn/OXfVJyo2hAnkVW9spBxPHIUghG94gu1trUBWGxyG/EHNxIKMEqGnw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4610 X-OriginatorOrg: Nvidia.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1602150436; bh=v1hteXeKQZnrEPlEtnYaihQKUm60RFyEVWpwCtOGF7s=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To: CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References: In-Reply-To:Accept-Language:Content-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-ms-traffictypediagnostic:x-ld-processed: x-ms-exchange-transport-forked:x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers:x-ms-exchange-senderadcheck: x-microsoft-antispam:x-microsoft-antispam-message-info: x-forefront-antispam-report:x-ms-exchange-antispam-messagedata: Content-Type:Content-Transfer-Encoding:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg; b=gtl3nWQHqEduJv3AKUJM6tHonIvuw3Oafm2bqgXKkd4Zn3dfMvwoLWcVxIZLQBXam cd28/yJb9kPHlcFLXU3v09ZyOmrilcISxepEE4z/bsn+1+tZDcMwkrfWQ+ttNVLRCI ICRCiO17XNWhlMwBn5XzgT2QZWaDyYzEHL/9jtieC1pNBa+Iye7R3O35xxkDqlnIzf gfgYwx6whTqInUELIWwW8rN2UQDq4CDX8yMIVAl+aCSxRIHB0qUi3obqONFm/K7TkA 4eYx/DMztYRjhtu0tIHRxTqO74Q2yAVYgZVXDix/I08rAGwoyMEqetOsb6YqSt26X8 mqrzja4mh1Dng== Subject: Re: [dpdk-dev] [PATCH v2 6/6] doc: update for two ports hairpin mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Hi Bing, > -----Original Message----- > From: Bing Zhao <bingz@nvidia.com> > Sent: Thursday, October 8, 2020 11:52 AM > Subject: [PATCH v2 6/6] doc: update for two ports hairpin mode >=20 > In the release notes, 2 ports hairpin mode feature is added. >=20 > In rte flow part, one suggestion is added to mention that metadata > could be used to connect the hairpin RX and TX flows if the hairpin > is working in explicit TX flow rule mode. >=20 > In the testpmd command line, the new parameter to set hairpin working > mode is described. >=20 > Signed-off-by: Bing Zhao <bingz@nvidia.com> > --- > doc/guides/prog_guide/rte_flow.rst | 3 +++ > doc/guides/rel_notes/release_20_11.rst | 8 ++++++++ > doc/guides/testpmd_app_ug/run_app.rst | 8 ++++++++ > 3 files changed, 19 insertions(+) >=20 > diff --git a/doc/guides/prog_guide/rte_flow.rst > b/doc/guides/prog_guide/rte_flow.rst > index 119b128..bb54d67 100644 > --- a/doc/guides/prog_guide/rte_flow.rst > +++ b/doc/guides/prog_guide/rte_flow.rst > @@ -2592,6 +2592,9 @@ set, unpredictable value will be seen depending on > driver implementation. For > loopback/hairpin packet, metadata set on Rx/Tx may or may not be > propagated to > the other path depending on HW capability. >=20 > +In hairpin case with TX explicit flow mode, metadata could (not mandator= y) be > +used to connect the RX and TX flows if it can be propagated from RX to T= X > path. > + > .. _table_rte_flow_action_set_meta: >=20 > .. table:: SET_META > diff --git a/doc/guides/rel_notes/release_20_11.rst > b/doc/guides/rel_notes/release_20_11.rst > index 0b2a370..05ceea0 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -109,6 +109,10 @@ New Features > * Extern objects and functions can be plugged into the pipeline. > * Transaction-oriented table updates. >=20 > +* **Updated the ethdev library to support hairpin between two ports.** > + > + New APIs are introduced to support binding / unbinding 2 ports hairpin= . > + Hairpin TX part flow rules can be inserted explicitly. >=20 > Removed Items > ------------- > @@ -240,6 +244,10 @@ ABI Changes >=20 > * ``ethdev`` internal functions are marked with ``__rte_internal`` tag= . >=20 > + * ``struct rte_eth_hairpin_conf`` has two new members: > + > + * ``uint32_t tx_explicit:1;`` > + * ``uint32_t manual_bind:1;`` >=20 > Known Issues > ------------ > diff --git a/doc/guides/testpmd_app_ug/run_app.rst > b/doc/guides/testpmd_app_ug/run_app.rst > index e2539f6..4e627c4 100644 > --- a/doc/guides/testpmd_app_ug/run_app.rst > +++ b/doc/guides/testpmd_app_ug/run_app.rst > @@ -497,3 +497,11 @@ The command line options are: > * ``--record-burst-stats`` >=20 > Enable display of RX and TX burst stats. > + > +* ``--hairpin-mode=3D0xXX`` > + > + Set the hairpin port mode with bitmask, only valid when hairpin queu= es > number is set. > + bit 4 - explicit TX flow rule > + bit 1 - two hairpin ports paired > + bit 0 - two hairpin ports loop > + The default value is 0. Hairpin will use single port mode and implic= it TX flow > mode. > -- > 1.8.3.1 Acked-by: Ori Kam <orika@nvidia.com> Thanks, Ori