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Fri, 30 Aug 2019 03:51:07 +0000 Received: from MN2PR18MB2877.namprd18.prod.outlook.com ([fe80::7cdd:71d0:6771:4bed]) by MN2PR18MB2877.namprd18.prod.outlook.com ([fe80::7cdd:71d0:6771:4bed%6]) with mapi id 15.20.2199.021; Fri, 30 Aug 2019 03:51:06 +0000 From: Anoob Joseph To: Akhil Goyal , Pablo de Lara CC: Ankur Dwivedi , Jerin Jacob Kollanukkaran , Narayana Prasad Raju Athreya , "dev@dpdk.org" Thread-Topic: [PATCH] common/cpt: add support for new firmware Thread-Index: AQHVUoSVZCdFSvwMNUa3OXryCyUXVacTJp6g Date: Fri, 30 Aug 2019 03:51:06 +0000 Message-ID: References: <1565775631-20264-1-git-send-email-anoobj@marvell.com> In-Reply-To: <1565775631-20264-1-git-send-email-anoobj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [223.230.89.3] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 659cfa6a-ac45-4f4a-613c-08d72cfd499e x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020); 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 659cfa6a-ac45-4f4a-613c-08d72cfd499e X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Aug 2019 03:51:06.7660 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3dKhJKPywvaF0qsVAn4gwcKgu5IZ48ylJbI/4Gr3fw9GEOmORRXWRo/U3JpjCHX0IEbnu7RPWzSke+X2X3eBOw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2461 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_01:2019-08-29,2019-08-30 signatures=0 Subject: Re: [dpdk-dev] [PATCH] common/cpt: add support for new firmware X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Akhil, Pablo, >From my end, this patch is good to go. Thanks, Anoob > -----Original Message----- > From: Anoob Joseph > Sent: Wednesday, August 14, 2019 3:11 PM > To: Akhil Goyal ; Pablo de Lara > > Cc: Ankur Dwivedi ; Jerin Jacob Kollanukkaran > ; Narayana Prasad Raju Athreya > ; dev@dpdk.org; Anoob Joseph > > Subject: [PATCH] common/cpt: add support for new firmware >=20 > From: Ankur Dwivedi >=20 > With the latest firmware, there are few changes for zuc and snow3g. >=20 > 1. The iv_source is present in bitfield 7 of minor opcode. In the old fir= mware this > was present in bitfield 6. >=20 > 2. Algorithm type is a 2 bit field in new firmware. In the old firmware i= t was > named as cipher type and it was a 1 bit field. >=20 > Signed-off-by: Ankur Dwivedi > Signed-off-by: Anoob Joseph > --- > drivers/common/cpt/cpt_mcode_defines.h | 4 ++-- > drivers/common/cpt/cpt_ucode.h | 6 ++++-- > 2 files changed, 6 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/common/cpt/cpt_mcode_defines.h > b/drivers/common/cpt/cpt_mcode_defines.h > index c0adbd5..b7c3feb 100644 > --- a/drivers/common/cpt/cpt_mcode_defines.h > +++ b/drivers/common/cpt/cpt_mcode_defines.h > @@ -303,8 +303,8 @@ struct cpt_ctx { > uint64_t hmac :1; > uint64_t zsk_flags :3; > uint64_t k_ecb :1; > - uint64_t snow3g :1; > - uint64_t rsvd :22; > + uint64_t snow3g :2; > + uint64_t rsvd :21; > /* Below fields are accessed by hardware */ > union { > mc_fc_context_t fctx; > diff --git a/drivers/common/cpt/cpt_ucode.h > b/drivers/common/cpt/cpt_ucode.h index 7d9c31e..0dac12e 100644 > --- a/drivers/common/cpt/cpt_ucode.h > +++ b/drivers/common/cpt/cpt_ucode.h > @@ -1467,7 +1467,8 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags, > opcode.s.major =3D CPT_MAJOR_OP_ZUC_SNOW3G; >=20 > /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ > - opcode.s.minor =3D ((1 << 6) | (snow3g << 5) | (0 << 4) | > + > + opcode.s.minor =3D ((1 << 7) | (snow3g << 5) | (0 << 4) | > (0 << 3) | (flags & 0x7)); >=20 > if (flags =3D=3D 0x1) { > @@ -1791,7 +1792,8 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags, > opcode.s.major =3D CPT_MAJOR_OP_ZUC_SNOW3G; >=20 > /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ > - opcode.s.minor =3D ((1 << 6) | (snow3g << 5) | (0 << 4) | > + > + opcode.s.minor =3D ((1 << 7) | (snow3g << 5) | (0 << 4) | > (0 << 3) | (flags & 0x7)); >=20 > /* consider iv len */ > -- > 2.7.4