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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW2PR12MB2538.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5d18a4ae-2090-433a-d747-08d9e19a811a X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Jan 2022 13:39:55.6087 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xWYhV84C7633wW/REENl943ERdSbtVSS0G0mF1k/WfDPXsnm5N7b260Sf33CcHvOnNEQWWv5RuVs3EfnpuNaYw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5687 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org [Public] Acked-by: Chandubabu Namburu -----Original Message----- From: ssebasti@amd.com =20 Sent: Tuesday, January 25, 2022 5:48 PM To: dev@dpdk.org Subject: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change From: Selwin Sebastian For each rate change command submission, the FW has to do a phy power off s= equence internally. For this to happen correctly, the PLL re-initialization= control setting has to be turned off before sending mailbox commands and r= e-enabled once the command submission is complete. Without the PLL control = setting, the link up takes longer time in a fixed phy configuration. Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 9 +++++++++ drivers/net/axgbe/axgbe_phy_impl.c | 22 ++++++++++++++++++++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_com= mon.h index df0aa21a9b..5a7ac35b6a 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1314,6 +1314,11 @@ #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056 #endif =20 +#ifndef MDIO_VEND2_PMA_MISC_CTRL0 +#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090 +#endif + + #ifndef MDIO_CTRL1_SPEED1G #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) #endif @@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr) return (addr >> 32) & 0x0ffffffff; } =20 +#define XGBE_PMA_PLL_CTRL_MASK BIT(15) +#define XGBE_PMA_PLL_CTRL_SET BIT(15) +#define XGBE_PMA_PLL_CTRL_CLEAR 0x0000 + /*END*/ =20 /* Bit setting and getting macros diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_p= hy_impl.c index 72104f8a3f..08d3484a11 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_po= rt *pdata) axgbe_phy_put_comm_ownership(pdata); } =20 +static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) { + XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, + XGBE_PMA_PLL_CTRL_MASK, + enable ? XGBE_PMA_PLL_CTRL_SET + : XGBE_PMA_PLL_CTRL_CLEAR); + + /* Wait for command to complete */ + rte_delay_us(150); +} + static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) { + /* Clear the PLL so that it helps in power down sequence */ + axgbe_phy_pll_ctrl(pdata, false); + /* Log if a previous command did not complete */ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); @@ -121= 3,10 +1227,14 @@ static void axgbe_phy_complete_ratechange(struct axgbe_por= t *pdata) wait =3D AXGBE_RATECHANGE_COUNT; while (wait--) { if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) - return; - + goto reenable_pll; rte_delay_us(1500); } + +reenable_pll: + /* Re-enable the PLL control */ + axgbe_phy_pll_ctrl(pdata, true); + PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); } =20 -- 2.25.1