From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1B786A04F9; Fri, 10 Jan 2020 10:09:32 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EA06D1E928; Fri, 10 Jan 2020 10:09:31 +0100 (CET) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2079.outbound.protection.outlook.com [40.107.92.79]) by dpdk.org (Postfix) with ESMTP id EFD5C1E920 for ; Fri, 10 Jan 2020 10:09:30 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NLO6kAiMySqTanfjIQgnEGWsSwkT1sN2eBiSCBV8YDWCCvNnCUHNMHsmM28nnNIYWdlvDxFhncf2IbP0A0Waf9fYXUcKl/HAFRN4742dcbyV3+5RreoGKD/S3jxEHbQRCKcBO51uxVAoiE3r9iJ3+EXnhezKG1BUiyBZJGJxQC3S8LGyBaPRU7Ph2ZHtSlvmKcpkxs0ZY+WMP4zbUMzV93rbDqMmieaITCmE+xDlsnB/7GzSdBfjk+k7wKbXxWiceUTjLEcmH+sb/aWgYMCyXdn1XgQ5BvFcndwx4IJ9qYQIP2bkb2GWpyYAt+VcpCFUw9c+lw4pILYsfEm7sT/XoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RVFxH0+o8O53h0ULu1XxRQfkAGL6qTtMDk1wUp73Fdw=; b=Y1FnTJOIU/HZUO6NyFqjIZu9f9C8AgN2yKppQi8JEfs/cWQJlAhOb0Zh2pF87pmEOA/IsXq/SL+JIeo/sCbSsEa2VVEtQhLwnjLig+yozqRT5B5z6MxzAWVskqhCq6sUjnFCj2431MccAtB22oMIs1XWAWAlXIRhDhe4Cp5Kr9S1civrF8pvOGp5irN/AknBn1nlTDcdq4p01XVyZyIP24GkEUbuyWtPLal8MCV6SXcmpBOsmeXkmraxQa+q2FYnvoBd2Z/hG72Qf2kO3wkKTYvQuq4IgXk9J5t8L+IKr1YlLhUJcWc7L4WxDrNs7cRLz2Lcq7SvWXG9fP+UFXhEQQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RVFxH0+o8O53h0ULu1XxRQfkAGL6qTtMDk1wUp73Fdw=; b=aifef87Gdo3Z7o9fLY6LHwbkzjDYcYvWbs2no0CxApOWfDF0v9UlQ/Z6O0Mmvg7qkFxCl+Fv2Qmqz9WZtFvwPeUN4Sx0Pa8VdJ4et7W23gQT5fz7r4lLxYk+U6PYAG6+OuoccVPnzXKz3P3w+Q3wQzPpQo97/grBBmVTiGLsCXc= Received: from MW2PR12MB2570.namprd12.prod.outlook.com (52.132.181.13) by MW2PR12MB2588.namprd12.prod.outlook.com (52.132.181.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2602.12; Fri, 10 Jan 2020 09:09:28 +0000 Received: from MW2PR12MB2570.namprd12.prod.outlook.com ([fe80::ec36:5d88:cc24:c660]) by MW2PR12MB2570.namprd12.prod.outlook.com ([fe80::ec36:5d88:cc24:c660%3]) with mapi id 15.20.2602.018; Fri, 10 Jan 2020 09:09:28 +0000 From: "Kumar, Ravi1" To: "Namburu, Chandu-babu" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v1] net/axgbe: enhance device stats reporting Thread-Index: AQHVtzMjFLqE04map0G+xUZth7XIZafjvDYw Date: Fri, 10 Jan 2020 09:09:28 +0000 Message-ID: References: <20191220124321.32415-1-cnamburu@amd.com> In-Reply-To: <20191220124321.32415-1-cnamburu@amd.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_Enabled=true; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_SetDate=2020-01-10T09:11:16Z; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_Method=Standard; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_Name=Internal Use Only - Unrestricted; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_ActionId=15d20330-2970-4d37-a8ab-0000efd5dc7f; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_ContentBits=1 msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_enabled: true msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_setdate: 2020-01-10T09:11:16Z msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_method: Standard msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_name: Internal Use Only - Unrestricted msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_siteid: 3dd8961f-e488-4e60-8e11-a82d994e183d msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_actionid: af19a1a7-d2db-4479-887b-0000d9dac4c9 msip_label_76546daa-41b6-470c-bb85-f6f40f044d7f_contentbits: 0 authentication-results: spf=none (sender IP is ) smtp.mailfrom=Ravi1.Kumar@amd.com; x-originating-ip: [165.204.157.251] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 270e0181-9811-4847-f805-08d795accc1b x-ms-traffictypediagnostic: MW2PR12MB2588:|MW2PR12MB2588: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; x-forefront-prvs: 02788FF38E x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(376002)(39860400002)(136003)(346002)(396003)(366004)(199004)(189003)(13464003)(64756008)(66476007)(9686003)(66556008)(71200400001)(66946007)(2906002)(8936002)(66446008)(110136005)(6506007)(8676002)(81166006)(316002)(81156014)(33656002)(76116006)(52536014)(186003)(7696005)(26005)(86362001)(5660300002)(30864003)(478600001)(55016002)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:MW2PR12MB2588; H:MW2PR12MB2570.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: H/GPK29L5VQp8Zl3F9BNW4+LQAgbhamU9U6UGzUMQbQwcedZp9miyIndYcF4hrO67RJmmgn6DLDBWV3TEnsWwlLzZtjRJmNsg3BSFWyCwzvC4lXP0ZkXOFqZIhmq5Rrh1MiwrBL7/eqh2HxK/UjYMXsy+GRkQ4Q7eUjy/yOqR5fUep0744f3gRWN6dNakE5AEy9rFkrENRdp/qA9UiFLW/Uf1FXlqus3Z/HPPxbrh35sZUtKUb/GtdFRTmKMc9UX6NWmQ9XR7FyTHLrCRizcUJJ89yJ3JHokv27V828tNn9FwRMnc6hyxRRHEj+1lBqjAMMiTe4bn+uoH1FwxKT1FZfOjomdhFm7WwciB5ykgwxfdlXQz2tZ3AHvCoTKFl9bJeXpnMen40DAeRzwRnh9YFVmopiIDxlZC/VAnSf5I27XbdqaeHeugzIqeik5RkSDGi5k0ULQ4by3UfG9iVT+OFlRhvrRxefkwRaiD4DKxStTZj73x5/Tx8bc7K9rRFzU Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 270e0181-9811-4847-f805-08d795accc1b X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jan 2020 09:09:28.6363 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XWLyStXLgezc6fVmoV9vINKAvicciXzLPf8wJ+wLM2ux7nC7eUyIQOmQGE/p0DkcNDfU4b3F1QRi80t7IvXK+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2588 Subject: Re: [dpdk-dev] [PATCH v1] net/axgbe: enhance device stats reporting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" [AMD Official Use Only - Internal Distribution Only] I have reviewed the patch and there are no issues. It can be merged. Regards, Ravi > > >-----Original Message----- >From: dev On Behalf Of cnamburu@amd.com >Sent: Friday, December 20, 2019 6:13 PM >To: dev@dpdk.org >Subject: [dpdk-dev] [PATCH v1] net/axgbe: enhance device stats reporting > >[CAUTION: External Email] > >From: Chandu Babu N > >Implements eth dev ops xstats_get, xstats_reset, xstats_get_names, xstats_= get_names_by_id, xstats_get_by_id > >Signed-off-by: Chandu Babu N >--- > drivers/net/axgbe/axgbe_dev.c | 15 ++ > drivers/net/axgbe/axgbe_ethdev.c | 408 +++++++++++++++++++++++++++++++ d= rivers/net/axgbe/axgbe_ethdev.h | 49 ++++ > drivers/net/axgbe/axgbe_rxtx.c | 1 + > drivers/net/axgbe/axgbe_rxtx.h | 1 + > 5 files changed, 474 insertions(+) > >diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c= index b1f0bbc8e..83089f20d 100644 >--- a/drivers/net/axgbe/axgbe_dev.c >+++ b/drivers/net/axgbe/axgbe_dev.c >@@ -1036,6 +1036,20 @@ static void axgbe_config_checksum_offload(struct ax= gbe_port *pdata) > AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); } > >+static void axgbe_config_mmc(struct axgbe_port *pdata) { >+ struct axgbe_mmc_stats *stats =3D &pdata->mmc_stats; >+ >+ /* Reset stats */ >+ memset(stats, 0, sizeof(*stats)); >+ >+ /* Set counters to reset on read */ >+ AXGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); >+ >+ /* Reset the counters */ >+ AXGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); } >+ > static int axgbe_init(struct axgbe_port *pdata) { > int ret; >@@ -1078,6 +1092,7 @@ static int axgbe_init(struct axgbe_port *pdata) > axgbe_config_flow_control(pdata); > axgbe_config_mac_speed(pdata); > axgbe_config_checksum_offload(pdata); >+ axgbe_config_mmc(pdata); > > return 0; > } >diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_et= hdev.c >index d1f160e79..750a768e4 100644 >--- a/drivers/net/axgbe/axgbe_ethdev.c >+++ b/drivers/net/axgbe/axgbe_ethdev.c >@@ -24,9 +24,79 @@ static int axgbe_dev_link_update(struct rte_eth_dev *de= v, static int axgbe_dev_stats_get(struct rte_eth_dev *dev, > struct rte_eth_stats *stats); static int = axgbe_dev_stats_reset(struct rte_eth_dev *dev); >+static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, >+ struct rte_eth_xstat *stats, >+ unsigned int n); static int=20 >+axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, >+ struct rte_eth_xstat_name *xstats_names, >+ unsigned int size); static int=20 >+axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, >+ const uint64_t *ids, >+ uint64_t *values, >+ unsigned int n); static int=20 >+axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, >+ struct rte_eth_xstat_name *xstats_names, >+ const uint64_t *ids, >+ unsigned int size); static int=20 >+axgbe_dev_xstats_reset(struct rte_eth_dev *dev); > static int axgbe_dev_info_get(struct rte_eth_dev *dev, > struct rte_eth_dev_info *dev_info); > >+struct axgbe_xstats { >+ char name[RTE_ETH_XSTATS_NAME_SIZE]; >+ int offset; >+}; >+ >+#define AXGMAC_MMC_STAT(_string, _var) \ >+ { _string, \ >+ offsetof(struct axgbe_mmc_stats, _var), \ >+ } >+ >+static const struct axgbe_xstats axgbe_xstats_strings[] =3D { >+ AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), >+ AXGMAC_MMC_STAT("tx_packets", txframecount_gb), >+ AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), >+ AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), >+ AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), >+ AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), >+ AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), >+ AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), >+ AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb)= , >+ AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb)= , >+ AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_g= b), >+ AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_g= b), >+ AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), >+ AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), >+ >+ AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), >+ AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), >+ AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), >+ AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), >+ AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), >+ AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), >+ AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), >+ AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), >+ AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb)= , >+ AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb)= , >+ AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_g= b), >+ AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_g= b), >+ AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), >+ AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), >+ AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), >+ AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), >+ AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), >+ AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), >+ AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), >+ AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), >+ AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), >+ AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), }; >+ >+#define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) >+ > /* The set of PCI devices this driver supports */ > #define AMD_PCI_VENDOR_ID 0x1022 > #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 @@ -89,6 +159,11 @@ static const = struct eth_dev_ops axgbe_eth_dev_ops =3D { > .link_update =3D axgbe_dev_link_update, > .stats_get =3D axgbe_dev_stats_get, > .stats_reset =3D axgbe_dev_stats_reset, >+ .xstats_get =3D axgbe_dev_xstats_get, >+ .xstats_reset =3D axgbe_dev_xstats_reset, >+ .xstats_get_names =3D axgbe_dev_xstats_get_names, >+ .xstats_get_names_by_id =3D axgbe_dev_xstats_get_names_by_id, >+ .xstats_get_by_id =3D axgbe_dev_xstats_get_by_id, > .dev_infos_get =3D axgbe_dev_info_get, > .rx_queue_setup =3D axgbe_dev_rx_queue_setup, > .rx_queue_release =3D axgbe_dev_rx_queue_release, >@@ -315,27 +390,359 @@ axgbe_dev_link_update(struct rte_eth_dev *dev, > return ret; > } > >+static void axgbe_read_mmc_stats(struct axgbe_port *pdata) { >+ struct axgbe_mmc_stats *stats =3D &pdata->mmc_stats; >+ >+ /* Freeze counters */ >+ AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); >+ >+ /* Tx counters */ >+ stats->txoctetcount_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); >+ stats->txoctetcount_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); >+ >+ stats->txframecount_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); >+ stats->txframecount_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); >+ >+ stats->txbroadcastframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); >+ stats->txbroadcastframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) <<=20 >+ 32); >+ >+ stats->txmulticastframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); >+ stats->txmulticastframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) <<=20 >+ 32); >+ >+ stats->tx64octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); >+ stats->tx64octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); >+ >+ stats->tx65to127octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); >+ stats->tx65to127octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->tx128to255octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); >+ stats->tx128to255octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->tx256to511octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); >+ stats->tx256to511octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->tx512to1023octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); >+ stats->tx512to1023octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->tx1024tomaxoctets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); >+ stats->tx1024tomaxoctets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->txunicastframes_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); >+ stats->txunicastframes_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) <<=20 >+ 32); >+ >+ stats->txmulticastframes_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); >+ stats->txmulticastframes_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) <<=20 >+ 32); >+ >+ stats->txbroadcastframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); >+ stats->txbroadcastframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) <<=20 >+ 32); >+ >+ stats->txunderflowerror +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); >+ stats->txunderflowerror +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); >+ >+ stats->txoctetcount_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); >+ stats->txoctetcount_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); >+ >+ stats->txframecount_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); >+ stats->txframecount_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); >+ >+ stats->txpauseframes +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); >+ stats->txpauseframes +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); >+ >+ stats->txvlanframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); >+ stats->txvlanframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); >+ >+ /* Rx counters */ >+ stats->rxframecount_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); >+ stats->rxframecount_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); >+ >+ stats->rxoctetcount_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); >+ stats->rxoctetcount_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); >+ >+ stats->rxoctetcount_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); >+ stats->rxoctetcount_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); >+ >+ stats->rxbroadcastframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); >+ stats->rxbroadcastframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) <<=20 >+ 32); >+ >+ stats->rxmulticastframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); >+ stats->rxmulticastframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) <<=20 >+ 32); >+ >+ stats->rxcrcerror +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); >+ stats->rxcrcerror +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); >+ >+ stats->rxrunterror +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); >+ >+ stats->rxjabbererror +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); >+ >+ stats->rxundersize_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); >+ >+ stats->rxoversize_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); >+ >+ stats->rx64octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); >+ stats->rx64octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); >+ >+ stats->rx65to127octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); >+ stats->rx65to127octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->rx128to255octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); >+ stats->rx128to255octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->rx256to511octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); >+ stats->rx256to511octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->rx512to1023octets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); >+ stats->rx512to1023octets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->rx1024tomaxoctets_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); >+ stats->rx1024tomaxoctets_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) <<=20 >+ 32); >+ >+ stats->rxunicastframes_g +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); >+ stats->rxunicastframes_g +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) <<=20 >+ 32); >+ >+ stats->rxlengtherror +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); >+ stats->rxlengtherror +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); >+ >+ stats->rxoutofrangetype +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); >+ stats->rxoutofrangetype +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); >+ >+ stats->rxpauseframes +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); >+ stats->rxpauseframes +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); >+ >+ stats->rxfifooverflow +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); >+ stats->rxfifooverflow +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); >+ >+ stats->rxvlanframes_gb +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); >+ stats->rxvlanframes_gb +=3D >+ ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); >+ >+ stats->rxwatchdogerror +=3D >+ AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); >+ >+ /* Un-freeze counters */ >+ AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); } >+ >+static int >+axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats= , >+ unsigned int n) >+{ >+ struct axgbe_port *pdata =3D dev->data->dev_private; >+ unsigned int i; >+ >+ if (!stats) >+ return 0; >+ >+ axgbe_read_mmc_stats(pdata); >+ >+ for (i =3D 0; i < n && i < AXGBE_XSTATS_COUNT; i++) { >+ stats[i].id =3D i; >+ stats[i].value =3D *(u64 *)((uint8_t *)&pdata->mmc_stats + >+ axgbe_xstats_strings[i].offset); >+ } >+ >+ return i; >+} >+ >+static int >+axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, >+ struct rte_eth_xstat_name *xstats_names, >+ unsigned int n) { >+ unsigned int i; >+ >+ if (n >=3D AXGBE_XSTATS_COUNT && xstats_names) { >+ for (i =3D 0; i < AXGBE_XSTATS_COUNT; ++i) { >+ snprintf(xstats_names[i].name, >+ RTE_ETH_XSTATS_NAME_SIZE, "%s", >+ axgbe_xstats_strings[i].name); >+ } >+ } >+ >+ return AXGBE_XSTATS_COUNT; >+} >+ >+static int >+axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, >+ uint64_t *values, unsigned int n) { >+ unsigned int i; >+ uint64_t values_copy[AXGBE_XSTATS_COUNT]; >+ >+ if (!ids) { >+ struct axgbe_port *pdata =3D dev->data->dev_private; >+ >+ if (n < AXGBE_XSTATS_COUNT) >+ return AXGBE_XSTATS_COUNT; >+ >+ axgbe_read_mmc_stats(pdata); >+ >+ for (i =3D 0; i < AXGBE_XSTATS_COUNT; i++) { >+ values[i] =3D *(u64 *)((uint8_t *)&pdata->mmc_stat= s + >+ axgbe_xstats_strings[i].offset); >+ } >+ >+ return i; >+ } >+ >+ axgbe_dev_xstats_get_by_id(dev, NULL, values_copy,=20 >+ AXGBE_XSTATS_COUNT); >+ >+ for (i =3D 0; i < n; i++) { >+ if (ids[i] >=3D AXGBE_XSTATS_COUNT) { >+ PMD_DRV_LOG(ERR, "id value isn't valid\n"); >+ return -1; >+ } >+ values[i] =3D values_copy[ids[i]]; >+ } >+ return n; >+} >+ >+static int >+axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, >+ struct rte_eth_xstat_name *xstats_names, >+ const uint64_t *ids, >+ unsigned int size) { >+ struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; >+ unsigned int i; >+ >+ if (!ids) >+ return axgbe_dev_xstats_get_names(dev, xstats_names,=20 >+ size); >+ >+ axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); >+ >+ for (i =3D 0; i < size; i++) { >+ if (ids[i] >=3D AXGBE_XSTATS_COUNT) { >+ PMD_DRV_LOG(ERR, "id value isn't valid\n"); >+ return -1; >+ } >+ strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].nam= e); >+ } >+ return size; >+} >+ >+static int >+axgbe_dev_xstats_reset(struct rte_eth_dev *dev) { >+ struct axgbe_port *pdata =3D dev->data->dev_private; >+ struct axgbe_mmc_stats *stats =3D &pdata->mmc_stats; >+ >+ /* MMC registers are configured for reset on read */ >+ axgbe_read_mmc_stats(pdata); >+ >+ /* Reset stats */ >+ memset(stats, 0, sizeof(*stats)); >+ >+ return 0; >+} >+ > static int > axgbe_dev_stats_get(struct rte_eth_dev *dev, > struct rte_eth_stats *stats) { > struct axgbe_rx_queue *rxq; > struct axgbe_tx_queue *txq; >+ struct axgbe_port *pdata =3D dev->data->dev_private; >+ struct axgbe_mmc_stats *mmc_stats =3D &pdata->mmc_stats; > unsigned int i; > >+ axgbe_read_mmc_stats(pdata); >+ >+ stats->imissed =3D mmc_stats->rxfifooverflow; >+ > for (i =3D 0; i < dev->data->nb_rx_queues; i++) { > rxq =3D dev->data->rx_queues[i]; > stats->q_ipackets[i] =3D rxq->pkts; > stats->ipackets +=3D rxq->pkts; > stats->q_ibytes[i] =3D rxq->bytes; > stats->ibytes +=3D rxq->bytes; >+ stats->rx_nombuf +=3D rxq->rx_mbuf_alloc_failed; >+ stats->q_errors[i] =3D rxq->errors + rxq->rx_mbuf_alloc_fa= iled; >+ stats->ierrors +=3D rxq->errors; > } >+ > for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > txq =3D dev->data->tx_queues[i]; > stats->q_opackets[i] =3D txq->pkts; > stats->opackets +=3D txq->pkts; > stats->q_obytes[i] =3D txq->bytes; > stats->obytes +=3D txq->bytes; >+ stats->oerrors +=3D txq->errors; > } > > return 0; >@@ -353,6 +760,7 @@ axgbe_dev_stats_reset(struct rte_eth_dev *dev) > rxq->pkts =3D 0; > rxq->bytes =3D 0; > rxq->errors =3D 0; >+ rxq->rx_mbuf_alloc_failed =3D 0; > } > for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > txq =3D dev->data->tx_queues[i]; diff --git a/drivers/net/= axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h >index e3cfaf36f..a1083b17b 100644 >--- a/drivers/net/axgbe/axgbe_ethdev.h >+++ b/drivers/net/axgbe/axgbe_ethdev.h >@@ -438,6 +438,53 @@ struct axgbe_version_data { > unsigned int an_cdr_workaround; > }; > >+struct axgbe_mmc_stats { >+ /* Tx Stats */ >+ uint64_t txoctetcount_gb; >+ uint64_t txframecount_gb; >+ uint64_t txbroadcastframes_g; >+ uint64_t txmulticastframes_g; >+ uint64_t tx64octets_gb; >+ uint64_t tx65to127octets_gb; >+ uint64_t tx128to255octets_gb; >+ uint64_t tx256to511octets_gb; >+ uint64_t tx512to1023octets_gb; >+ uint64_t tx1024tomaxoctets_gb; >+ uint64_t txunicastframes_gb; >+ uint64_t txmulticastframes_gb; >+ uint64_t txbroadcastframes_gb; >+ uint64_t txunderflowerror; >+ uint64_t txoctetcount_g; >+ uint64_t txframecount_g; >+ uint64_t txpauseframes; >+ uint64_t txvlanframes_g; >+ >+ /* Rx Stats */ >+ uint64_t rxframecount_gb; >+ uint64_t rxoctetcount_gb; >+ uint64_t rxoctetcount_g; >+ uint64_t rxbroadcastframes_g; >+ uint64_t rxmulticastframes_g; >+ uint64_t rxcrcerror; >+ uint64_t rxrunterror; >+ uint64_t rxjabbererror; >+ uint64_t rxundersize_g; >+ uint64_t rxoversize_g; >+ uint64_t rx64octets_gb; >+ uint64_t rx65to127octets_gb; >+ uint64_t rx128to255octets_gb; >+ uint64_t rx256to511octets_gb; >+ uint64_t rx512to1023octets_gb; >+ uint64_t rx1024tomaxoctets_gb; >+ uint64_t rxunicastframes_g; >+ uint64_t rxlengtherror; >+ uint64_t rxoutofrangetype; >+ uint64_t rxpauseframes; >+ uint64_t rxfifooverflow; >+ uint64_t rxvlanframes_gb; >+ uint64_t rxwatchdogerror; >+}; >+ > /* > * Structure to store private data for each port. > */ >@@ -576,6 +623,8 @@ struct axgbe_port { > int crc_strip_enable; > /* csum enable to hardware */ > uint32_t rx_csum_enable; >+ >+ struct axgbe_mmc_stats mmc_stats; > }; > > void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); diff --git = a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index cfc= 55b359..96055c25b 100644 >--- a/drivers/net/axgbe/axgbe_rxtx.c >+++ b/drivers/net/axgbe/axgbe_rxtx.c >@@ -229,6 +229,7 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_p= kts, > (unsigned int)rxq->queue_id); > rte_eth_devices[ > rxq->port_id].data->rx_mbuf_alloc_failed++= ; >+ rxq->rx_mbuf_alloc_failed++; > break; > } > pidx =3D idx + 1; >diff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx= .h index 917da58ce..a21537df9 100644 >--- a/drivers/net/axgbe/axgbe_rxtx.h >+++ b/drivers/net/axgbe/axgbe_rxtx.h >@@ -91,6 +91,7 @@ struct axgbe_rx_queue { > uint64_t pkts; > uint64_t bytes; > uint64_t errors; >+ uint64_t rx_mbuf_alloc_failed; > /* Number of mbufs allocated from pool*/ > uint64_t mbuf_alloc; > >-- >2.17.1