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List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Amit Prakash Shukla > Sent: Wednesday, October 18, 2023 12:24 AM > To: Vamsi Krishna Attunuru > Cc: dev@dpdk.org; Jerin Jacob Kollanukkaran ; > fengchengwen@huawei.com; kevin.laatz@intel.com; > bruce.richardson@intel.com; conor.walsh@intel.com; g.singh@nxp.com; > sachin.saxena@oss.nxp.com; hemant.agrawal@nxp.com; > cheng1.jiang@intel.com; Nithin Kumar Dabilpuram > ; Anoob Joseph ; > mb@smartsharesystems.com; Amit Prakash Shukla > > Subject: [PATCH v2] dma/cnxk: offload source buffer free >=20 > Added support in driver, to offload source buffer free to hardware on > completion of DMA transfer. >=20 > Signed-off-by: Amit Prakash Shukla > --- > v2: > - Patch rebased. >=20 > v1: > - Driver implementation from RFC. >=20 Acked-by: Vamsi Attunuru > drivers/dma/cnxk/cnxk_dmadev.c | 48 > +++++++++++++++++++++++++++---- > drivers/dma/cnxk/cnxk_dmadev_fp.c | 8 +++--- > 2 files changed, 46 insertions(+), 10 deletions(-) >=20 > diff --git a/drivers/dma/cnxk/cnxk_dmadev.c > b/drivers/dma/cnxk/cnxk_dmadev.c index 26680edfde..1e7f49792c 100644 > --- a/drivers/dma/cnxk/cnxk_dmadev.c > +++ b/drivers/dma/cnxk/cnxk_dmadev.c > @@ -16,7 +16,8 @@ cnxk_dmadev_info_get(const struct rte_dma_dev > *dev, struct rte_dma_info *dev_inf > dev_info->nb_vchans =3D dpivf->num_vchans; > dev_info->dev_capa =3D RTE_DMA_CAPA_MEM_TO_MEM | > RTE_DMA_CAPA_MEM_TO_DEV | > RTE_DMA_CAPA_DEV_TO_MEM | > RTE_DMA_CAPA_DEV_TO_DEV | > - RTE_DMA_CAPA_OPS_COPY | > RTE_DMA_CAPA_OPS_COPY_SG; > + RTE_DMA_CAPA_OPS_COPY | > RTE_DMA_CAPA_OPS_COPY_SG | > + RTE_DMA_CAPA_M2D_AUTO_FREE; > dev_info->max_desc =3D CNXK_DPI_MAX_DESC; > dev_info->min_desc =3D CNXK_DPI_MIN_DESC; > dev_info->max_sges =3D CNXK_DPI_MAX_POINTER; @@ -115,9 > +116,26 @@ cnxk_dmadev_configure(struct rte_dma_dev *dev, const struct > rte_dma_conf *conf, > return 0; > } >=20 > -static void > +static int > +dmadev_src_buf_aura_get(struct rte_mempool *sb_mp, const char > +*mp_ops_name) { > + struct rte_mempool_ops *ops; > + > + if (sb_mp =3D=3D NULL) > + return 0; > + > + ops =3D rte_mempool_get_ops(sb_mp->ops_index); > + if (strcmp(ops->name, mp_ops_name) !=3D 0) > + return -EINVAL; > + > + return roc_npa_aura_handle_to_aura(sb_mp->pool_id); > +} > + > +static int > cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct > rte_dma_vchan_conf *conf) { > + int aura; > + > header->cn9k.pt =3D DPI_HDR_PT_ZBW_CA; >=20 > switch (conf->direction) { > @@ -140,6 +158,11 @@ cn9k_dmadev_setup_hdr(union > cnxk_dpi_instr_cmd *header, const struct rte_dma_vch > header->cn9k.func =3D conf->dst_port.pcie.pfid << 12; > header->cn9k.func |=3D conf->dst_port.pcie.vfid; > } > + aura =3D dmadev_src_buf_aura_get(conf- > >auto_free.m2d.pool, "cn9k_mempool_ops"); > + if (aura < 0) > + return aura; > + header->cn9k.aura =3D aura; > + header->cn9k.ii =3D 1; > break; > case RTE_DMA_DIR_MEM_TO_MEM: > header->cn9k.xtype =3D DPI_XTYPE_INTERNAL_ONLY; @@ - > 153,11 +176,15 @@ cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd > *header, const struct rte_dma_vch > header->cn9k.fport =3D conf->dst_port.pcie.coreid; > header->cn9k.pvfe =3D 0; > }; > + > + return 0; > } >=20 > -static void > +static int > cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct > rte_dma_vchan_conf *conf) { > + int aura; > + > header->cn10k.pt =3D DPI_HDR_PT_ZBW_CA; >=20 > switch (conf->direction) { > @@ -180,6 +207,10 @@ cn10k_dmadev_setup_hdr(union > cnxk_dpi_instr_cmd *header, const struct rte_dma_vc > header->cn10k.func =3D conf->dst_port.pcie.pfid << > 12; > header->cn10k.func |=3D conf->dst_port.pcie.vfid; > } > + aura =3D dmadev_src_buf_aura_get(conf- > >auto_free.m2d.pool, "cn10k_mempool_ops"); > + if (aura < 0) > + return aura; > + header->cn10k.aura =3D aura; > break; > case RTE_DMA_DIR_MEM_TO_MEM: > header->cn10k.xtype =3D DPI_XTYPE_INTERNAL_ONLY; @@ - > 193,6 +224,8 @@ cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd > *header, const struct rte_dma_vc > header->cn10k.fport =3D conf->dst_port.pcie.coreid; > header->cn10k.pvfe =3D 0; > }; > + > + return 0; > } >=20 > static int > @@ -204,16 +237,19 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev > *dev, uint16_t vchan, > union cnxk_dpi_instr_cmd *header; > uint16_t max_desc; > uint32_t size; > - int i; > + int i, ret; >=20 > RTE_SET_USED(conf_sz); >=20 > header =3D (union cnxk_dpi_instr_cmd *)&dpi_conf->cmd.u; >=20 > if (dpivf->is_cn10k) > - cn10k_dmadev_setup_hdr(header, conf); > + ret =3D cn10k_dmadev_setup_hdr(header, conf); > else > - cn9k_dmadev_setup_hdr(header, conf); > + ret =3D cn9k_dmadev_setup_hdr(header, conf); > + > + if (ret) > + return ret; >=20 > /* Free up descriptor memory before allocating. */ > cnxk_dmadev_vchan_free(dpivf, vchan); > diff --git a/drivers/dma/cnxk/cnxk_dmadev_fp.c > b/drivers/dma/cnxk/cnxk_dmadev_fp.c > index 16d7b5426b..95df19a2db 100644 > --- a/drivers/dma/cnxk/cnxk_dmadev_fp.c > +++ b/drivers/dma/cnxk/cnxk_dmadev_fp.c > @@ -252,7 +252,7 @@ cnxk_dmadev_copy(void *dev_private, uint16_t > vchan, rte_iova_t src, rte_iova_t d > CNXK_DPI_STRM_INC(dpi_conf->c_desc, tail); >=20 > cmd[0] =3D (1UL << 54) | (1UL << 48); > - cmd[1] =3D dpi_conf->cmd.u; > + cmd[1] =3D dpi_conf->cmd.u | ((flags & > RTE_DMA_OP_FLAG_AUTO_FREE) << > +37); > cmd[2] =3D (uint64_t)comp_ptr; > cmd[4] =3D length; > cmd[6] =3D length; > @@ -308,7 +308,7 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t > vchan, const struct rte_dma_sge > comp_ptr =3D dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail]; > CNXK_DPI_STRM_INC(dpi_conf->c_desc, tail); >=20 > - hdr[1] =3D dpi_conf->cmd.u; > + hdr[1] =3D dpi_conf->cmd.u | ((flags & > RTE_DMA_OP_FLAG_AUTO_FREE) << > +37); > hdr[2] =3D (uint64_t)comp_ptr; >=20 > /* > @@ -365,7 +365,7 @@ cn10k_dmadev_copy(void *dev_private, uint16_t > vchan, rte_iova_t src, rte_iova_t >=20 > cmd[0] =3D dpi_conf->cmd.u | (1U << 6) | 1U; > cmd[1] =3D (uint64_t)comp_ptr; > - cmd[2] =3D 0; > + cmd[2] =3D (1UL << 47) | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) > << 43); > cmd[4] =3D length; > cmd[5] =3D src; > cmd[6] =3D length; > @@ -412,7 +412,7 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t > vchan, const struct rte_dma_sge >=20 > hdr[0] =3D dpi_conf->cmd.u | (nb_dst << 6) | nb_src; > hdr[1] =3D (uint64_t)comp_ptr; > - hdr[2] =3D 0; > + hdr[2] =3D (1UL << 47) | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << > 43); >=20 > rc =3D __dpi_queue_write_sg(dpivf, hdr, src, dst, nb_src, nb_dst); > if (unlikely(rc)) { > -- > 2.25.1