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Thu, 2 Jul 2020 20:30:28 +0000 From: "Carrillo, Erik G" To: Phil Yang , "dev@dpdk.org" CC: "jerinj@marvell.com" , "Honnappa.Nagarahalli@arm.com" , "drc@linux.vnet.ibm.com" , "Ruifeng.Wang@arm.com" , "Dharmik.Thakkar@arm.com" , "nd@arm.com" Thread-Topic: [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics Thread-Index: AQHWUDGr4gDsUEu8kkqWn/npY4B686j0voOg Date: Thu, 2 Jul 2020 20:30:28 +0000 Message-ID: References: <1591960798-24024-1-git-send-email-phil.yang@arm.com> <1593667604-12029-1-git-send-email-phil.yang@arm.com> <1593667604-12029-4-git-send-email-phil.yang@arm.com> In-Reply-To: <1593667604-12029-4-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.55.52.205] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d0741cc3-abcb-4e4a-d265-08d81ec6c26c x-ms-traffictypediagnostic: MWHPR11MB1343: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:813; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR1101MB2127.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0741cc3-abcb-4e4a-d265-08d81ec6c26c X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Jul 2020 20:30:28.5935 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PqVV3eC7ozvpg+/nWMahG1XhIZ7X3ZR9lRj3mqnDDltAvwAm/cfIx91tho/Ysyc/DqXQhtPa9GUwpW++0yeYfW+QrGBZ0LGSDsdyXpgLU94= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1343 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang > Sent: Thursday, July 2, 2020 12:27 AM > To: Carrillo, Erik G ; dev@dpdk.org > Cc: jerinj@marvell.com; Honnappa.Nagarahalli@arm.com; > drc@linux.vnet.ibm.com; Ruifeng.Wang@arm.com; > Dharmik.Thakkar@arm.com; nd@arm.com > Subject: [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics >=20 > The implementation-specific opaque data is shared between arm and cancel > operations. The state flag acts as a guard variable to make sure the upda= te of > opaque data is synchronized. This patch uses c11 atomics with explicit on= e > way memory barrier instead of full barriers rte_smp_w/rmb() to synchroniz= e > the opaque data between timer arm and cancel threads. >=20 > Signed-off-by: Phil Yang > Reviewed-by: Dharmik Thakkar > Reviewed-by: Ruifeng Wang Acked-by: Erik Gabriel Carrillo